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Trailing-Edge - PDP-10 Archives - ks_diag_gs - diagnostics/dsrma.sav
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DSRMA	DECSYSTEM 2020 RM03-RH11 BASIC DRIVE DIAGNOSTIC
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CAUTION - - MOUNT SCRATCH PACK(S) BEFORE RUNNING.
THIS DIAG. WRITES THE PACK.
**********

DUAL PORT TESTS DO NOT WRITE THE PACK

ALL DRIVES BEING TESTED SHOULD BE LOCKED ON PROPER PORT
WITH DEVICE SELECT PLUG INSTALLED
UNLESS INSTRUCTED OTHERWISE ...

RECONFIGURE ?   @
REMOVE (AC) POWER FROM THE DRIVE
RESTORE (AC) POWER TO DRIVE AND LOAD HEADS IF POSSIBLEDEVICE SELECTION PROBLEM EXISTSREFER TO LISTING BEFORE REPLACING ANYTHINGDEMAND-TRANSFER HANDSHAKE FAILURECHECK FOR LOOSE ADDRESS PLUGACANNOT READ 0'S ON CONTROL BUS C00-C15READING REG13 DOES NOT RETURN COMP OF 1'S WRITTENCAN'T READ 1'S ON CONTROL BUS C00-C15@DRIVE TYPE REGISTER (REG-06) FAILURETYPES 20024 & 24024 ARE ACCEPTABLECAN'T WRITE 1'S OVER CONTROL BUT C00-C15eBSEE LISTING FOR TEST DETAILSCAN'T WRITE 0'S OVER CONTROL BUS C00-C15}8eJRHCLR NOT RESETTING ALL BITS IN HOLDING REGISTERDATA WRITTEN =
DATA EXPECTED=
DATA  READ   =CAN'T FLOAT DATA ON CONTROL BUS C00-C15POSSIBLY! DATA PATH BITS CROSS COUPLEDPARITY LOGIC FAILURE{He_CAN'T GENERATE ODD PARITY WHEN DATA HAS EVEN # OF 1'SCAN'T GENERATE CORRECT PARITY WHEN DATA HAS ODD # OF 1'SPARITY ERROR -- PARITY NETWORK FAILURERESPONDS INCORRECTLY TO NETWORK TEST PATTERNCONTROL REGISTER FAULT BITS C11, C12REG-00 DATA SHOULD BE C11=1, C12=0GO-BIT (REG-00 C00) NOT CLEARING WITH RHCLR(3GREG-00 C0-C05 SHOULD BE =|0fREG-00 C00-C05 DATA FAILUREREG-00 C00-C05 WERE CHANGED FROM 0 BY
WRITING 70 TO C00-C05 OF REG #REGISTER SELECTION FAULTREG-15 C00-C02,C04-C06,C08-C09 SHOULD BE 0PERSISTANT DBPE, REG-15 C03PERSISTANT REGISTER-15 ERROR. ONE OR MORE OF THESE:C10(LOS-BC),C11(LOS-SC),C12(INVCMD)`f C07(DEV-CK),C14(SKI)sHf#PERSISTANT "OPE" REG-15 C13CAN'T WRITE 1'S TO REG-15 IMPLEMENTED BITSDATA SHOULD BE = 076210CAN'T CLEAR ALL REG-15 BY WRITING 0'S TO ITCAN'T CLEAR ALL REG-15 BITS WITH RHCLR45REG-15 DATA SHOULD BE=CAN'T TRANSFER PATTERNS TO AND FROM REG-15REG-12 FAULT C10-C15 SHOULD BE 0CAN'T WRITE 1'S TO C00-C09 OF REG-12CAN'T WRITE 0'S TO C00-C09 OF REG-12(REGISTER DATA SHOULD BE=CAN'T FLOAT PATTERNS TO REG-12 C00-C09REG-11 (C00-C06,C09-C10,C13-C15) SHOULD BE 0CAN'T WRITE 1'S TO REG-11 C07,C10-C12CAN'T WRITE 0'S TO REG-11 C07,C10-C12@52CAN'T FLOAT PATTERNS IN REG-11 IMPLEMENTED BITSRHCLR IS CLEARING BITS IN REG-11CAN'T WRITE 1'S TO C00-C15 OF REG-05RHCLR CAUSING REG-05 BITS TO CLEAR. IT SHOULD NOTSUSPECT REGISTER SELECTION PROBLEMCAN'T WRITE 0'S TO C00-C15 OF REG-05CAN'T FLOAT PATTERNS TO C00-C15 OF REG-05RHCLR WON'T CLEAR REG-02, C03 "PAR-ER"RHCLR WON'T CLEAR PAR-ER (C03 REG-02)WRITING REG-05 HAS CAUSED PAR-ER (C03 REG-02)@g$H}1RHCLR WON'T CLEAR PAR-ER C03 REG-02|(gWRITING PATTERNS TO REG-05 HAS CAUSED PAR-ERCAN'T WRITE A 1 TO C03 REG-02CAN'T WRITE A 0 TO C03 REG-02RHCLR WILL NOT RESET C03 REG-021 OR MORE OF THE FOLLOWING REG-02 BITS STUCK SETPAR-ER,FMT-ER,WCLK-F,ECH,HCE,DCKILF,ILR,RMR,AOE,IAEWLE,DTE,OPIUNSAFEFAULTY POWER MONITOR CKTSg)HCRCCAN'T WRITE 1'S TO C00-C15 OF REG-02RHCLR WON'T CLEAR C00-C15 OF REG-02}`g2CAN'T WRITE 0'S TO C00-C15 OF REG-02CAN'T FLOAT PATTERNS DOWN C00-C15 OF REG-02DRIVE DID NOT DETECT PARITY ERROR (C03 REG-02)DIAG WROTE 0'S TO REG-00 AND INCORRECT PARITY}gDREADING REGISTER-HAS CAUSED ILR (C01 REG-02)HAS FAILED TO SET ILR (C01 REG-02)C14 REG-01 "ERROR" SET WITH NO ERRORS IN DRIVEH45"ERROR" C14 REG-01 NOT SET WITH SOME ERROR CONDITIONRHCLR WON'T CLEAR M-MODE C00 REG-03|hg\CAN'T WRITE A 1 TO C00 OF REG-03CAN'T WRITE A 0 TO C00 OF REG-03CAN'T CLEAR C00 OF REG-03 WITH RHCLRZREGISTER INTERFERENCE PROBLEM
WRITING 0'S TO REG- HAS CAUSED REG-
TO BE MODIFIED. THIS REGISTER WAS WRITTEN INITIALLY WITH DATA= ~gvISSUING DRIVE CLEAR WITHOUT GO-BIT HAS CAUSED AN ERRORISSUING DRV CLR WITHOUT "GO", HAS SET "GO"ISSUING DRV-CLR WITHOUT THE GO BIT HAS CAUSED}hBITS IN ER1 TO CLEAR (IT SHOULD BE 177777)DRIVE CLEAR FAILED TO CLEAR C00-C15 REG-02DEVICE SELECTION FAULTISSUING A DRIVE CLEAR TO DRIVE- HAS CAUSED REG-02 IN DRIVE-
TO BE MODIFIED FROM ITS INITIAL STATE (177777)
~hhISSUING A NO-OP HAS HUNG THE GO-BIT C00 REG-00ISSUING A NO-OP HAS CAUSED "ERROR" REG-01 C14{Hh'DEBENB (C14 REG-03) NOT STOPPING U-SEQTHE GO BIT SHOULD BE SET WITH U-SEQ STOPPEDGO-BIT SHOULD BE CLEARDEBCLK (C15 REG-03) NOT STEPPING U-SEQMAINT MODE LOGIC FAULTC00 & C14 OF REG-03 NOT INTERLOCKED PROPERLY"GO" SHOULD BE = 0WHEN GO=0, C07 REG-01 DRY SHOULD BE 1WHEN GO=1, C07 REG01 DRY SHOULD BE 0"PIP" C13 REG-03 APPEARS STUCK AT 1yhK"PIP" C13 REG-03 SHOULD BE 1 WHEN GOING INTO DIAG MODEPROBLEM WITH "PIP" C13 REG-01 IN MAINT MODEWRITING A 1 TO C08 REG-03 "ON-CYL" SHOULD CLEAR "PIP"GOING INTO MAINT MODE SHOULD CAUSE MOL=0 (C12 REG-01)WRITING "UN-RDY" IN MAINT REG (C09 REG-03)SHOULD CAUSE MOL=1 (C12 REG-01)WRL C11 REG-01 SHOULD BE 0 WHEN GOING INTO MAINT MODECAN'T SET WRL C11 REG-01 BY WRITING W-PROT C03 REG-03AFTER GOING INTO MAINT MODE, (C14,C07 REG-15) SHOULD BE 0WRITING C07,C06 OF REG-03 WITH 1'S SHOULD CAUSEREG-15 C14,C07 TO SET "SKI" AND "DEV-CK"}8iDEV-CK (C07 REG-15), SHOULD CAUSE UNSAFE (C14 REG-02)FAULTY REG-03 LOGIC HAS CAUSED INCORRECT STATUSSHOULD HAVE: M-MODE=1,PIP=1,WRL=0,MOL=0,DEV-CK=0,SKI=0TOGGLING "MOL" VIA MAINT REG DID NOT SET VV=00iISSUING A PACK ACKNOWLEDGE COMMAND CAUSED AN ERROR~iISSUING A PACK ACKNOWLEDGE HAS HUNG THE GO-BITISSUING A PACK ACKNOWLEDGE DID NOT SET VV=1ISSUING READIN PRESET HAS CAUSED A COMPOSITE ERROR~Hi,ISSUING READIN PRESET HAS HUNG THE GO-BITISSUING READIN PRESET DID NOT SET VV=1C08 REG-01 "DPR" SHOULD BE A 1Pi8"PGM" C09 REG-01 SHOULD BE A 0~ i;COULD BE PORT SELECT SWITCH OR PULL-UP PROBLEMISSUING READIN PRESET HAS CAUSED COMPOSITE ERRORREADIN PRESET SHOULD CLEAR REG-05,REG-128iJREADIN PRESET SHOULD CLEAR REG-11 C07,C10-C128iOISSUING OFFSET COMMAND CAUSED COMPOSITE ERROR8iTISSUING AN OFFSET COMMAND HAS HUNG THE GO-BIT0iYAN OFFSET COMMAND SHOULD SET "OFS-MD" (C00 REG-01)~hi^WRITING REG-12 "DCY" SHOULD CLEAR "OFS-MD" C00 REG-01ISSUING OFFSET CMD WITH VV=0 DID NOT SET|(ihC12 REG-15 "INVCMD"ISSUING A NO-OP WITH WRONG PARITY SHOULD CAUSE"PAR-ER" C03 REG-02ISSUING A NO-OP WITH INCORRECT PARITY SHOULDINHIBIT SETTING OF THE GO-BITISSUING A NO-OP WITH INCORRECT PARITY HAS CAUSED"DBPE" C03 REG-15 TO SETWRITING REG-03 OR REG-04 WITH "GO" SET HAS CAUSED "RMR"~ jWRITING REG-05 WHILE GO=1 FAILED TO CAUSE "RMR" C02 REG-02"RMR" DID NOT INHIBIT WRITING OF REGISTER-05THE REGISTER DATA SHOULD BE = 17777uhjISSUING A SEEK COMMAND HAS CAUSED AN ERRORISSUING A SEEK COMMAND FAILED TO SET "GO"FAILED TO CAUSE "IAE" C10 REG-02WITH A SEEK TO ILLEGAL CYLINDER #

SEEKOTOSANLEGALAADDRESSKHAS CAUSEDLIAEHSEEK1TO ILLEGAL ADR FAILED TO CAUSE "IAE" C10 REG-02RHCLR FAILED TO RESET "ATTN" C15 REG-01CAUSING AN "ERROR" DID NOT SET "ATTN" C15 REG-01ATTN AND STATUS KSDMP FOR THIS RH:PROBLEM WITH PSEUDO ATTN POSITION LOGIC HAS BEEN DETECTEDTHE ATTN REGISTER SHOULD BE ASSERTING A 1 IN THE BIT POSITIONFOR THE DRIVE BEING TESTED ONLY.  ALL OTHERS SHOULD BE 0REFER TO LISTING IF MODULE REPLACEMENT FAILSCAN'T CLEAR ATTN BY WRITING PSEUDO ATTN BIT FOR THIS DRIVEATTN CLEARED BY WRITING REG-04 WITH DRIVE RESPONDING TO WRONG PSEUDO ATTN BITFAILURE TO CLEAR "ATTN" WITH A DRIVE CLEAR COMMAND~jgSETTING GO (WITHOUT COMP ERR) FAILED TO CLEAR "ATTN"WRITING REG-00 WHILE "ERROR"=1 FAILED TO SET "ATTN"TOGGLING "MOL" (IN DIAG MODE) FAILED TO SET "ATTN"}0jwISSUING A NO-OP WHILE "ERROR"=1 FAILED TO SET "ATTN"ISSUING NO-OP WHILE "ERROR"=0 HAS CAUSED "ATTN"  FOLLOWING RHCLR SOME DRIVE STILL SENDING "ATTN" TO RHIF MODULE REPLACEMENT FAILS, REFER TO LISTING{`k
DRIVE SHOULD BE POWERED UP WITH UNIT SELECT PLUG INSERTED
REMOVE THE UNIT SELECT PLUG
RE-INSERT THE UNIT SELECT PLUGDEMAND-TRANSFER HANDSHAKE FAILURE READING STATUSSUSPECT LOOSE UNITY SELECT PLUG OR FAULTY SWITCHHANDSHAKE COMPLETED, EVEN WITH UNIT SELECT PLUG REMOVED{0k/POSSIBLE FAULTY UNIT SELECT SWITCH IN DRIVECONTROLLER SEES "ATTN" WHILE UNIT SELECT REMOVEDHANDSHAKE FAILURE AFTER RE-INSERTING UNIT SELECT PLUGPLUG PROBABLY NOT SEATED PROPERLY. TRY AGAIN!!COULD ALSO BE AN INTERMITTANT UNIT SELECT SWITCHFAILURE TO GET "OPE" (C13 REG-15) AFTER REMOVINGAND RE-INSERTING THE UNIT SELECT PLUG}
DIAGNOSTIC DETECTS THAT}hkUIS WRITE PROTECTED
IS THIS CORRECT?
PLACE WRITE PROTECT SWITCH IN THE OTHER STATEWRITE PROTECT TEST, STATUS ERRORHITTING WRITE PROTECT FAILED TO CHANGE STATUSx`kgCOULD ALSO BE A FAULTY SWITCH IS THIS CORRECT?
HARDWARE STATUS INDICATES DRIVE IS SINGLE PORTEDHARDWARE STATUS INDICATES DRIVE IS DUAL PORTEDOPERATOR INPUT DISAGREES WITH DRIVE TYPE (REG-06) DATACOULD BE MISSNG BACKPLANE JUMPER FOR REG-06
DIAG DETECTS MOL=1 IS THIS CORRECT
USING START-STOP SWITCH, CYCLE DRIVE OFF-LINE
DIAG DETECTS MOL=0 IS THIS CORRECT
USING START-STOP SWITCH, CYCLE DRIVE ON-LINEHARDWARE STATUS AND OPERATOR DISAGREEINCORRECT STATUS FOLLOWING CYCLE-DOWNSHOULD HAVE MOL=0 AND ERROR=0INCORRECT STATUS FOLLOWING CYCLE-UPl!SHOULD HAVE MOL=1 AND ERROR=0
USING PORT SELECT SWITCH, SWITCH TO PRIMARY PORT~8l*
SWITCH THE PORT SELECT SWITCH FROM PRIMARY PORT TO A/B 
USING THE PORT SELECT SWITCH, SWITCH FROM A/B TO SECONDARY PORT l7
USING START-STOP SWITCH, CYCLE DRIVE OFF THEN BACK ON LINE~8l=
SWITCH THE PORT SELECT SWITCH FROM WHEREVER IT IS, TO THE PRIMARY PORT
AND CYCLE DRIVE DOWN AND UP USING START-STOP SWITCH~HlJ
CANNOT EXIT THIS TEST UNTIL IT WORKS. DUAL PORT LOGIC HAS BROKEN
TOGGLING MOL WHILE ON PRIMARY PORT CAUSED RAE}hlVFAULTY PORT SELECT SWITCH OR ITS INTERCONNECTIONSTOGGLING MOL WHILE ON PRIMARY PORT CAUSED STATUS ERRORSHOULD HAVE MOL=1 PGM=0SWITCHING FROM PRIMARY PORT TO A/B CAUSED RAE~ lhSWITCHING FROM PRIMARY PORT TO A/B CAUSED STATUS ERRORTOGGLING MOL WHILE IN A/B CAUSED RAETOGGLING MOL WHILE IN A/B CAUSED STATUS ERROR|lwSHOULD HAVE MOL=1 PGM=1FAILED TO SET "ATTN" WHILE IN A/B TRIED TO SET "ATTN" BY WRITING 1'S TO C00-C15 REG-02CAN'T CLEAR "ATTN" USING RHCLR (FROM A/B)SWITCHING FROM A/B TO SECONDARY PORT CAUSED RAETOGGLING MOL WHILE SWITCHED TO SECONDARY PORT CAUSED RAETOGGLING MOL WHILE SWITCHED TO SECONDARY PORT}@mFAILED TO CAUSE RAE (CBTO)DUAL PORT LOGIC APPEARS HUNG UPSWITCHING BACK TO PRIMARY PORT AND TOGGLING MOL CAUSED RAESWITCHING BACK TO PRIMARY PORT AND TOGGLING MOLHAS CAUSED A STATUS ERRORt@m+
WITH THE START STOP SWITCH IN THE STOP POSITION, MOMENTARILY
REMOVE AND THEN RESTORE (AC) POWER FROM THE DEVICE
POWERING UP DRIVE DID NOT SET "ATTN" C15 REG-01INCORRECT STATUS FOLLOWING POWER UP OF DRIVESHOULD HAVE (DEV-CK=0 UNSAFE=1) WHICH IMPLIES AC-LOWC00-C05, C11-C15 REG-07 SHOULD ALWAYS BE 0LOOK AHEAD REGISTER NOT COUNTING


DIAGNOSTIC WAS LOOKING FOR SECTOR #CAN'T FIND SOME SECTOR AFTER READING LOOK AHEAD REG. 1000 TIMESLOOK AHEAD SECTOR IS ILLEGAL IN 18-BIT MODELAST LEGAL SECTOR IS 35 (OCTAL)INCORRECT STATUS AFTER ISSUING M-MODE OFFSET COMMANDPGM EXPECTS: ATTN=1, OFS-MD=1 (C00 REG-01), GO=0, ERROR=0INCORRECT STATUS AFTER ISSUING M-MODE "RTN-CL" COMMANDPGM EXPECTS: ATTN=1,OFS-MD=0,GO=0,ERROR=0 ISSUING ILLEGAL CMD IN M-MODE CAUSED INCORRECT STATUSPGM EXPECTS: ATTN=1 GO=0 ILF=1 (NO OTHER ERROR)ISSUING A FUNCTION (WITHOUT "GO") CAUSED A STATUS ERROR|xnPGM EXPECTS: ATTN=0 ERROR=0 GO=0ISSUING A COMMAND IN M-MODE CAUSED STATUS ERRORPGM EXPECTS: GO=0 ATTN=0 ERROR=0READING REG14 DID NOT RETURN ZEROS IN BITS 00-09CAN'T FLOAT PATTERNS DOWN C00-C15 OF RHWC REG.MODULE CALLOUT IMPOSSIBLE}8n!CAN'T FLOAT PATTERNS DOWN C00-C15 OF RHBACAN'T FLOAT PATTERNS DOWN C00-C15 OF RHDBERROR DETECTED - DLT BIT DID NOT SETERROR DETECTED - TRE BIT DID NOT SETERROR DETECTED - SC BIT DID NOT SET}n6ERROR DETECTED - DLT BIT DID NOT CLEARERROR DETECTED - TRE BIT DID NOT CLEARERROR DETECTED - SC BIT DID NOT CLEARIR BIT DID NOT SET AFTER INITIALIZATIONOR BIT SET AFTER INITIALIZATIONOUTPUT READY DID NOT SET AFTER LOADING A WORDz8nNFIRST WORD OUT OF THE SILO SHOULD HAVE BEEN ALL ZEROSSECOND WORD OUT OF THE SILO SHOULD HAVE BEEN ALL ONESIR BIT DID NOT CLEAR AFTER THE SILO WAS FILLEDOR BIT WAS NOT SET AFTER THE SILO WAS FILLEDDATA RETURNED FROM THE SILO WAS INCORRECT @'HSEEK TIMED OUT OR COMPOSITE ERROR SET ON SEEK TO CYL0DLT BIT DID NOT SET AFTER A SILO OVERFLOWTHE FIRST WORD IN THE SILO CHANGED WITH OVERFLOWCONDITION, SHOULD NOT HAVE BEEN AFFECTED0n{OUTPUT READY BIT DID NOT SET AFTER SILO WAS LOADED0oOUTPUT READY DID NOT SET AFTER THE SILO WAS LOADED@oDATA LATE DID NOT SET AFTER 2 SILO READS~o@@PIP, REG-01 (C13), DID NOT SET ON RECAL COMMANDCOMPOSITE ERROR DETECTED DURING A RECAL COMMAND@

ERROR DETECTED ON FULL SPEED SEARCHz`o 'PX@REG14 C00-C09 DID NOT SET AS EXPECTEDFUNCTIONAL FAILURE MODULE CALL OUT NOT POSSIBLEBITS 26 THRU 35(BB00-BB09) READ FROM REGISTER 14DID NOT COMPARE WITH CYLINDER ADDRESS SENT TO CYLADDR REGAN ILLEGAL CYL NUMBER WAS SENT TO THE DRIVEIAE DID NOT SET AS EXPECTEDFUNCTIONAL TEST FAILURE DURING A MAINTENANCE MODE SEEKMODULE CALL OUT NOT POSSIBLEA LEGAL CYLINDER NUMBER WAS SENT TO THE DRIVEhoEAND IAE WAS SET{(oG @'PXIAE DID NOT SET AS EXPECTED DURING A SEARCH TO AN ILLEGAL CYLLAST SECTOR SET WITH A SECTOR ADDRESS OF LESS THAN 35LAST SECTOR DID NOT SET WITH A SECTOR ADDRESS OF 35LAST SECTOR SET WITH A SECTOR ADDRESS GREATER THAN 35@LAST SECTOR TRK DID NOT SET AS EXPECTEDLAST SECTOR TRK SET ON A SECTOR TRK OTHER THAN TRK4 SECT35BB00-BB09 WERE NOT ZERO AS EXPECTED{(omHEAD ADDRESS MAY HAVE BEEN SENT TO DRIVE BUSIAE ERROR OCCURRED IN A MAINT MODE SEEK TO A LEGAL CYLINDERAN ERROR OTHER THAN IAE OCCURRED DURING A MAINT MODE SEEK TO A LEGAL CYLFUNCTIONAL FAILURE MODULE CALLOUT NOT POSSIBLEIAE DID NOT SET AS EXPECTED ON ILLEGAL DATA ADR.COMPOSITE ERROR SET DURING A FULL SPEED SEARCHTHE SECTOR NUMBER SPECIFIED BY THE LOOK AHEAD~ppREG DID NOT MATCH SECTOR NUMBER IN THE DATAADDRESS REGISTER FOLLOWING A SEARCH OPERATION(p @'HA COMPOSITE ERROR OR TIME OUT OCCURRED DURING~p"A DRIVE RECAL. FUNCTIONAL FAILURE MODULE CALLOUT IMPOSSIBLEDEVICE HUNG,"GO" DID NOT SET AFTER A SEEK COMMANDFUNCTIONAL FAILURE MODULE CALLOUT NOT POSIBLE} p2COMPOSITE ERROR DETECTED DURING A FULL SPEED SEEK @'@A COMPOSITE ERROR OR TIME OUT OCCURRED DURING A DRIVERECAL. FUNCTIONAL FAILURE MODULE CALLOUT IMPOSSIBLESEEK. FUNCTIONAL TEST FAILURE MODULE CALLOUT IMPOSSIBLE|@pI @'PH"OCC" BIT IS EQUAL TO A ONE. IT SHOULD BE A ZERO"OCC" BIT IS EQUAL TO A ZERO. IT SHOULD BE A ONEILF SET DURING A LEGAL FUNCTION COMMAND~RUN GO IN REG03 DID NOT SET ON A MAINT MODE READOPI DID NOT SET WHEN CONTROLLER DID NOT ASSERTTHE RUN LINE FOR A DATA RESET.uppe"OPI" TIMER DID NOT CLEAR WITH RESET OF GO@@@@A WRITE CMD WAS SENT TO THE DRIVE WITH WRT PROTON A ONE. THIS DID NOT PRODUCE WLE AS EXPECTEDWLE WAS SET WITH WRITE PROTECT AND AND A READ COMMANDWLE WAS SET WITHOUT WRITE PROTECT BEING SET@ THE EBL BIT(C13) IS A ONE, IT SHOULD BE A ZEROTHE EBL BIT(C13) IS AT ZERO, IT SHOULD BE AT ONE@xTHE DA OR DCY DID NOT INCREMENT CORRECTLY ON DIAG EBL"LBT" WAS NOT A ZERO, AS EXPECTED"LBT" DID NOT GO TO A ONE ON THE LAST BLOCK"LBT" BIT SET BEFORE LAST BLOCK30~"AOE" DID NOT SET AS EXPECTEDPH31AOE WAS NOT CLEAR AS EXPECTED @'@@@THE OFFSET MODE BIT DID NOT CLEAR ON A RECAL COMMANDTHE OFFSET DIRECTION BIT DID NOT CLEAR ON A RECAL COMMANDOFFSET WAS NOT CLEARED BY EITHER A WRT OR WRT HEADER COMMAND8q7OFFSET MODE WAS CLEARED BY EITHER A READ DATA~q<OR READ HEADER AND DATA @'QXDRIVE CYLINDER ADDRESS DID NOT INCREMENT AS EXPECTED
	IN MAINT MODE FUNCTIONAL TEST FAILURE.  MODULE CALL OUT NOT
	POSSIBLEx`qLOFFSET MODE DID NOT CLEAR ON A MAINT MODE IMPLIED SEEK~PROM STROBE DID NOT SET AFTER 27. BIT CLOCKSPROM STROBE SHOULD STILL BE SETPROM STROBE SHOULD BE CLEARPROM STROBE SHOULD REASSERT AFTER 12 CLOCKSREAD OR WRITE GATE SHOULD NOT BE SETWRITE GATE DID NOT SETHAVE DETECTED A ONE WHERE THERE SHOULDHAVE BEEN A ZERO.
THE ERROR OCCURED ON CLOCK # 
AFTER THE RISING EDGE OF PROM STROBEERROR DETECTED DURING M-MODE WRTHD + DATA PATH TESTINGERROR OCCURED IN THE PRE-HEADER AREAERROR OCCURED IN THE HEADER AREAERROR OCCURED IN THE DATA AREA|hrERROR OCCURED IN THE CRC AREAFAULT IN 1ST 29 BYTES OF SECTOR GAP. "BYTE SHOULD BE 0'S"PRE HEADER SYNC BYTE FAULT "SHOULD BE 031"ERRONEOUS DATA IN HEADER WORD AREA4 BYTES OF HEADER INFORMATION SHOULD BE 0HEADER CRC DATA ERROR. IT SHOULD BE ZERO@r!17 BYTES OF POST HEADER GAP NOT ALL ZERO~r%POST HEADER SYNC BYTE FAULT. "SHOULD BE 031"
BYTE # 	DATA = 
DATA WAS = 
HEADER CRC WORD WAS = FAULT IN 1ST 18 BITS WHICH CAME OVER DATA BUSr5DATA SHOULD BE = 000000FAULT IN 2ND 18 BITS WHICH CAME OVER DATA BUSzr<DATA SHOULD BE = 777777CAN'T FLOAT PATTERNS OVER WRITE DATA PATH CORRECTLY
ERROR ON AN 18. BIT XFER OVER DATA BUS. ERROR WAS ON TRANSFER # 
DATA ACROSS THE MASSBUS = 
DATA AT DRIVES MAINT REG = DBPE WHILE GOING FROM CONTROLLER TO DRIVE	FAULTY "DTE" DETECTION LOGICEXPECTED LF-SYNC = 1 EXPECTED LF-SYNC = 0 CAN'T SEND CONSTANT DATA THROUGH DATA PATHCAN'T XFER FLOATING PATTERNS OVER DATA PATHCAN'T XFER MISC. DATA PATTERNS OVER DATA PATH{ rlDIFFICULT FAULT. CONSTANT AND FLOATING PATTERNSHAVE ALREADY WORKEDMODULE CALLOUT WOULD BE IMPOSSIBLEDRIVE DATA BUS PARITY FAULTDRIVE DATA BUS PARITY GENERATOR FAULTERROR DETECTED DURING M-MODE WRITE DATA PATH TESTINGERROR DETECTED DURING M-MODE READ DATA PATH TESTING
ECC FIELD CORRECT= 
ECC FIELD ACTUAL = ECC GENERATOR HAS OUT-PUT INCORRECT DATA8sFAULTY STATUS DOING M-MODE READ HEADER + DATA~xsSHOULD HAVE: DATA AREA=1 HCRC=0 HCE=0 FER=0DRIVE FAILED TO DETECT "HCRC" ERROR WHEN~s!WRONG CRC WORD WAS SUPPLIED IN MAINT MODEDRIVE FAILED TO DETECT "HCE" WHEN WRONG CYLINDERDATA WAS SENT BY DIAGNOSTICDRIVE FAILED TO DETECT FORMAT ERROR}@s1DRIVE IN 18 BIT MODE. DIAGNOSTIC FURNISHEDHEADER DATA FOR 16 BIT MODE@"HCI" LOGIC NOT FUNCTIONING CORRECTLYWITH HCI=1, HCRC,HCE,FER SHOULD BE ZERODATA CHECK DID NOT SET WHEN AN INCORRECT}@sFECC CHARACTER WAS SENT.DBPE DETECTED DURING FULL SPEED DATA TESTCHECK MASSBUSS CABLES AND TERMINATORSDEV.CK DETECTED DURING FULL SPEED DATA TESTLOSS, BC DETECTED DURING FULL SPEED DATA TESTy0sZDTE-OPI DETECTED DURING FULL SPEED DATA TESTERROR DETECTED DURING FULL SPEED DATA TESTFUNCTIONAL TEST FAILURE-MODULE CALLOUT NOT POSSIBLEDEV.CHK DETECTED DURING FULL SPEED WRITE HEADER AND DATAERROR DETECTED DURING FULL SPEED WRITE HEADER AND DATADBPE DETECTED DURING FULL SPEED READ HEADER AND DATADEV CHK DETECTED DURING A FULL SPEED READ HEADER AND DATADTE DETECTED DURING A FULL SPEED READ HEADER AND DATALOSS BC DETECTED DURING A FULL SPEED READ HEADER AND DATADATA READ IS DIFFERENT FROM THAT WRITTEN~pt@		;SET UP MESSAGE
HEADER WORD EXPECTED WAS:		;SET UP MESSAGE
HEADER(WORDOREADPWAS:{tHEADERRREADNDIDGNOTWMATCHTHEADERAEXPECTEDHCE"ORMFERAOCCURREDEONIREADTHEADERAANDADATASOP.HCRCOCCURREDOONEREADTHEADERXANDADATAROP.HCRC,HCETORFERDETECTED ON READ HEADER AND DATAOPERATION DURING THE HEAD INTERFERENCE TESTHCRC,HCE OR FER DETECTED ON READ HEADER ANDDATA OPERATION DURING THE CYLINDER INTERFERENCE TESTCOMPOSITE ERROR DETECTED DURING A FULL SPEED WRITE DATA OPR.xxtACOMPOSITE ERROR DETECTED DURING A FULL SPEED READ DATA OPRLBT DID NOT SET ON A WRITE TO CYL1466,HD4,SECT35  ~AOE DID NOT SET AS EXPECTED ON A TRANSFER PAST THE LAST BLOCK@@ERROR OTHER THAN DCK OCCURRED DURING FULL SPEED READ WITH OFFSETCOMPOSITE ERROR DETECTED DURING FULL SPEED TRANSFERFUNCTIONAL FAILURE-MODULE CALL OUT NOT POSSIBLEERROR DETECTED IN RH11 KSRHST WORD DURING FULL SPEED TRANSFERERROR DETECTED DURING FULL SPEED READ HEADER AND DATAFUNCTIONAL FAILURE-MODULE CALLOUT NOT POSSIBLEEXPECTED GO-BIT = 0, THE TRANSFER SHOULD|tzHAVE FINISHED.EXPECTED DCK=1,ECH=0,ECC POS=4607,ECC PATT=3777EXPECTED DCK=1,ECH=1,ECC POS=4640.,ECC PATT=3477EXPECTED GO-BIT=0, THE TRANSFER SHOULDIV
THEEREGISTERMNUMBERSCAUSINGPTHE-CAPTURERISH=NREADINGPSOMEDREGISTERONIPORT-AH(OTHERVTHENS0)AHASRCAPTUREDEPORT-AIVDIDBNOTDRECEIVECANVATA8v,WHEN@PORT-BORELEASED.AS(PORT-AOHADBREQUESTED)(v1IVvEIV

,48<@$<~}:,@eJ~ KR,=HX2S:8`}6	 KK|@I$XzK)0I&tp}J,I$|(UBAS:    HI PIA= LO PIA=

UBARAM PAGE ADDR=$$

: ,~DRMR2  REG-14  TSTBIT (C12)DRMR2  REG-14  CNT CYL (C11)DRMR2  REG-14  CNT HD  (C10)DRMR2  REG-14  TAG  (C13)XwDRSR   REG-01  ATA  (C15)(wRHCS1  REG-00  GO BIT (C00)DRER1  REG-02  OPI  (C13)~xwDRSR   REG-01  ERROR (C14)DRMR2  REG-14  RECAL (C06)DRMR1  REG-03  OCC  (C15){pwDRMR1  REG-03  RUN+GO (C14)DRMR1  REG-03  MBA EBL (C13)DRMR1  REG-03  EN SRCH (C11)DRMR1  REG-03  CONT  (C06)DRMR1  REG-03  L SECT (C02)DRMR1  REG-03  L SECTK (C01)DRSR   REG-01  OFS MODE (C00)DRMR1  REG-03  ROM STB (C05)DRMR1  REG-03  LF SYNC (C10)DRMR1  REG-03  EN CRC  (C09)DRMR1  REG-03  DATA AREA (C08)}w8DRMR1  REG-03  HD AREA (C07)DRMR1  REG-03  EN ECC  (C04)DRMR1  REG-03  WR DATA (C03)DRMR2  REG-14  RD GATE (C01)DRMR2  REG-14  WR GATE (C00) FNCTN(30-34)= GO-BIT= DRIVE=

 WORD CNT =  BLK ADDR=|@wO SURFACE= SECTOR= DRIVE TYPE=<SINGLE PORTED RM03DUAL PORTED RM03NOT AN RM03

( EXTENTION= DRIVE SER. NO.= DATA BUFFER=H OFFSET DIRECTION IS (-)(+) DESIRED CYLINDER= CURRENT CYLINDER= HOLD REG DATA=(wl ECC POSITION=4 ECC PATTERN=,
SET CYLINDER=z0wr
SET HEAD=
(SET CONTROL)   ?BIT-H

~@
USING START-STOP SWITCH CYCLE THE DRIVE ON-LINE
WAIT FOR READY LAMP TO STAY LIT, THEN

FAILURE TO SET MOL=1 USING MAINT REGISTER C09



MOL FAILED TO SET OR <CR> WAS HIT
BEFORE DRIVE WAS READY.



FAILURE TO SET VV=1 WITH A READIN PRESET COMMAND



WITH M-MODE=1 AND COMP ERR=1, CAN'T CLEAR ERRORS BEFORE ISSUING
A READIN PRESET WITHOUT COMING OUT OF M-MODE

(x
USING THE START-STOP SWITCH, CYCLE THE DRIVE OFF-LINE|Hx%

FAILURE TO CLEAR MOL VIA C09 OF MAINT REG


WRITE ENABLE THE DRIVE

FAILURE TO WRITE ENABLE THE DRIVE USING MAINT REG C03

@@@ @@x
DEVICERTIMEOUTB(HUNG)SPGMFWAS WAITING ATOPCS-}W~aH~

0

(

B

-- THE FOLLOWING BITS ARE IN THE WRONG STATE --

EXPECTED ROM PC IN OCTAL IS `~@w@@EPORT-A	PORT-B	8
DURING TEST "pxT" AT PC = s0xVIS HUNG ON PORT-AIS HUNG ON PORT-B~p,`6$}

@K6~. I$eJ~ KR,=HM`e>>(6X?~[m|\+y$LRgL)3SO$\@:x$e0|}

@K6~. I$eJ~ KR,=HM`CRZM. eo`CS$[8i&tp^{ZS;,S_~<}xQRF4wB

y MMM9J/	1kRMi`R>p}`x{$}pI ~a$=iW ~{ i&\`:xCS$[8i&tp^S2q]$}p]O&-1i&}o_KbY2Kh:C0\Y_HJ6SP?~}xQ"E(Q C&dYi<9:N>d$`@k


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THE FOLLOWING RM03'S ARE DETECTED 
DRIVES
Xy;    SELECT DRIVES (0-7) ~`y>OR "A" - &a; NO DRIVES SELECTED ? 

|I*PGM TRACE* TEST- PC- *TEST OMITTED. "USER MODE"*
PyI *TEST OMITTED. NO "OPRSEL"*
{yL
UNEXPECTED CBTO AT PC-   THE TEST WILL LOOP BUT !!!
THE DIAGNOSIS IS PROBABLY INVALID DUE TO THE CBTO
MAKE SURE LOGICAL ADDR PLUG IS NOT LOOSE

UNEXPECTED CONTROL BUS PARITY ERROR AT PC-   THE TEST WILL 
LOOP BUT THE DIAGNOSIS IS PROBABLY INVALID DUE TO THE P.E.
$
?? INVALID TEST SELECTED IN SW27-35. TEST-
PGM PAUSE: SW-25 IS SET.  LAST TEST COMPLETED TEST - hytPGM CONTINUED
0yv
DUAL PORT TESTING CAN NOT BE DONE IN USER MODE
}hy{
DUAL PORT TESTS HAVE BEEN SELECTED FROM THE SWITCHES
IVPASS DUAL PORT TESTS
RESTORE SYSTEM CONFIGURATION. HIT <CR> WHEN READY  
RESET SWITCH-3 TO CONTINUE
q8z
CAN'T READ THE DRIVE TYPE REG FROM EITHER PORT. HERE IS WHAT I GOT.
 "LOCK"  ON ONE OF THE PORTS, PERFORM
ANOTHER HEAD LOAD AND HIT <CR> WHEN READY  WILL NOT BE TESTED. IT IS NOT DUAL PORTED
$

|IDO YOU WANT SETUP INSTRUCTIONS SET UP HIT <CR> WHEN READY  
PASS COMPLETE SET UPAS FOLLOWS:
1. CABLE THE MASSBUS INTO PORT-A "IN"
2. CABLE (SPECIAL DUAL PORT TEST CABLE) PORT-A "OUT" TO PORT-B "IN"
THE TEST CABLE IS PART # 7010507-02
3. PORT-B "OUT" IS EITHER TERMINATED OR CABLED TO REST OF THE BUS
4. DRIVE SHOULD BE CYCLED DOWN AND UP WITH PORT SWITCH IN A/B MODE

LEAVING THE DUAL PORT OPTION SWITCH SET WILL CAUSE THE TESTS TO 
CONTINUOUSLY LOOP ON A SINGLE DRIVE.

 ** CAUTION ** IF THERE EXISTS A ON THE BUS,
IT MUST BE POWERED DOWN BEFORE THE TEST IS STARTED

*PGM TRACE*  TEST-}fK7IlI#]C)@;G-!m	6a{wp}CyyC4)9iO_
HIT <CR> WHEN READY    DRIVE-OPR INTERVENTION REQ'D IN TEST-FAILURE OCCURED DURING TEST-
THE FOLLOWING DEVICES HAVE BEEN TESTED

LIST PGM SWITCH OPTIONS ? 	LEFT SIDE SWITCHES:
400000	ABORT PGM AFTER 1ST PASS
040000	INHIBIT PRINTOUT
~({020000	OUTPUT TO LPT
010000	BELL ON ERROR
004000	LOOP ON ERROR
002000	HALT ON ERROR (EXEC MODE)
001000	PRINT ALL ERRORS
}({000200	USE ABBREVIATED PRINTOUTS
000004	INHIBIT CACHE
000040	MODIFY UBA/RH11 DEVICE ADDRESSES
000010	RUN OPER INTERVENTION TESTS ALSO

 RIGHT SIDE SWITCHES:
400000	PGM TRACE IN EFFECT (ALL TESTS)
}p{&200000	EXPANDED MODULE CALLOUTS
040000	RUN DUAL PORT TEST
004000	TRACE TESTS THAT ARE OMITTED (SKIPPED)
002000	PAUSE BETWEEN TESTS UNTIL THIS SWITCH IS RESET
~X{8001000	RUN TEST SELECTED IN SWITCHES 27-35

WORD	EXPECTED	BAD WORD	CORE ADDRESS
`
ERROR: TEST-~p{C RH-4
SCOPE PC =   START ADR OF TEST = 
DATA SWITCHES = SCOPE PC-TST- DEV-x{LSW-xX|J01z 82#02'&02B)`2e.h31H3!5`389p3c=p4
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@R

8@v`APA>pA_Au 8B'B\ Bt/PC!!6!!!!8!!! CQ?pDFDYOXEWXEqaHF-gikXFlr@G%y GhpH	 H<		XH`	)!!!!!!!!! I	XI_	%Jx	3K;	;Kl	CHL^	R0Ms	jPNp	qO 	w(OS	}8P
(PP
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