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klad.sources/mscsld.xrf
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1 %TITLE 'STIRS FAULT ISOLATION DATA FOR M8616 (CSL) BOARD'
2
3 MODULE MSCSLD (
4 LANGUAGE(BLISS36)
5 ) =
6
7 BEGIN
8
9 !
10 ! COPYRIGHT (C) 1979 BY
11 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
12 !
13 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
14 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
15 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
16 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
17 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
18 ! TRANSFERRED.
19 !
20 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
21 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
22 ! CORPORATION.
23 !
24 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
25 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
26 !
27
28 !++
29 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
30 !
31 ! ABSTRACT:
32 !
33 ! THIS MODULE CONTAINS THE FAULT ISOLATION DATA FOR THE KS10
34 ! STIMULUS/RESPONSE (STIRS) DIAGNOSTIC FOR THE M8616 (CSL) BOARD.
35 ! IT IS LINKED TO THE 'MSSTRC' AND 'MSCSLT' MODULES TO PRODUCE
36 ! THE 'MSCSL.EXE' FILE.
37 !
38 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
39 !
40 ! AUTHOR: RICH MURATORI , CREATION DATE: 23-MAY-79
41 !
42 ! MODIFIED BY:
43 !
44 ! RICH MURATORI, 23-MAY-79; VERSION 0.1
45 !--
46 !
47 ! EQUATED SYMBOLS:
48 !
49
50 GLOBAL LITERAL
51 DATA_VERSION = 1, !VERSION NUMBER FOR THIS MODULE
52 DATA_EDIT = 0; !EDIT NUMBER FOR THIS MODULE
53 !
54 ! MACROS:
55 !
56
57 COMPILETIME
58 ALLOC_B = 35, ! PDP-11 STYLE BIT # IN WORD, READY TO OVERFLOW
59 ALLOC_W = -1, ! WORD #, SO WE WILL START WITH 0 AFTER OVERFLOW
60 ALLOC_N = 0, ! NUMBER OF THINGS ALLOCATED
61 ALLOC_N_1 = 0, ! (ALLOC_N - 1) TEMPORARY
62 ALLOC_W_1 = 0; ! (ALLOC_W + 1) TEMPORARY
63
64 MACRO
65 ALLOC(ALLOC_NAME,ALLOC_SLIT) = ! ALLOCATE FAULT ANALYSIS BITS
66 %ASSIGN(ALLOC_B,ALLOC_B + 1)
67 %IF ALLOC_B EQL 36
68 %THEN
69 %ASSIGN(ALLOC_B,0)
70 %ASSIGN(ALLOC_W,ALLOC_W + 1)
71 COMPILETIME
72 %NAME(W_,%NUMBER(ALLOC_W)) = 0;
73 %FI
74 MACRO
75 ALLOC_NAME = %QUOTE %ASSIGN (
76 %QUOTE %EXPAND %NAME(W_,%NUMBER(ALLOC_W)),
77 %QUOTE %EXPAND %NAME(W_,%NUMBER(ALLOC_W)) OR
78 (1 ^ %QUOTE %EXPAND %NUMBER(ALLOC_B)))
79 %QUOTE % ;
80 BIND
81 %NAME(N_,%NUMBER(ALLOC_N)) =
82 %IF %NULL(ALLOC_SLIT)
83 %THEN
84 %ASSIGN(ALLOC_N_1,ALLOC_N - 1)
85 %NAME(N_,%NUMBER(ALLOC_N_1))
86 %ELSE
87 UPLIT(%ASCIZ ALLOC_SLIT)
88 %FI ;
89 %ASSIGN(ALLOC_N,ALLOC_N + 1)
90 %,
91 DUMP(X,N)[] = ! X0, ... XN
92 %IF %COUNT GEQ N %THEN %EXITMACRO %FI
93 %IF %COUNT NEQ 0 %THEN , %FI
94 %NAME(X,%NUMBER(%COUNT))
95 DUMP(X,N)
96 %,
97 DUMP_ASSIGN(N)[] = ! %ASSIGN(X0,0) ... %ASSIGN(XN,0)
98 %IF %COUNT GEQ N %THEN %EXITMACRO %FI
99 %QUOTE %ASSIGN (%NAME(W_,%NUMBER(%COUNT)),0)
100 DUMP_ASSIGN(N)
101 %;
102
103 !SOME SPECIAL MACROS WHICH COMBINE SEVERAL NETWORK MACROS
104
105 MACRO
106 PI_REQ1 = PIREQ1 PIREQ%,
107 PI_REQ2 = PIREQ2 PIREQ%,
108 PI_REQ3 = PIREQ3 PIREQ%,
109 PI_REQ4 = PIREQ4 PIREQ%,
110 PI_REQ5 = PIREQ5 PIREQ%,
111 PI_REQ6 = PIREQ6 PIREQ%,
112 PI_REQ7 = PIREQ7 PIREQ%,
113 TCLKA = T_CLK_A TCLK_CSL R_CLK_E RCLK_CSL%,
114 TCLKB = T_CLK_B TCLK_CSL R_CLK_E RCLK_CSL%,
115 TCLKC = T_CLK_C TCLK_CSL%,
116 TCLKD = T_CLK_D TCLK_CSL%,
117 RCLKD = R_CLK_D R_CLK_E RCLK_CSL%,
118 RCLKH = R_CLK_H RCLK_CSL%,
119 TCLK_CSL = T_CLK_CSL PDLY3 MSTRCLK%,
120 RCLK_CSL = R_CLK_CSL PDLY5 MSTRCLK%,
121 MSTRCLK = MSTR_CLK MNT_ENBH%;
122
123 !NETWORKS ON CSL1
124
125 ALLOC( MSTR_CLK , 'CSL1: MASTER CLOCK FLOPS')
126 ALLOC( T_CLK , 'CSL1: "T CLK H"')
127 ALLOC( PDLY1 , 'CSL1: PROGRAMMED DELAY NETWORK #1')
128 ALLOC( PDLY2 , 'CSL1: PROGRAMMED DELAY NETWORK #2')
129 ALLOC( PDLY3 , 'CSL1: PROGRAMMED DELAY NETWORK #3')
130 ALLOC( PDLY4 , 'CSL1: PROGRAMMED DELAY NETWORK #4')
131 ALLOC( PDLY5 , 'CSL1: PROGRAMMED DELAY NETWORK #5')
132 ALLOC( T_CLK_CSL , 'CSL1: "T CLK CSL\#20\"')
133 ALLOC( R_CLK , 'CSL1: "R CLK H"')
134 ALLOC( R_CLK_CSL , 'CSL1: "R CLK CSL\#20\"')
135 ALLOC( BUS_ARB, 'CSL1: BUS ARBITRATOR')
136
137 !NETWORKS ON CSL2
138
139 ALLOC( ADR0L2_L, 'CSL2: ADR 0')
140 ALLOC( ADR0L2_H )
141 ALLOC( ADR1L_L, 'CSL2: ADR 1')
142 ALLOC(ADR1L_H )
143
144 !NETWORKS ON CSL3
145
146 ALLOC( REC_PE, 'CSL3: "REC PE" DETECTOR')
147 ALLOC( CACHE_EN, 'CSL3: CACHE ENABLE')
148 ALLOC( CRA_PE_LTCH , 'CSL3: PARITY ERROR LATCH')
149 ALLOC( CRM_PE_LTCH )
150 ALLOC( DP_PE_LTCH )
151 ALLOC( REC_PE_LTCH )
152 ALLOC( CPU_PE, 'CSL3: "CPU PE" NETWORK')
153 ALLOC( REC_BUS_PE , 'CSL3: "REC BUS PE" NETWORK')
154 ALLOC( DP_PAR_ERR , 'CSL3: "DP PAR ERR" NETWORK')
155 ALLOC( PE_LTCH , 'CSL3: "PE (1)" LATCH')
156 ALLOC( PE_DET , 'CSL3: PARITY DETECT CONTROL FLOPS')
157 ALLOC( RST_LTCH )
158 ALLOC( CRM_DET )
159 ALLOC( DP_PE_DET )
160 ALLOC( RAM_ER_DLY , 'CSL3: RAM ERROR LATCHS')
161 ALLOC( RAM_ER_LTCH )
162 ALLOC( NEXM_LTCH , 'CSL3: "NEXM" DETECT NETWORK')
163 ALLOC( MEM , 'CSL3: "MEM" LATCH')
164 ALLOC( MEMH )
165 ALLOC( RD_0 , 'CSL3: REG READ SIGNALS')
166 ALLOC( RD_100 )
167 ALLOC( RD_300 )
168 ALLOC( RD_302 )
169 ALLOC( WRT100 , 'CSL3: REG WRITE SIGNALS')
170 ALLOC( WRT102 )
171 ALLOC( WRT104 )
172 ALLOC( WRT106 )
173 ALLOC( WRT110 )
174 ALLOC( WRT112 )
175 ALLOC( WRT114 )
176 ALLOC( WRT116 )
177 ALLOC( WRT204 )
178 ALLOC( WRT205 )
179 ALLOC( WRT206 )
180 ALLOC( WRT210 )
181 ALLOC( WRT212 )
182
183 !NETWORKS ON CSL4
184
185 ALLOC( DFN_0, 'CSL4: REGISTER 205')
186 ALLOC( DFN_1 )
187 ALLOC( DFN_2 )
188 ALLOC( DFN_3 )
189 ALLOC( DFN_4 )
190 ALLOC( DFN_5 )
191 ALLOC( DFN_6 )
192 ALLOC( DFN_7 )
193 ALLOC( DFN_11 )
194 ALLOC( TRAP_EN )
195 ALLOC( CRM_RESET , 'CSL4: REGISTER 204' )
196 ALLOC( DP_RESET )
197 ALLOC( STK_RESET )
198 ALLOC( CRM_WRT )
199 ALLOC( CRM_ADR_LD )
200 ALLOC( SS_MODE )
201 ALLOC( REG204 )
202 ALLOC( XMIT_DATA , 'CSL4: REGISTER 210')
203 ALLOC( XMIT_ADR )
204 ALLOC( C_R_C_E ) !'CRA R CLK ENB (1)'
205 ALLOC( C_T_C_E ) !'CRA T CLK ENB (1)'
206 ALLOC( LTCH_DATA )
207 ALLOC( C_LTCHS )
208 ALLOC( REG210 )
209 ALLOC( BUS_REQ , 'CSL4: "BUS REQ" LATCH')
210 ALLOC( CONS_REQ )
211 ALLOC( REQ_CTL )
212 ALLOC( MSEC_EN , 'CSL4: "1 MSEC EN" LATCH')
213 ALLOC( TEN_INT_LTCH , 'CSL4: "10 INT" LATCH')
214 ALLOC( GRANT , 'CSL4: "GRANT" DRIVER')
215 ALLOC( HLT_LP , 'CSL4: "HALT LOOP (1)" LATCH')
216 ALLOC( EXEC_B , 'CSL4: "EXECUTE" LATCH')
217 ALLOC( EXEC_DRVR , 'CSL4: "EXECUTE" DRIVER')
218 ALLOC( RUN_1 , 'CSL4: "RUN" LATCH')
219 ALLOC( RUN_DRVR , 'CSL4: "RUN" DRIVER')
220 ALLOC( CONT_H , 'CSL4: "CONTINUE" LATCH')
221 ALLOC( CONT_DRVR , 'CSL4: "CONTINUE" DRIVER')
222 ALLOC( INT_10 , 'CSL4: "INT 10" CONTROL NETWORK')
223 ALLOC( CMD_LD , 'CSL4: "CPM CMD LD" SIGNAL')
224 ALLOC( DATA_ENB , 'CSL4: "DATA ENB" LATCH')
225 ALLOC( RTN_DATA, 'CSL4: "RETURN DATA" SIGNAL')
226 ALLOC( LTCH_DATA_ENB , 'CSL4: "LATCH DATA ENB (1)" SIGNAL')
227 ALLOC( DATA_ACK , 'CSL4: "DATA ACK" LATCH')
228 ALLOC( CRA_R_CLK , 'CSL4: "CRA R CLK\#20\" SIGNAL')
229 ALLOC( R_CLK_ENB , 'CSL4: "R CLK ENB" SIGNAL')
230 ALLOC( T_CLK_EN , 'CSL4: "CRA T CLK ENABLE" SIGNAL')
231 ALLOC( STAT_RD , 'CSL4: "STATUS RD (1)" SIGNAL')
232 ALLOC( GRANT_1 , 'CSL4: CONTROL LATCHES')
233 ALLOC( X_D1 )
234 ALLOC( C_LTCH1 )
235 ALLOC( T_ENB , 'CSL4: TRANSCEIVER TRANSMIT CONTROL SIGNALS')
236 ALLOC( T_ENB_A )
237 ALLOC( DATA_CYC )
238 ALLOC( XMIT_ENBS , 'CSL4: REGISTER 210 AND TRANSCEIVER TRANSMIT CONTROL SIGNALS')
239
240 !NETWORKS ON CSL5
241
242 ALLOC( RST1 , 'CSL5: "RESET (1)" SIGNAL')
243 ALLOC( PNL_RST , 'CSL5: "PANEL RESET" SIGNAL')
244 ALLOC( RESETL_L , 'CSL5: "RESET" SIGNAL DRIVERS')
245 ALLOC( RESETL_H )
246 ALLOC( RESETB_L )
247 ALLOC( RESETB_H)
248 ALLOC( RESETH )
249 ALLOC( CRAM_CLK , 'CSL5: "CRAM CLK" SIGNAL')
250 ALLOC( SING_CLK , 'CSL5: "SINGLE CLK" SIGNAL')
251 ALLOC( CLK_RUN , 'CSL5: "CLK RUN" SIGNAL')
252 ALLOC( PF_ST_1 , 'CSL5: "PAGE FAIL START (1)" SIGNAL')
253 ALLOC( PF_1 , 'CSL5: "PAGE FAIL (1)" SIGNAL')
254 ALLOC( CLK_ENBS , 'CSL5: CPU CLOCK ENABLES')
255 ALLOC( SHFT_LOGIC )
256 ALLOC( ENB , 'CSL5: "ENABLE (1)" SIGNAL')
257 ALLOC( ENABLE_PE )
258 ALLOC( PF , 'CSL5: "PAGE FAIL" SIGNAL')
259 ALLOC( WRT_DLY , 'CSL5: "WRT DLY" SIGNAL')
260 ALLOC( RD_DATA , 'CSL5: "RD DATA (1)" SIGNAL')
261 ALLOC( RD_DLY , 'CSL5: "RD DLY" SIGNAL')
262 ALLOC( READ_DLY , 'CSL5: "READ DLY" SIGNAL')
263 ALLOC( T_CNT_DN , 'CSL5: "T COUNT DONE (1)" SIGNAL')
264 ALLOC( T_COUNT_DONE )
265 ALLOC( ENB_RES , 'CSL5: "ENABLE + RESET" SIGNAL')
266
267 !NETWORKS ON CSL6
268
269 ALLOC( BUS20_23 , 'CSL6: BUS DATA 20-23 TRANSCEIVER')
270 ALLOC( BUS24_27 , 'CSL6: BUS DATA 24-27 TRANSCEIVER')
271 ALLOC( BUS28_31 , 'CSL6: BUS DATA 28-31 TRANSCEIVER')
272 ALLOC( BUS32_35 , 'CSL6: BUS DATA 32-35 TRANSCEIVER')
273 ALLOC( ADR0L6_L , 'CSL6: ADR 0' )
274 ALLOC( ADR0L6_H )
275 ALLOC( CSLBUF0 , 'CSL6: CSL BUS BUFFER')
276 ALLOC( CSLBUF1 )
277 ALLOC( CSLBUF2 )
278 ALLOC( CSLBUF3 )
279 ALLOC( CSLBUF4 )
280 ALLOC( CSLBUF5 )
281 ALLOC( MNT_ENBL, 'CSL6: "MAINT ENB" SIGNAL')
282 ALLOC( MNT_ENBH )
283 ALLOC( MNT_CLK , 'CSL6: "CLK 0" SIGNAL')
284 ALLOC( XMIT_PAR_RT , 'CSL6,7: TRANSCEIVER PARITY SIGNALS FOR BUS DATA 18-35')
285 ALLOC( RCV_PAR_RT )
286
287 !NETWORKS ON CSL7
288
289 ALLOC( BUS4_7 , 'CSL7: BUS DATA 4-7 TRANSCEIVER')
290 ALLOC( BUS8_11 , 'CSL7: BUS DATA 8-11 TRANSCEIVER')
291 ALLOC( BUS12_15 , 'CSL7: BUS DATA 12-15 TRANSCEIVER')
292 ALLOC( BUS16_19 , 'CSL7: BUS DATA 16-19 TRANSCEIVER')
293
294 !NETWORKS ON CSL8
295
296 ALLOC( BUS0_3 , 'CSL8: BUS DATA 0-3 TRANSCEIVER')
297 ALLOC( CMD_XCVR , 'CSL8: BUS CONTROL SIGNALS TRANSCEIVER')
298 ALLOC( RST_XCVR , 'CSL8: "R RESET" TRANSCEIVER')
299 ALLOC( R_PAR_RT , 'CSL8: "R PAR RIGHT" TRANSCEIVER')
300 ALLOC( R_PAR_LFT , 'CSL8: "R PAR LEFT" TRANSCEIVER')
301 ALLOC( XMIT_PAR_LFT , 'CSL7,8: TRANSCEIVER PARITY SIGNALS FOR BUS DATA 00-17')
302 ALLOC( RCV_PAR_LFT )
303 ALLOC( MEM_BUSY , 'CSL8: "MEM BUSY" SIGNAL')
304
305 !NETWORKS ON CSL9
306
307 ALLOC( R_CLK_A , 'CSL9: "R CLK A" SIGNAL')
308 ALLOC( R_CLK_B , 'CSL9: "R CLK B" SIGNAL')
309 ALLOC( R_CLK_H , 'CSL9: "R CLK H" SIGNAL')
310 ALLOC( R_CLK_L , 'CSL9: "R CLK L" SIGNAL')
311 ALLOC( R_CLK_D , 'CSL9: "R CLK D" SIGNAL')
312 ALLOC( R_CLK_E , 'CSL9: "R CLK E" SIGNAL')
313
314 !NETWORKS ON CSLA
315
316 ALLOC( T_CLK_A , 'CSLA: "T CLK A" SIGNAL')
317 ALLOC( T_CLK_B , 'CSLA: "T CLK B" SIGNAL')
318 ALLOC( T_CLK_C , 'CSLA: "T CLK C" SIGNAL')
319 ALLOC( T_CLK_D , 'CSLA: "T CLK D" SIGNAL')
320 ALLOC( NEXM , 'CSLA: READ MUX 1')
321 ALLOC( TEN_INT )
322 ALLOC( BUSREQ )
323 ALLOC( RAM_ERROR , 'CSLA: READ MUX 2')
324 ALLOC( RCLK_ENB0 )
325 ALLOC( CR_CLK_ENB )
326 ALLOC( DP_CLK_ENB )
327 ALLOC( EXEC , 'CSLA: READ MUX 3')
328 ALLOC( RUN )
329 ALLOC( CONT )
330 ALLOC( PE )
331 ALLOC( HALT_LOOP )
332 ALLOC( DATAACK )
333 ALLOC( R_RESET , 'CSLA: READ MUX 4')
334 ALLOC( PIREQ2 )
335 ALLOC( PIREQ1 )
336 ALLOC( RECEIVE_PE )
337 ALLOC( RPAR_LEFT , 'CSLA: READ MUX 5')
338 ALLOC( PIREQ4 )
339 ALLOC( CRM_PE )
340 ALLOC( RDATA_05 )
341 ALLOC( RDATA_13 )
342 ALLOC( RDATA_21 )
343 ALLOC( RDATA_29 )
344 ALLOC( RDATA_07 , 'CSLA: READ MUX 6')
345 ALLOC( RDATA_15 )
346 ALLOC( RDATA_23 )
347 ALLOC( RDATA_31 )
348 ALLOC( RDATA_04 )
349 ALLOC( RDATA_12 )
350 ALLOC( RDATA_20 )
351 ALLOC( RDATA_28 )
352 ALLOC( RDATA_00 , 'CSLA: READ MUX 7')
353 ALLOC( R_BADATA )
354 ALLOC( PIREQ5 )
355 ALLOC( MEM_PAR_ERR )
356 ALLOC( RDATA_08 )
357 ALLOC( RDATA_16 )
358 ALLOC( RDATA_24 )
359 ALLOC( RDATA_32 )
360 ALLOC( RDATA_01 , 'CSLA: READ MUX 8')
361 ALLOC( R_COMADR )
362 ALLOC( PIREQ6 )
363 ALLOC( DP_PE )
364 ALLOC( RDATA_11 )
365 ALLOC( RDATA_19 )
366 ALLOC( RDATA_27 )
367 ALLOC( RDATA_35 )
368 ALLOC( RPAR_RIGHT , 'CSLA: READ MUX 9')
369 ALLOC( MEMBUSY )
370 ALLOC( PIREQ3 )
371 ALLOC( RDATA_06 )
372 ALLOC( RDATA_14 )
373 ALLOC( RDATA_22 )
374 ALLOC( RDATA_30 )
375 ALLOC( RDATA_02 , 'CSLA: READ MUX 10')
376 ALLOC( R_IODATA )
377 ALLOC( PIREQ7 )
378 ALLOC( CRA_PE )
379 ALLOC( RDATA_10 )
380 ALLOC( RDATA_18 )
381 ALLOC( RDATA_26 )
382 ALLOC( RDATA_34 )
383 ALLOC( RDATA_09 , 'CSLA: READ MUX 11')
384 ALLOC( RDATA_17 )
385 ALLOC( RDATA_25 )
386 ALLOC( RDATA_33 )
387 ALLOC( RDATA_03 )
388 ALLOC( R_DATA )
389 ALLOC( MEM_REF_ERR )
390 ALLOC( PIREQ , 'CSLA: PI REQ DRIVERS')
391
392
393 MACRO
394 NTWK =
395 %ASSIGN(ALLOC_W_1,ALLOC_W + 1)
396 DUMP(W_,%NUMBER(ALLOC_W_1))
397 DUMP_ASSIGN(%NUMBER(ALLOC_W_1))
398 %;
399
400 ! THIS PLIT MAKES A V E R Y LONG LISTING WITH EXPANSIONS
401 SWITCHES LIST(NOEXPAND);
402
403 GLOBAL BIND
404 NET_NAMES = PLIT
405 (
406 DUMP(N_,%NUMBER(ALLOC_N))
407 );
408
409 ! DOCUMENT WHAT JUST HAPPENED
410 %PRINT(%NUMBER(ALLOC_N))
411 %PRINT(%NUMBER(ALLOC_W))
412 %PRINT(%NUMBER(ALLOC_B))
413
414 GLOBAL LITERAL
415 MAXNETS = ALLOC_N; !NUMBER OF NETWORKS
416 BIND T1_E1 = UPLIT(WRT100 RST_LTCH RESETH RST_XCVR RCLKD TCLKA R_RESET RD_100 ADR1L_H ADR0L2_L NTWK);
417 BIND T1_E2 = UPLIT(RST1 PNL_RST RST_LTCH RESETH RST_XCVR RCLKD TCLKA R_RESET RD_100 ADR1L_H ADR0L2_L NTWK);
418 BIND T1_NE1 = UPLIT(RESETH RST_XCVR TCLKA RCLKD R_RESET RD_100 ADR1L_H ADR0L2_L PNL_RST RST1 RST_LTCH WRT100 NTWK);
419 BIND T1_E3 = UPLIT(PE_LTCH PE NTWK);
420
421 BIND T1_ES = PLIT( T1_E1,
422 T1_E2,
423 T1_E3);
424 BIND T1_NES = PLIT( T1_NE1);
425
426
427 BIND T2_E1 = UPLIT(WRT210 RESETB_L BUSREQ GRANT GRANT_1 BUS_ARB BUS_REQ RD_300 ADR0L2_H NTWK);
428 BIND T2_E2 = UPLIT(BUSREQ WRT210 BUS_REQ RD_300 ADR0L2_H NTWK);
429 BIND T2_NE1 = UPLIT(RESETB_L BUSREQ BUS_REQ RD_300 ADR0L2_H WRT210 NTWK);
430
431 BIND T2_ES = PLIT( T2_E1,
432 T2_E2);
433 BIND T2_NES = PLIT( T2_NE1);
434
435
436 BIND T3_E1 = UPLIT(BUSREQ BUS_REQ REQ_CTL GRANT GRANT_1 BUS_ARB TCLKD TCLKC RCLKH RD_300 ADR0L2_H NTWK);
437 BIND T3_NE1 = UPLIT(TCLKD TCLKC RCLKH NTWK);
438
439 BIND T3_ES = PLIT( T3_E1);
440 BIND T3_NES = PLIT( T3_NE1);
441
442
443 BIND T4_E1 = UPLIT(NEXM NEXM_LTCH RCLKD GRANT_1 MEM RESETL_L WRT210 WRT114 MEM_BUSY RD_300 ADR0L2_H NTWK);
444 BIND T4_NE1 = UPLIT(RESETL_L NTWK);
445 BIND T4_E2 = UPLIT(WRT114 NEXM_LTCH NEXM RD_300 ADR0L2_H NTWK);
446 BIND T4_NE2 = UPLIT(NEXM RD_300 ADR0L2_H NTWK);
447
448 BIND T4_ES = PLIT( T4_E1,
449 T4_E2);
450 BIND T4_NES = PLIT( T4_NE1,
451 T4_NE2);
452
453
454 BIND T5_E1 = UPLIT(CONS_REQ NTWK);
455
456 BIND T5_ES = PLIT( T5_E1);
457
458
459 BIND T6_E1 = UPLIT(MEMH NTWK);
460
461 BIND T6_ES = PLIT( T6_E1);
462
463
464 BIND T7_E1 = UPLIT(TCLKD TCLKB C_LTCH1 RCLK_ENB0 C_LTCHS R_CLK_ENB RD_302 ADR0L6_H NTWK);
465 BIND T7_E2 = UPLIT(RCLK_ENB0 R_CLK_ENB LTCH_DATA_ENB C_LTCH1 C_LTCHS GRANT BUSREQ RD_302 ADR0L6_H NTWK);
466 BIND T7_NE1 = UPLIT(C_LTCH1 C_LTCHS TCLKD TCLKB RD_302 ADR0L6_H RCLK_ENB0 NTWK);
467
468 BIND T7_ES = PLIT( T7_E1,
469 T7_E2);
470 BIND T7_NES = PLIT( T7_NE1);
471
472
473 BIND T8_E1 = UPLIT(MNT_ENBL NTWK);
474 BIND T8_E2 = UPLIT(MNT_ENBL MNT_CLK NTWK);
475 BIND T8_NE1 = UPLIT(MNT_ENBL MNT_CLK NTWK);
476
477 BIND T8_ES = PLIT( T8_E1,
478 T8_E2);
479 BIND T8_NES = PLIT( T8_NE1);
480
481
482 BIND T9_E1 = UPLIT(REG210 RESETB_H NTWK);
483
484 BIND T9_ES = PLIT( T9_E1);
485
486
487 BIND T10_E1 = UPLIT(R_CLK_ENB T_CLK_B LTCH_DATA_ENB DATA_ENB RTN_DATA LTCH_DATA GRANT_1 NTWK);
488
489 BIND T10_ES = PLIT( T10_E1);
490
491
492 BIND T11_E1 = UPLIT(R_CLK_ENB T_CLK_B LTCH_DATA_ENB LTCH_DATA C_LTCHS C_LTCH1 NTWK);
493
494 BIND T11_ES = PLIT( T11_E1);
495
496
497 BIND T12_E1 = UPLIT(R_CLK_ENB T_CLK_B LTCH_DATA_ENB GRANT_1 C_LTCHS C_LTCH1 NTWK);
498
499 BIND T12_ES = PLIT( T12_E1);
500
501
502 BIND T13_E1 = UPLIT(R_CLK_ENB T_CLK_B LTCH_DATA_ENB C_LTCH1 C_LTCHS NTWK);
503
504 BIND T13_ES = PLIT( T13_E1);
505
506
507 BIND T14_E1 = UPLIT(R_CLK_ENB NTWK);
508
509 BIND T14_ES = PLIT( T14_E1);
510
511
512 BIND T15_E1 = UPLIT(CR_CLK_ENB CLK_ENBS NTWK);
513 BIND T15_E2 = UPLIT(DP_CLK_ENB CLK_ENBS PF_1 NTWK);
514 BIND T15_E3 = UPLIT(CLK_ENBS ENB SING_CLK CLK_RUN T_CLK WRT206 CSLBUF1 R_CLK NTWK);
515 BIND T15_NE1 = UPLIT(SING_CLK WRT206 CSLBUF1 T_CLK R_CLK NTWK);
516
517 BIND T15_ES = PLIT( T15_E1,
518 T15_E2,
519 T15_E3);
520 BIND T15_NES = PLIT( T15_NE1);
521
522
523 BIND T16_E1 = UPLIT(SING_CLK CLK_RUN ENB CLK_ENBS CR_CLK_ENB NTWK);
524
525 BIND T16_ES = PLIT( T16_E1);
526
527
528 BIND T17_E1 = UPLIT(R_DATA CMD_XCVR CSLBUF2 NTWK);
529 BIND T17_E2 = UPLIT(R_IODATA CMD_XCVR CSLBUF0 NTWK);
530 BIND T17_E3 = UPLIT(R_COMADR CMD_XCVR CSLBUF1 NTWK);
531 BIND T17_E4 = UPLIT(R_BADATA CMD_XCVR CSLBUF3 NTWK);
532 BIND T17_E5 = UPLIT(ADR0L6_L DATA_CYC STAT_RD X_D1 XMIT_DATA CMD_XCVR NTWK);
533 BIND T17_E6 = UPLIT(WRT114 RD_100 ADR0L6_L ADR1L_H CMD_XCVR T_ENB XMIT_ADR NTWK);
534 BIND T17_NE1 = UPLIT(RD_100 ADR0L6_L ADR1L_H NTWK);
535
536 BIND T17_ES = PLIT( T17_E1,
537 T17_E2,
538 T17_E3,
539 T17_E4,
540 T17_E5,
541 T17_E6);
542 BIND T17_NES = PLIT( T17_NE1);
543
544
545 BIND T18_E1 = UPLIT(R_DATA CMD_XCVR CSLBUF2 NTWK);
546 BIND T18_E2 = UPLIT(R_IODATA CMD_XCVR CSLBUF0 NTWK);
547 BIND T18_E3 = UPLIT(R_COMADR CMD_XCVR CSLBUF1 NTWK);
548 BIND T18_E4 = UPLIT(R_BADATA CMD_XCVR CSLBUF3 NTWK);
549 BIND T18_E5 = UPLIT(ADR0L6_H DATA_CYC CMD_XCVR NTWK);
550 BIND T18_E6 = UPLIT(WRT114 RD_100 ADR0L6_L ADR1L_H CMD_XCVR T_ENB XMIT_DATA NTWK);
551 BIND T18_NE1 = UPLIT(RD_100 ADR0L6_L ADR1L_H ADR0L6_H NTWK);
552
553 BIND T18_ES = PLIT( T18_E1,
554 T18_E2,
555 T18_E3,
556 T18_E4,
557 T18_E5,
558 T18_E6);
559 BIND T18_NES = PLIT( T18_NE1);
560
561
562 BIND T19_E1 = UPLIT(DATAACK RD_0 DATA_ACK DATA_ENB R_CLK_L RTN_DATA MEMH NTWK);
563 BIND T19_E2 = UPLIT(R_CLK_L DATA_ENB RTN_DATA NTWK);
564 BIND T19_E3 = UPLIT(DATA_ACK DATA_ENB RD_0 DATAACK NTWK);
565 BIND T19_NE1 = UPLIT(R_CLK_L MEMH DATA_ACK DATAACK RD_0 NTWK);
566
567 BIND T19_ES = PLIT( T19_E1,
568 T19_E2,
569 T19_E3);
570 BIND T19_NES = PLIT( T19_NE1);
571
572
573 BIND T20_E1 = UPLIT(DATAACK RD_0 DATA_ACK DATA_ENB R_CLK_L RTN_DATA NTWK);
574 BIND T20_E2 = UPLIT(R_CLK_L DATA_ENB RTN_DATA NTWK);
575
576 BIND T20_ES = PLIT( T20_E1,
577 T20_E2);
578
579
580 BIND T21_E1 = UPLIT(RTN_DATA DATA_ENB DATA_ACK DATAACK NTWK);
581 BIND T21_E2 = UPLIT(RTN_DATA DATA_ENB NTWK);
582
583 BIND T21_ES = PLIT( T21_E1,
584 T21_E2);
585
586
587 BIND T22_E1 = UPLIT(RTN_DATA DATA_ENB DATA_ACK DATAACK NTWK);
588 BIND T22_E2 = UPLIT(RTN_DATA DATA_ENB NTWK);
589
590 BIND T22_ES = PLIT( T22_E1,
591 T22_E2);
592
593
594 BIND T23_E1 = UPLIT(DATA_ENB DATA_ACK DATAACK NTWK);
595
596 BIND T23_ES = PLIT( T23_E1);
597
598
599 BIND T24_E1 = UPLIT(RDATA_03 BUS0_3 CSLBUF0 NTWK);
600 BIND T24_E2 = UPLIT(RDATA_02 BUS0_3 CSLBUF1 NTWK);
601 BIND T24_E3 = UPLIT(RDATA_01 BUS0_3 CSLBUF2 NTWK);
602 BIND T24_E4 = UPLIT(RDATA_00 BUS0_3 CSLBUF3 NTWK);
603 BIND T24_E5 = UPLIT(ADR0L6_L DATA_CYC STAT_RD X_D1 XMIT_DATA BUS0_3 NTWK);
604 BIND T24_E6 = UPLIT(WRT112 R_CLK_B RD_0 ADR0L6_H ADR1L_H BUS0_3 T_ENB XMIT_ADR NTWK);
605 BIND T24_NE1 = UPLIT(RD_0 ADR0L6_H ADR0L6_L WRT112 R_CLK_B NTWK);
606
607 BIND T24_ES = PLIT( T24_E1,
608 T24_E2,
609 T24_E3,
610 T24_E4,
611 T24_E5,
612 T24_E6);
613 BIND T24_NES = PLIT( T24_NE1);
614
615
616 BIND T25_E1 = UPLIT(RDATA_03 BUS0_3 CSLBUF0 NTWK);
617 BIND T25_E2 = UPLIT(RDATA_02 BUS0_3 CSLBUF1 NTWK);
618 BIND T25_E3 = UPLIT(RDATA_01 BUS0_3 CSLBUF2 NTWK);
619 BIND T25_E4 = UPLIT(RDATA_00 BUS0_3 CSLBUF3 NTWK);
620 BIND T25_E5 = UPLIT(ADR0L6_H DATA_CYC BUS0_3 NTWK);
621 BIND T25_E6 = UPLIT(WRT112 R_CLK_B RD_0 ADR0L6_H ADR1L_H BUS0_3 T_ENB XMIT_DATA X_D1 NTWK);
622 BIND T25_NE1 = UPLIT(RD_0 ADR0L6_H ADR0L6_L WRT112 R_CLK_B NTWK);
623
624 BIND T25_ES = PLIT( T25_E1,
625 T25_E2,
626 T25_E3,
627 T25_E4,
628 T25_E5,
629 T25_E6);
630 BIND T25_NES = PLIT( T25_NE1);
631
632
633 BIND T26_E1 = UPLIT(RDATA_11 NTWK);
634 BIND T26_E2 = UPLIT(RDATA_10 NTWK);
635 BIND T26_E3 = UPLIT(RDATA_09 NTWK);
636 BIND T26_E4 = UPLIT(RDATA_08 NTWK);
637 BIND T26_E5 = UPLIT(RDATA_07 NTWK);
638 BIND T26_E6 = UPLIT(RDATA_06 NTWK);
639 BIND T26_E7 = UPLIT(RDATA_05 NTWK);
640 BIND T26_E8 = UPLIT(RDATA_04 NTWK);
641 BIND T26_E9 = UPLIT(DATA_CYC STAT_RD X_D1 XMIT_DATA NTWK);
642 BIND T26_E10 = UPLIT(BUS4_7 NTWK);
643 BIND T26_E11 = UPLIT(ADR0L6_L BUS8_11 NTWK);
644 BIND T26_E12 = UPLIT(BUS4_7 NTWK);
645 BIND T26_E13 = UPLIT(BUS8_11 NTWK);
646 BIND T26_E14 = UPLIT(WRT110 RD_0 T_ENB XMIT_ADR R_CLK_B NTWK);
647 BIND T26_NE1 = UPLIT(R_CLK_B RD_0 WRT110 ADR0L6_L NTWK);
648
649 BIND T26_ES = PLIT( T26_E1,
650 T26_E2,
651 T26_E3,
652 T26_E4,
653 T26_E5,
654 T26_E6,
655 T26_E7,
656 T26_E8,
657 T26_E9,
658 T26_E10,
659 T26_E11,
660 T26_E12,
661 T26_E13,
662 T26_E14);
663 BIND T26_NES = PLIT( T26_NE1);
664
665
666 BIND T27_E1 = UPLIT(RDATA_11 NTWK);
667 BIND T27_E2 = UPLIT(RDATA_10 NTWK);
668 BIND T27_E3 = UPLIT(RDATA_09 NTWK);
669 BIND T27_E4 = UPLIT(RDATA_08 NTWK);
670 BIND T27_E5 = UPLIT(RDATA_07 NTWK);
671 BIND T27_E6 = UPLIT(RDATA_06 NTWK);
672 BIND T27_E7 = UPLIT(RDATA_05 NTWK);
673 BIND T27_E8 = UPLIT(RDATA_04 NTWK);
674 BIND T27_E9 = UPLIT(DATA_CYC NTWK);
675 BIND T27_E10 = UPLIT(BUS4_7 NTWK);
676 BIND T27_E11 = UPLIT(BUS8_11 NTWK);
677 BIND T27_E12 = UPLIT(BUS4_7 NTWK);
678 BIND T27_E13 = UPLIT(ADR0L6_L BUS8_11 NTWK);
679 BIND T27_E14 = UPLIT(WRT110 RD_0 T_ENB XMIT_DATA X_D1 R_CLK_B NTWK);
680 BIND T27_NE1 = UPLIT(ADR0L6_L RD_0 WRT110 R_CLK_B NTWK);
681
682 BIND T27_ES = PLIT( T27_E1,
683 T27_E2,
684 T27_E3,
685 T27_E4,
686 T27_E5,
687 T27_E6,
688 T27_E7,
689 T27_E8,
690 T27_E9,
691 T27_E10,
692 T27_E11,
693 T27_E12,
694 T27_E13,
695 T27_E14);
696 BIND T27_NES = PLIT( T27_NE1);
697
698
699 BIND T28_E1 = UPLIT(RDATA_19 NTWK);
700 BIND T28_E2 = UPLIT(RDATA_18 NTWK);
701 BIND T28_E3 = UPLIT(RDATA_17 NTWK);
702 BIND T28_E4 = UPLIT(RDATA_16 NTWK);
703 BIND T28_E5 = UPLIT(RDATA_15 NTWK);
704 BIND T28_E6 = UPLIT(RDATA_14 NTWK);
705 BIND T28_E7 = UPLIT(RDATA_13 NTWK);
706 BIND T28_E8 = UPLIT(RDATA_12 NTWK);
707 BIND T28_E9 = UPLIT(DATA_CYC STAT_RD X_D1 XMIT_DATA NTWK);
708 BIND T28_E10 = UPLIT(BUS12_15 NTWK);
709 BIND T28_E11 = UPLIT(ADR0L6_L BUS16_19 NTWK);
710 BIND T28_E12 = UPLIT(T_ENB R_CLK_B BUS12_15 NTWK);
711 BIND T28_E13 = UPLIT(T_ENB_A R_CLK_A BUS16_19 NTWK);
712 BIND T28_E14 = UPLIT(WRT106 RD_0 NTWK);
713 BIND T28_NE1 = UPLIT(ADR0L6_L RD_0 WRT106 R_CLK_B R_CLK_A NTWK);
714
715 BIND T28_ES = PLIT( T28_E1,
716 T28_E2,
717 T28_E3,
718 T28_E4,
719 T28_E5,
720 T28_E6,
721 T28_E7,
722 T28_E8,
723 T28_E9,
724 T28_E10,
725 T28_E11,
726 T28_E12,
727 T28_E13,
728 T28_E14);
729 BIND T28_NES = PLIT( T28_NE1);
730
731
732 BIND T29_E1 = UPLIT(RDATA_19 NTWK);
733 BIND T29_E2 = UPLIT(RDATA_18 NTWK);
734 BIND T29_E3 = UPLIT(RDATA_17 NTWK);
735 BIND T29_E4 = UPLIT(RDATA_16 NTWK);
736 BIND T29_E5 = UPLIT(RDATA_15 NTWK);
737 BIND T29_E6 = UPLIT(RDATA_14 NTWK);
738 BIND T29_E7 = UPLIT(RDATA_13 NTWK);
739 BIND T29_E8 = UPLIT(RDATA_12 NTWK);
740 BIND T29_E9 = UPLIT(DATA_CYC NTWK);
741 BIND T29_E10 = UPLIT(BUS12_15 NTWK);
742 BIND T29_E11 = UPLIT(BUS16_19 NTWK);
743 BIND T29_E12 = UPLIT(T_ENB R_CLK_B BUS12_15 NTWK);
744 BIND T29_E13 = UPLIT(ADR0L6_L T_ENB_A R_CLK_A BUS16_19 NTWK);
745 BIND T29_E14 = UPLIT(WRT106 RD_0 NTWK);
746 BIND T29_NE1 = UPLIT(ADR0L6_L RD_0 WRT106 R_CLK_B R_CLK_A NTWK);
747
748 BIND T29_ES = PLIT( T29_E1,
749 T29_E2,
750 T29_E3,
751 T29_E4,
752 T29_E5,
753 T29_E6,
754 T29_E7,
755 T29_E8,
756 T29_E9,
757 T29_E10,
758 T29_E11,
759 T29_E12,
760 T29_E13,
761 T29_E14);
762 BIND T29_NES = PLIT( T29_NE1);
763
764
765 BIND T30_E1 = UPLIT(RDATA_27 NTWK);
766 BIND T30_E2 = UPLIT(RDATA_26 NTWK);
767 BIND T30_E3 = UPLIT(RDATA_25 NTWK);
768 BIND T30_E4 = UPLIT(RDATA_24 NTWK);
769 BIND T30_E5 = UPLIT(RDATA_23 NTWK);
770 BIND T30_E6 = UPLIT(RDATA_22 NTWK);
771 BIND T30_E7 = UPLIT(RDATA_21 NTWK);
772 BIND T30_E8 = UPLIT(RDATA_20 NTWK);
773 BIND T30_E9 = UPLIT(DATA_CYC STAT_RD X_D1 XMIT_DATA NTWK);
774 BIND T30_E10 = UPLIT(BUS20_23 NTWK);
775 BIND T30_E11 = UPLIT(ADR0L6_L BUS24_27 NTWK);
776 BIND T30_E12 = UPLIT(BUS20_23 NTWK);
777 BIND T30_E13 = UPLIT(BUS24_27 NTWK);
778 BIND T30_E14 = UPLIT(R_CLK_A T_ENB_A WRT104 RD_0 NTWK);
779 BIND T30_NE1 = UPLIT(ADR0L6_L RD_0 WRT104 R_CLK_A NTWK);
780
781 BIND T30_ES = PLIT( T30_E1,
782 T30_E2,
783 T30_E3,
784 T30_E4,
785 T30_E5,
786 T30_E6,
787 T30_E7,
788 T30_E8,
789 T30_E9,
790 T30_E10,
791 T30_E11,
792 T30_E12,
793 T30_E13,
794 T30_E14);
795 BIND T30_NES = PLIT( T30_NE1);
796
797
798 BIND T31_E1 = UPLIT(RDATA_27 NTWK);
799 BIND T31_E2 = UPLIT(RDATA_26 NTWK);
800 BIND T31_E3 = UPLIT(RDATA_25 NTWK);
801 BIND T31_E4 = UPLIT(RDATA_24 NTWK);
802 BIND T31_E5 = UPLIT(RDATA_23 NTWK);
803 BIND T31_E6 = UPLIT(RDATA_22 NTWK);
804 BIND T31_E7 = UPLIT(RDATA_21 NTWK);
805 BIND T31_E8 = UPLIT(RDATA_20 NTWK);
806 BIND T31_E9 = UPLIT(DATA_CYC NTWK);
807 BIND T31_E10 = UPLIT(BUS20_23 NTWK);
808 BIND T31_E11 = UPLIT(BUS24_27 NTWK);
809 BIND T31_E12 = UPLIT(BUS20_23 NTWK);
810 BIND T31_E13 = UPLIT(ADR0L6_L BUS24_27 NTWK);
811 BIND T31_E14 = UPLIT(R_CLK_A T_ENB_A WRT104 RD_0 NTWK);
812 BIND T31_NE1 = UPLIT(ADR0L6_L RD_0 WRT104 R_CLK_A NTWK);
813
814 BIND T31_ES = PLIT( T31_E1,
815 T31_E2,
816 T31_E3,
817 T31_E4,
818 T31_E5,
819 T31_E6,
820 T31_E7,
821 T31_E8,
822 T31_E9,
823 T31_E10,
824 T31_E11,
825 T31_E12,
826 T31_E13,
827 T31_E14);
828 BIND T31_NES = PLIT( T31_NE1);
829
830
831 BIND T32_E1 = UPLIT(RDATA_35 NTWK);
832 BIND T32_E2 = UPLIT(RDATA_34 NTWK);
833 BIND T32_E3 = UPLIT(RDATA_33 NTWK);
834 BIND T32_E4 = UPLIT(RDATA_32 NTWK);
835 BIND T32_E5 = UPLIT(RDATA_31 NTWK);
836 BIND T32_E6 = UPLIT(RDATA_30 NTWK);
837 BIND T32_E7 = UPLIT(RDATA_29 NTWK);
838 BIND T32_E8 = UPLIT(RDATA_28 NTWK);
839 BIND T32_E9 = UPLIT(DATA_CYC STAT_RD X_D1 XMIT_DATA NTWK);
840 BIND T32_E10 = UPLIT(BUS28_31 NTWK);
841 BIND T32_E11 = UPLIT(ADR0L6_L BUS32_35 NTWK);
842 BIND T32_E12 = UPLIT(BUS28_31 NTWK);
843 BIND T32_E13 = UPLIT(BUS32_35 NTWK);
844 BIND T32_E14 = UPLIT(R_CLK_A T_ENB_A WRT102 RD_0 NTWK);
845 BIND T32_NE1 = UPLIT(RD_0 WRT102 ADR0L6_L R_CLK_A NTWK);
846
847 BIND T32_ES = PLIT( T32_E1,
848 T32_E2,
849 T32_E3,
850 T32_E4,
851 T32_E5,
852 T32_E6,
853 T32_E7,
854 T32_E8,
855 T32_E9,
856 T32_E10,
857 T32_E11,
858 T32_E12,
859 T32_E13,
860 T32_E14);
861 BIND T32_NES = PLIT( T32_NE1);
862
863
864 BIND T33_E1 = UPLIT(RDATA_35 NTWK);
865 BIND T33_E2 = UPLIT(RDATA_34 NTWK);
866 BIND T33_E3 = UPLIT(RDATA_33 NTWK);
867 BIND T33_E4 = UPLIT(RDATA_32 NTWK);
868 BIND T33_E5 = UPLIT(RDATA_31 NTWK);
869 BIND T33_E6 = UPLIT(RDATA_30 NTWK);
870 BIND T33_E7 = UPLIT(RDATA_29 NTWK);
871 BIND T33_E8 = UPLIT(RDATA_28 NTWK);
872 BIND T33_E9 = UPLIT(DATA_CYC NTWK);
873 BIND T33_E10 = UPLIT(BUS28_31 NTWK);
874 BIND T33_E11 = UPLIT(BUS32_35 NTWK);
875 BIND T33_E12 = UPLIT(BUS28_31 NTWK);
876 BIND T33_E13 = UPLIT(ADR0L6_L BUS32_35 NTWK);
877 BIND T33_E14 = UPLIT(R_CLK_A T_ENB_A WRT102 RD_0 NTWK);
878 BIND T33_NE1 = UPLIT(RD_0 WRT102 ADR0L6_L R_CLK_A NTWK);
879
880 BIND T33_ES = PLIT( T33_E1,
881 T33_E2,
882 T33_E3,
883 T33_E4,
884 T33_E5,
885 T33_E6,
886 T33_E7,
887 T33_E8,
888 T33_E9,
889 T33_E10,
890 T33_E11,
891 T33_E12,
892 T33_E13,
893 T33_E14);
894 BIND T33_NES = PLIT( T33_NE1);
895
896
897 BIND T34_E1 = UPLIT(XMIT_ENBS NTWK);
898 BIND T34_E2 = UPLIT(XMIT_ENBS NTWK);
899 BIND T34_E3 = UPLIT(XMIT_ENBS NTWK);
900 BIND T34_E4 = UPLIT(XMIT_ENBS NTWK);
901
902 BIND T34_ES = PLIT( T34_E1,
903 T34_E2,
904 T34_E3,
905 T34_E4);
906
907
908 BIND T35_E1 = UPLIT(XMIT_ENBS NTWK);
909 BIND T35_E2 = UPLIT(XMIT_ENBS NTWK);
910 BIND T35_E3 = UPLIT(XMIT_ENBS NTWK);
911 BIND T35_E4 = UPLIT(XMIT_ENBS NTWK);
912
913 BIND T35_ES = PLIT( T35_E1,
914 T35_E2,
915 T35_E3,
916 T35_E4);
917
918
919 BIND T36_E1 = UPLIT(XMIT_ENBS NTWK);
920 BIND T36_E2 = UPLIT(XMIT_ENBS NTWK);
921 BIND T36_E3 = UPLIT(XMIT_ENBS NTWK);
922 BIND T36_E4 = UPLIT(XMIT_ENBS NTWK);
923
924 BIND T36_ES = PLIT( T36_E1,
925 T36_E2,
926 T36_E3,
927 T36_E4);
928
929
930 BIND T37_E1 = UPLIT(XMIT_ENBS NTWK);
931 BIND T37_E2 = UPLIT(XMIT_ENBS NTWK);
932 BIND T37_E3 = UPLIT(XMIT_ENBS NTWK);
933 BIND T37_E4 = UPLIT(XMIT_ENBS NTWK);
934
935 BIND T37_ES = PLIT( T37_E1,
936 T37_E2,
937 T37_E3,
938 T37_E4);
939
940
941 BIND T38_E1 = UPLIT(STAT_RD NTWK);
942
943 BIND T38_ES = PLIT( T38_E1);
944
945
946 BIND T39_E1 = UPLIT(STAT_RD NTWK);
947
948 BIND T39_ES = PLIT( T39_E1);
949
950
951 BIND T40_E1 = UPLIT(STAT_RD NTWK);
952
953 BIND T40_ES = PLIT( T40_E1);
954
955
956 BIND T41_E1 = UPLIT(STAT_RD NTWK);
957
958 BIND T41_ES = PLIT( T41_E1);
959
960
961 BIND T42_E1 = UPLIT(STAT_RD NTWK);
962
963 BIND T42_ES = PLIT( T42_E1);
964
965
966 BIND T43_E1 = UPLIT(STAT_RD NTWK);
967
968 BIND T43_ES = PLIT( T43_E1);
969
970
971 BIND T44_E1 = UPLIT(STAT_RD NTWK);
972
973 BIND T44_ES = PLIT( T44_E1);
974
975
976 BIND T45_E1 = UPLIT(STAT_RD NTWK);
977
978 BIND T45_ES = PLIT( T45_E1);
979
980
981 BIND T46_E1 = UPLIT(STAT_RD NTWK);
982
983 BIND T46_ES = PLIT( T46_E1);
984
985
986 BIND T47_E1 = UPLIT(CRA_R_CLK T_CLK_EN C_R_C_E C_T_C_E DFN_11 NTWK);
987
988 BIND T47_ES = PLIT( T47_E1);
989
990
991 BIND T48_E1 = UPLIT(C_R_C_E CRA_R_CLK NTWK);
992
993 BIND T48_ES = PLIT( T48_E1);
994
995
996 BIND T49_E1 = UPLIT(C_T_C_E T_CLK_EN NTWK);
997
998 BIND T49_ES = PLIT( T49_E1);
999
1000
1001 BIND T50_E1 = UPLIT(DFN_0 CRM_WRT WRT204 CSLBUF5 NTWK);
1002 BIND T50_NE1 = UPLIT(DFN_0 CRM_WRT WRT204 NTWK);
1003
1004 BIND T50_ES = PLIT( T50_E1);
1005 BIND T50_NES = PLIT( T50_NE1);
1006
1007
1008 BIND T51_E1 = UPLIT(DFN_1 DFN_4 NTWK);
1009
1010 BIND T51_ES = PLIT( T51_E1);
1011
1012
1013 BIND T52_E1 = UPLIT(DFN_2 DFN_5 NTWK);
1014
1015 BIND T52_ES = PLIT( T52_E1);
1016
1017
1018 BIND T53_E1 = UPLIT(CRM_RESET WRT204 NTWK);
1019
1020 BIND T53_ES = PLIT( T53_E1);
1021
1022
1023 BIND T54_E1 = UPLIT(CRM_WRT NTWK);
1024
1025 BIND T54_ES = PLIT( T54_E1);
1026
1027
1028 BIND T55_E1 = UPLIT(CRM_ADR_LD DFN_1 NTWK);
1029 BIND T55_NE1 = UPLIT(CRM_ADR_LD DFN_1 NTWK);
1030
1031 BIND T55_ES = PLIT( T55_E1);
1032 BIND T55_NES = PLIT( T55_NE1);
1033
1034
1035 BIND T56_E1 = UPLIT(REG204 NTWK);
1036
1037 BIND T56_ES = PLIT( T56_E1);
1038
1039
1040 BIND T57_E1 = UPLIT(HLT_LP CMD_LD CRAM_CLK HALT_LOOP NTWK);
1041 BIND T57_E2 = UPLIT(HLT_LP HALT_LOOP NTWK);
1042 BIND T57_NE1 = UPLIT(HALT_LOOP NTWK);
1043
1044 BIND T57_ES = PLIT( T57_E1,
1045 T57_E2);
1046 BIND T57_NES = PLIT( T57_NE1);
1047
1048
1049 BIND T58_E1 = UPLIT(HLT_LP CMD_LD NTWK);
1050
1051 BIND T58_ES = PLIT( T58_E1);
1052
1053
1054 BIND T59_E1 = UPLIT(HLT_LP NTWK);
1055
1056 BIND T59_ES = PLIT( T59_E1);
1057
1058
1059 BIND T60_E1 = UPLIT(HLT_LP CMD_LD CRAM_CLK NTWK);
1060
1061 BIND T60_ES = PLIT( T60_E1);
1062
1063
1064 BIND T61_E1 = UPLIT(HLT_LP NTWK);
1065
1066 BIND T61_ES = PLIT( T61_E1);
1067
1068
1069 BIND T62_E1 = UPLIT(HLT_LP CMD_LD NTWK);
1070
1071 BIND T62_ES = PLIT( T62_E1);
1072
1073
1074 BIND T63_E1 = UPLIT(WRT212 RUN_1 RUN NTWK);
1075 BIND T63_E2 = UPLIT(WRT212 EXEC_B EXEC NTWK);
1076 BIND T63_E3 = UPLIT(WRT212 CONT_H CONT NTWK);
1077 BIND T63_E4 = UPLIT(RUN_1 RUN NTWK);
1078 BIND T63_E5 = UPLIT(EXEC_B EXEC NTWK);
1079 BIND T63_E6 = UPLIT(CONT_H CONT NTWK);
1080 BIND T63_NE1 = UPLIT(WRT212 RUN NTWK);
1081 BIND T63_NE2 = UPLIT(WRT212 EXEC NTWK);
1082 BIND T63_NE3 = UPLIT(WRT212 CONT NTWK);
1083
1084 BIND T63_ES = PLIT( T63_E1,
1085 T63_E2,
1086 T63_E3,
1087 T63_E4,
1088 T63_E5,
1089 T63_E6);
1090 BIND T63_NES = PLIT( T63_NE1,
1091 T63_NE2,
1092 T63_NE3);
1093
1094
1095 BIND T64_E1 = UPLIT(RUN_1 NTWK);
1096 BIND T64_E2 = UPLIT(EXEC_B NTWK);
1097 BIND T64_E3 = UPLIT(CONT_H NTWK);
1098
1099 BIND T64_ES = PLIT( T64_E1,
1100 T64_E2,
1101 T64_E3);
1102
1103
1104 BIND T65_E1 = UPLIT(RUN_1 NTWK);
1105 BIND T65_E2 = UPLIT(EXEC_B NTWK);
1106 BIND T65_E3 = UPLIT(CONT_H NTWK);
1107
1108 BIND T65_ES = PLIT( T65_E1,
1109 T65_E2,
1110 T65_E3);
1111
1112
1113 BIND T66_E1 = UPLIT(RUN_1 NTWK);
1114 BIND T66_E2 = UPLIT(EXEC_B NTWK);
1115 BIND T66_E3 = UPLIT(CONT_H NTWK);
1116
1117 BIND T66_ES = PLIT( T66_E1,
1118 T66_E2,
1119 T66_E3);
1120
1121
1122 BIND T67_E1 = UPLIT(RUN_1 NTWK);
1123 BIND T67_E2 = UPLIT(EXEC_B NTWK);
1124 BIND T67_E3 = UPLIT(CONT_H NTWK);
1125
1126 BIND T67_ES = PLIT( T67_E1,
1127 T67_E2,
1128 T67_E3);
1129
1130
1131 BIND T68_E1 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1132 BIND T68_E2 = UPLIT(RPAR_LEFT R_PAR_LFT XMIT_PAR_LFT NTWK);
1133 BIND T68_E3 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1134 BIND T68_E4 = UPLIT(R_PAR_LFT XMIT_PAR_LFT RPAR_LEFT NTWK);
1135 BIND T68_E5 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1136 BIND T68_E6 = UPLIT(R_PAR_LFT XMIT_PAR_LFT RPAR_LEFT NTWK);
1137 BIND T68_E7 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1138 BIND T68_E8 = UPLIT(RPAR_LEFT R_PAR_LFT XMIT_PAR_LFT NTWK);
1139 BIND T68_E9 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1140 BIND T68_E10 = UPLIT(R_PAR_LFT RPAR_LEFT XMIT_PAR_LFT NTWK);
1141 BIND T68_E11 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1142 BIND T68_E12 = UPLIT(R_PAR_LFT RPAR_LEFT XMIT_PAR_LFT NTWK);
1143 BIND T68_E13 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1144 BIND T68_E14 = UPLIT(R_PAR_LFT RPAR_LEFT XMIT_PAR_LFT NTWK);
1145 BIND T68_E15 = UPLIT(R_PAR_RT RPAR_RIGHT XMIT_PAR_RT NTWK);
1146 BIND T68_E16 = UPLIT(R_PAR_LFT RPAR_LEFT XMIT_PAR_LFT NTWK);
1147
1148 BIND T68_ES = PLIT( T68_E1,
1149 T68_E2,
1150 T68_E3,
1151 T68_E4,
1152 T68_E5,
1153 T68_E6,
1154 T68_E7,
1155 T68_E8,
1156 T68_E9,
1157 T68_E10,
1158 T68_E11,
1159 T68_E12,
1160 T68_E13,
1161 T68_E14,
1162 T68_E15,
1163 T68_E16);
1164
1165
1166 BIND T69_E1 = UPLIT(R_CLK CLK_ENBS ENB T_CNT_DN READ_DLY RD_DLY WRT_DLY CLK_RUN NTWK);
1167 BIND T69_E2 = UPLIT(R_CLK PF_1 CLK_ENBS ENB T_CNT_DN READ_DLY RD_DLY WRT_DLY CLK_RUN NTWK);
1168 BIND T69_E3 = UPLIT(R_CLK CLK_ENBS ENB SING_CLK NTWK);
1169 BIND T69_E4 = UPLIT(R_CLK CLK_ENBS ENB T_CNT_DN READ_DLY RD_DLY WRT_DLY CLK_RUN NTWK);
1170
1171 BIND T69_ES = PLIT( T69_E1,
1172 T69_E2,
1173 T69_E3,
1174 T69_E4);
1175
1176
1177 BIND T70_E1 = UPLIT(CLK_ENBS ENB SING_CLK CLK_RUN NTWK);
1178
1179 BIND T70_ES = PLIT( T70_E1);
1180
1181
1182 BIND T71_E1 = UPLIT(CLK_ENBS ENB CLK_RUN SING_CLK NTWK);
1183
1184 BIND T71_ES = PLIT( T71_E1);
1185
1186
1187 BIND T72_E1 = UPLIT(T_COUNT_DONE NTWK);
1188 BIND T72_E2 = UPLIT(T_COUNT_DONE NTWK);
1189 BIND T72_E3 = UPLIT(T_COUNT_DONE NTWK);
1190 BIND T72_E4 = UPLIT(T_COUNT_DONE NTWK);
1191
1192 BIND T72_ES = PLIT( T72_E1,
1193 T72_E2,
1194 T72_E3,
1195 T72_E4);
1196
1197
1198 BIND T73_E1 = UPLIT(T_COUNT_DONE NTWK);
1199 BIND T73_E2 = UPLIT(T_COUNT_DONE NTWK);
1200
1201 BIND T73_ES = PLIT( T73_E1,
1202 T73_E2);
1203
1204
1205 BIND T74_E1 = UPLIT(T_COUNT_DONE NTWK);
1206 BIND T74_E2 = UPLIT(T_COUNT_DONE NTWK);
1207 BIND T74_E3 = UPLIT(T_COUNT_DONE NTWK);
1208
1209 BIND T74_ES = PLIT( T74_E1,
1210 T74_E2,
1211 T74_E3);
1212
1213
1214 BIND T75_E1 = UPLIT(PE PE_LTCH CPU_PE REC_BUS_PE NTWK);
1215
1216 BIND T75_ES = PLIT( T75_E1);
1217
1218
1219 BIND T76_E1 = UPLIT(PE PE_LTCH CPU_PE REC_BUS_PE DP_PAR_ERR RAM_ER_DLY NTWK);
1220
1221 BIND T76_ES = PLIT( T76_E1);
1222
1223
1224 BIND T77_E1 = UPLIT(PE PE_LTCH CPU_PE REC_BUS_PE NTWK);
1225
1226 BIND T77_ES = PLIT( T77_E1);
1227
1228
1229 BIND T78_E1 = UPLIT(CRM_DET PE PE_LTCH CPU_PE REC_BUS_PE NTWK);
1230
1231 BIND T78_ES = PLIT( T78_E1);
1232
1233
1234 BIND T79_E1 = UPLIT(CRA_PE CRA_PE_LTCH PE_LTCH NTWK);
1235 BIND T79_E2 = UPLIT(PE PE_LTCH CPU_PE CRM_DET PE_DET NTWK);
1236 BIND T79_E3 = UPLIT(PE_LTCH CPU_PE CRM_DET PE REC_BUS_PE NTWK);
1237 BIND T79_NE1 = UPLIT(PE NTWK);
1238
1239 BIND T79_ES = PLIT( T79_E1,
1240 T79_E2,
1241 T79_E3);
1242 BIND T79_NES = PLIT( T79_NE1);
1243
1244
1245 BIND T80_E1 = UPLIT(CRM_PE_LTCH CRM_PE PE_LTCH NTWK);
1246 BIND T80_E2 = UPLIT(PE_LTCH CPU_PE CRM_DET PE_DET NTWK);
1247 BIND T80_E3 = UPLIT(PE_LTCH CPU_PE CRM_DET REC_BUS_PE NTWK);
1248
1249 BIND T80_ES = PLIT( T80_E1,
1250 T80_E2,
1251 T80_E3);
1252
1253
1254 BIND T81_E1 = UPLIT(PE_LTCH PE_DET NTWK);
1255
1256 BIND T81_ES = PLIT( T81_E1);
1257
1258
1259 BIND T82_E1 = UPLIT(PE_LTCH CPU_PE CRM_DET PE_DET NTWK);
1260 BIND T82_E2 = UPLIT(PE_LTCH CRA_PE_LTCH CRA_PE PE_DET NTWK);
1261
1262 BIND T82_ES = PLIT( T82_E1,
1263 T82_E2);
1264
1265
1266 BIND T83_E1 = UPLIT(ENABLE_PE NTWK);
1267
1268 BIND T83_ES = PLIT( T83_E1);
1269
1270
1271 BIND T84_E1 = UPLIT(REC_PE NTWK);
1272 BIND T84_E2 = UPLIT(REC_PE NTWK);
1273 BIND T84_E3 = UPLIT(REC_PE NTWK);
1274 BIND T84_E4 = UPLIT(REC_PE NTWK);
1275 BIND T84_E5 = UPLIT(REC_PE NTWK);
1276 BIND T84_E6 = UPLIT(REC_PE NTWK);
1277 BIND T84_E7 = UPLIT(REC_PE NTWK);
1278 BIND T84_E8 = UPLIT(REC_PE NTWK);
1279
1280 BIND T84_ES = PLIT( T84_E1,
1281 T84_E2,
1282 T84_E3,
1283 T84_E4,
1284 T84_E5,
1285 T84_E6,
1286 T84_E7,
1287 T84_E8);
1288
1289
1290 BIND T85_E1 = UPLIT(REC_PE REC_PE_LTCH RECEIVE_PE NTWK);
1291 BIND T85_E2 = UPLIT(DP_PE_LTCH DP_PAR_ERR DP_PE NTWK);
1292 BIND T85_E3 = UPLIT(RAM_ER_DLY RAM_ER_LTCH RAM_ERROR NTWK);
1293
1294 BIND T85_ES = PLIT( T85_E1,
1295 T85_E2,
1296 T85_E3);
1297
1298
1299 BIND T86_E1 = UPLIT(MEM_PAR_ERR NTWK);
1300 BIND T86_E2 = UPLIT(PE_LTCH NTWK);
1301
1302 BIND T86_ES = PLIT( T86_E1,
1303 T86_E2);
1304
1305
1306 BIND T87_E1 = UPLIT(TEN_INT_LTCH TEN_INT NTWK);
1307 BIND T87_E2 = UPLIT(TEN_INT_LTCH TEN_INT NTWK);
1308 BIND T87_NE1 = UPLIT(TEN_INT NTWK);
1309
1310 BIND T87_ES = PLIT( T87_E1,
1311 T87_E2);
1312 BIND T87_NES = PLIT( T87_NE1);
1313
1314
1315 BIND T88_E1 = UPLIT(TEN_INT_LTCH NTWK);
1316 BIND T88_E2 = UPLIT(TEN_INT_LTCH DP_RESET NTWK);
1317
1318 BIND T88_ES = PLIT( T88_E1,
1319 T88_E2);
1320
1321
1322 BIND T89_E1 = UPLIT(SHFT_LOGIC NTWK);
1323 BIND T89_E2 = UPLIT(SHFT_LOGIC NTWK);
1324
1325 BIND T89_ES = PLIT( T89_E1,
1326 T89_E2);
1327
1328
1329 BIND T90_E1 = UPLIT(SHFT_LOGIC NTWK);
1330 BIND T90_E2 = UPLIT(SHFT_LOGIC NTWK);
1331
1332 BIND T90_ES = PLIT( T90_E1,
1333 T90_E2);
1334
1335
1336 BIND T91_E1 = UPLIT(SHFT_LOGIC NTWK);
1337 BIND T91_E2 = UPLIT(SHFT_LOGIC NTWK);
1338
1339 BIND T91_ES = PLIT( T91_E1,
1340 T91_E2);
1341
1342
1343 BIND T92_E1 = UPLIT(MEM_BUSY NTWK);
1344
1345 BIND T92_ES = PLIT( T92_E1);
1346
1347
1348 BIND T93_E1 = UPLIT(PI_REQ1 INT_10 WRT116 NTWK);
1349 BIND T93_E2 = UPLIT(PI_REQ2 INT_10 WRT116 NTWK);
1350 BIND T93_E3 = UPLIT(PI_REQ3 INT_10 WRT116 NTWK);
1351 BIND T93_E4 = UPLIT(PI_REQ4 INT_10 WRT116 NTWK);
1352 BIND T93_E5 = UPLIT(PI_REQ5 INT_10 WRT116 NTWK);
1353 BIND T93_E6 = UPLIT(PI_REQ6 INT_10 WRT116 NTWK);
1354 BIND T93_E7 = UPLIT(PI_REQ7 INT_10 WRT116 NTWK);
1355 BIND T93_E8 = UPLIT(PI_REQ1 INT_10 WRT116 NTWK);
1356 BIND T93_E9 = UPLIT(PI_REQ2 INT_10 WRT116 NTWK);
1357 BIND T93_E10 = UPLIT(PI_REQ3 INT_10 WRT116 NTWK);
1358 BIND T93_E11 = UPLIT(PI_REQ4 INT_10 WRT116 NTWK);
1359 BIND T93_E12 = UPLIT(PI_REQ5 INT_10 WRT116 NTWK);
1360 BIND T93_E13 = UPLIT(PI_REQ6 INT_10 WRT116 NTWK);
1361 BIND T93_E14 = UPLIT(PI_REQ7 INT_10 WRT116 NTWK);
1362
1363 BIND T93_ES = PLIT( T93_E1,
1364 T93_E2,
1365 T93_E3,
1366 T93_E4,
1367 T93_E5,
1368 T93_E6,
1369 T93_E7,
1370 T93_E8,
1371 T93_E9,
1372 T93_E10,
1373 T93_E11,
1374 T93_E12,
1375 T93_E13,
1376 T93_E14);
1377
1378
1379 BIND T94_E1 = UPLIT(INT_10 PI_REQ1 NTWK);
1380
1381 BIND T94_ES = PLIT( T94_E1);
1382
1383
1384 BIND T95_E1 = UPLIT(PI_REQ1 INT_10 NTWK);
1385
1386 BIND T95_ES = PLIT( T95_E1);
1387
1388
1389 BIND T96_E1 = UPLIT(PF_1 PF_ST_1 ENB NTWK);
1390 BIND T96_E2 = UPLIT(PF_1 PF_ST_1 ENB NTWK);
1391 BIND T96_E3 = UPLIT(PF_1 PF_ST_1 ENB NTWK);
1392
1393 BIND T96_ES = PLIT( T96_E1,
1394 T96_E2,
1395 T96_E3);
1396
1397
1398 BIND T97_E1 = UPLIT(TRAP_EN NTWK);
1399 BIND T97_E2 = UPLIT(TRAP_EN NTWK);
1400
1401 BIND T97_ES = PLIT( T97_E1,
1402 T97_E2);
1403
1404
1405 BIND T98_E1 = UPLIT(EXEC_DRVR NTWK);
1406 BIND T98_E3 = UPLIT(EXEC_DRVR NTWK);
1407
1408 BIND T98_ES = PLIT( T98_E1,
1409 T98_E3);
1410
1411
1412 BIND T99_E1 = UPLIT(CONT_DRVR NTWK);
1413 BIND T99_E2 = UPLIT(CONT_DRVR NTWK);
1414
1415 BIND T99_ES = PLIT( T99_E1,
1416 T99_E2);
1417
1418
1419 BIND T100_E1 = UPLIT(MSEC_EN NTWK);
1420 BIND T100_E2 = UPLIT(MSEC_EN NTWK);
1421
1422 BIND T100_ES = PLIT( T100_E1,
1423 T100_E2);
1424
1425
1426 BIND T101_E1 = UPLIT(STK_RESET NTWK);
1427
1428 BIND T101_ES = PLIT( T101_E1);
1429
1430
1431 BIND T102_E1 = UPLIT(CLK_ENBS ENB RD_DATA READ_DLY RD_DLY NTWK);
1432 BIND T102_E2 = UPLIT(CLK_ENBS ENB RD_DATA READ_DLY RD_DLY NTWK);
1433
1434 BIND T102_ES = PLIT( T102_E1,
1435 T102_E2);
1436 GLOBAL BIND ES_TBL = UPLIT( T1_ES,
1437 T2_ES,
1438 T3_ES,
1439 T4_ES,
1440 T5_ES,
1441 T6_ES,
1442 T7_ES,
1443 T8_ES,
1444 T9_ES,
1445 T10_ES,
1446 T11_ES,
1447 T12_ES,
1448 T13_ES,
1449 T14_ES,
1450 T15_ES,
1451 T16_ES,
1452 T17_ES,
1453 T18_ES,
1454 T19_ES,
1455 T20_ES,
1456 T21_ES,
1457 T22_ES,
1458 T23_ES,
1459 T24_ES,
1460 T25_ES,
1461 T26_ES,
1462 T27_ES,
1463 T28_ES,
1464 T29_ES,
1465 T30_ES,
1466 T31_ES,
1467 T32_ES,
1468 T33_ES,
1469 T34_ES,
1470 T35_ES,
1471 T36_ES,
1472 T37_ES,
1473 T38_ES,
1474 T39_ES,
1475 T40_ES,
1476 T41_ES,
1477 T42_ES,
1478 T43_ES,
1479 T44_ES,
1480 T45_ES,
1481 T46_ES,
1482 T47_ES,
1483 T48_ES,
1484 T49_ES,
1485 T50_ES,
1486 T51_ES,
1487 T52_ES,
1488 T53_ES,
1489 T54_ES,
1490 T55_ES,
1491 T56_ES,
1492 T57_ES,
1493 T58_ES,
1494 T59_ES,
1495 T60_ES,
1496 T61_ES,
1497 T62_ES,
1498 T63_ES,
1499 T64_ES,
1500 T65_ES,
1501 T66_ES,
1502 T67_ES,
1503 T68_ES,
1504 T69_ES,
1505 T70_ES,
1506 T71_ES,
1507 T72_ES,
1508 T73_ES,
1509 T74_ES,
1510 T75_ES,
1511 T76_ES,
1512 T77_ES,
1513 T78_ES,
1514 T79_ES,
1515 T80_ES,
1516 T81_ES,
1517 T82_ES,
1518 T83_ES,
1519 T84_ES,
1520 T85_ES,
1521 T86_ES,
1522 T87_ES,
1523 T88_ES,
1524 T89_ES,
1525 T90_ES,
1526 T91_ES,
1527 T92_ES,
1528 T93_ES,
1529 T94_ES,
1530 T95_ES,
1531 T96_ES,
1532 T97_ES,
1533 T98_ES,
1534 T99_ES,
1535 T100_ES,
1536 T101_ES,
1537 T102_ES);
1538
1539 GLOBAL BIND NES_TBL = UPLIT( T1_NES,
1540 T2_NES,
1541 T3_NES,
1542 T4_NES,
1543 0,
1544 0,
1545 T7_NES,
1546 T8_NES,
1547 0,
1548 0,
1549 0,
1550 0,
1551 0,
1552 0,
1553 T15_NES,
1554 0,
1555 T17_NES,
1556 T18_NES,
1557 T19_NES,
1558 0,
1559 0,
1560 0,
1561 0,
1562 T24_NES,
1563 T25_NES,
1564 T26_NES,
1565 T27_NES,
1566 T28_NES,
1567 T29_NES,
1568 T30_NES,
1569 T31_NES,
1570 T32_NES,
1571 T33_NES,
1572 0,
1573 0,
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0,
1581 0,
1582 0,
1583 0,
1584 0,
1585 0,
1586 0,
1587 0,
1588 T50_NES,
1589 0,
1590 0,
1591 0,
1592 0,
1593 T55_NES,
1594 0,
1595 T57_NES,
1596 0,
1597 0,
1598 0,
1599 0,
1600 0,
1601 T63_NES,
1602 0,
1603 0,
1604 0,
1605 0,
1606 0,
1607 0,
1608 0,
1609 0,
1610 0,
1611 0,
1612 0,
1613 0,
1614 0,
1615 0,
1616 0,
1617 T79_NES,
1618 0,
1619 0,
1620 0,
1621 0,
1622 0,
1623 0,
1624 0,
1625 T87_NES,
1626 0,
1627 0,
1628 0,
1629 0,
1630 0,
1631 0,
1632 0,
1633 0,
1634 0,
1635 0,
1636 0,
1637 0,
1638 0,
1639 0,
1640 0);
1641
1642 EXTERNAL ROUTINE
1643 TST1,
1644 TST2,
1645 TST3,
1646 TST4,
1647 TST5,
1648 TST6,
1649 TST7,
1650 TST8,
1651 TST9,
1652 TST10,
1653 TST11,
1654 TST12,
1655 TST13,
1656 TST14,
1657 TST15,
1658 TST16,
1659 TST17,
1660 TST18,
1661 TST19,
1662 TST20,
1663 TST21,
1664 TST22,
1665 TST23,
1666 TST24,
1667 TST25,
1668 TST26,
1669 TST27,
1670 TST28,
1671 TST29,
1672 TST30,
1673 TST31,
1674 TST32,
1675 TST33,
1676 TST34,
1677 TST35,
1678 TST36,
1679 TST37,
1680 TST38,
1681 TST39,
1682 TST40,
1683 TST41,
1684 TST42,
1685 TST43,
1686 TST44,
1687 TST45,
1688 TST46,
1689 TST47,
1690 TST48,
1691 TST49,
1692 TST50,
1693 TST51,
1694 TST52,
1695 TST53,
1696 TST54,
1697 TST55,
1698 TST56,
1699 TST57,
1700 TST58,
1701 TST59,
1702 TST60,
1703 TST61,
1704 TST62,
1705 TST63,
1706 TST64,
1707 TST65,
1708 TST66,
1709 TST67,
1710 TST68,
1711 TST69,
1712 TST70,
1713 TST71,
1714 TST72,
1715 TST73,
1716 TST74,
1717 TST75,
1718 TST76,
1719 TST77,
1720 TST78,
1721 TST79,
1722 TST80,
1723 TST81,
1724 TST82,
1725 TST83,
1726 TST84,
1727 TST85,
1728 TST86,
1729 TST87,
1730 TST88,
1731 TST89,
1732 TST90,
1733 TST91,
1734 TST92,
1735 TST93,
1736 TST94,
1737 TST95,
1738 TST96,
1739 TST97,
1740 TST98,
1741 TST99,
1742 TST100,
1743 TST101,
1744 TST102;
1745
1746
1747 GLOBAL BIND TEST_DISP = PLIT( TST1,
1748 TST2,
1749 TST3,
1750 TST4,
1751 TST5,
1752 TST6,
1753 TST7,
1754 TST8,
1755 TST9,
1756 TST10,
1757 TST11,
1758 TST12,
1759 TST13,
1760 TST14,
1761 TST15,
1762 TST16,
1763 TST17,
1764 TST18,
1765 TST19,
1766 TST20,
1767 TST21,
1768 TST22,
1769 TST23,
1770 TST24,
1771 TST25,
1772 TST26,
1773 TST27,
1774 TST28,
1775 TST29,
1776 TST30,
1777 TST31,
1778 TST32,
1779 TST33,
1780 TST34,
1781 TST35,
1782 TST36,
1783 TST37,
1784 TST38,
1785 TST39,
1786 TST40,
1787 TST41,
1788 TST42,
1789 TST43,
1790 TST44,
1791 TST45,
1792 TST46,
1793 TST47,
1794 TST48,
1795 TST49,
1796 TST50,
1797 TST51,
1798 TST52,
1799 TST53,
1800 TST54,
1801 TST55,
1802 TST56,
1803 TST57,
1804 TST58,
1805 TST59,
1806 TST60,
1807 TST61,
1808 TST62,
1809 TST63,
1810 TST64,
1811 TST65,
1812 TST66,
1813 TST67,
1814 TST68,
1815 TST69,
1816 TST70,
1817 TST71,
1818 TST72,
1819 TST73,
1820 TST74,
1821 TST75,
1822 TST76,
1823 TST77,
1824 TST78,
1825 TST79,
1826 TST80,
1827 TST81,
1828 TST82,
1829 TST83,
1830 TST84,
1831 TST85,
1832 TST86,
1833 TST87,
1834 TST88,
1835 TST89,
1836 TST90,
1837 TST91,
1838 TST92,
1839 TST93,
1840 TST94,
1841 TST95,
1842 TST96,
1843 TST97,
1844 TST98,
1845 TST99,
1846 TST100,
1847 TST101,
1848 TST102);
1849 GLOBAL LITERAL MAXTEST = 102;
1850
1851 GLOBAL
1852 TESTS_FAILED: BITVECTOR[MAXTEST];
1853
1854 GLOBAL
1855 NET_FAULTS: BITVECTOR[MAXNETS];
1856
1857 END
1858 ELUDOM
ADR0L2_H 140 427 428 429 436 443 445 446
ADR0L2_L 139 416 417 418
ADR0L6_H 274 464 465 466 549 551 604 605 620 621 622
ADR0L6_L 273 532 533 534 550 551 603 605 622 643 647 678
680 709 713 744 746 775 779 810 812 841 845 876
878
ADR1L_H 142 416 417 418 533 534 550 551 604 621
ADR1L_L 141
ALLOC_B 58# 66 67# 69 78 412
ALLOC_N 60# 81 84 89 406 410 415
ALLOC_NAME 65 75#
ALLOC_N_1 61# 84 85
ALLOC_SLIT 65 82 87
ALLOC_W 59# 70 72 76 77 395 411
ALLOC_W_1 62# 395 396 397
ALLOC 65# 125 126 127 128 129 130 131 132 133 134 135
139 140 141 142 146 147 148 149 150 151 152 153
154 155 156 157 158 159 160 161 162 163 164 165
166 167 168 169 170 171 172 173 174 175 176 177
178 179 180 181 185 186 187 188 189 190 191 192
193 194 195 196 197 198 199 200 201 202 203 204
205 206 207 208 209 210 211 212 213 214 215 216
217 218 219 220 221 222 223 224 225 226 227 228
229 230 231 232 233 234 235 236 237 238 242 243
244 245 246 247 248 249 250 251 252 253 254 255
256 257 258 259 260 261 262 263 264 265 269 270
271 272 273 274 275 276 277 278 279 280 281 282
283 284 285 289 290 291 292 296 297 298 299 300
301 302 303 307 308 309 310 311 312 316 317 318
319 320 321 322 323 324 325 326 327 328 329 330
331 332 333 334 335 336 337 338 339 340 341 342
343 344 345 346 347 348 349 350 351 352 353 354
355 356 357 358 359 360 361 362 363 364 365 366
367 368 369 370 371 372 373 374 375 376 377 378
379 380 381 382 383 384 385 386 387 388 389 390
BLISS36 4
BUS0_3 296 599 600 601 602 603 604 616 617 618 619 620
621
BUS12_15 291 708 710 741 743
BUS16_19 292 709 711 742 744
BUS20_23 269 774 776 807 809
BUS24_27 270 775 777 808 810
BUS28_31 271 840 842 873 875
BUS32_35 272 841 843 874 876
BUS4_7 289 642 644 675 677
BUS8_11 290 643 645 676 678
BUSREQ 322 427 428 429 436 465
BUS_ARB 135 427 436
BUS_REQ 209 427 428 429 436
CACHE_EN 147
CLK_ENBS 254 512 513 514 523 1166 1167 1168 1169 1177 1182 1431
1432
CLK_RUN 251 514 523 1166 1167 1169 1177 1182
CMD_LD 223 1040 1049 1059 1069
CMD_XCVR 297 528 529 530 531 532 533 545 546 547 548 549
550
CONS_REQ 210 454
CONT 329 1076 1079 1082
CONT_DRVR 221 1412 1413
CONT_H 220 1076 1079 1097 1106 1115 1124
CPU_PE 152 1214 1219 1224 1229 1235 1236 1246 1247 1259
CRAM_CLK 249 1040 1059
CRA_PE 378 1234 1260
CRA_PE_LTCH 148 1234 1260
CRA_R_CLK 228 986 991
CRM_ADR_LD 199 1028 1029
CRM_DET 158 1229 1235 1236 1246 1247 1259
CRM_PE 339 1245
CRM_PE_LTCH 149 1245
CRM_RESET 195 1018
CRM_WRT 198 1001 1002 1023
CR_CLK_ENB 325 512 523
CSLBUF0 275 529 546 599 616
CSLBUF1 276 514 515 530 547 600 617
CSLBUF2 277 528 545 601 618
CSLBUF3 278 531 548 602 619
CSLBUF4 279
CSLBUF5 280 1001
C_LTCH1 234 464 465 466 492 497 502
C_LTCHS 207 464 465 466 492 497 502
C_R_C_E 204 986 991
C_T_C_E 205 986 996
DATAACK 332 562 564 565 573 580 587 594
DATA_ACK 227 562 564 565 573 580 587 594
DATA_CYC 237 532 549 603 620 641 674 707 740 773 806 839
872
DATA_EDIT 52#
DATA_ENB 224 487 562 563 564 573 574 580 581 587 588 594
DATA_VERSION 51#
DFN_0 185 1001 1002
DFN_1 186 1008 1028 1029
DFN_11 193 986
DFN_2 187 1013
DFN_3 188
DFN_4 189 1008
DFN_5 190 1013
DFN_6 191
DFN_7 192
DP_CLK_ENB 326 513
DP_PAR_ERR 154 1219 1291
DP_PE_DET 159
DP_PE_LTCH 150 1291
DP_PE 363 1291
DP_RESET 196 1316
DUMP 91# 95 396 406
DUMP_ASSIGN 97# 100 397
ENABLE_PE 257 1266
ENB 256 514 523 1166 1167 1168 1169 1177 1182 1389 1390 1391
1431 1432
ENB_RES 265
ES_TBL 1436#
EXEC 327 1075 1078 1081
EXEC_B 216 1075 1078 1096 1105 1114 1123
EXEC_DRVR 217 1405 1406
GRANT_1 232 427 436 443 487 497
GRANT 214 427 436 465
HALT_LOOP 331 1040 1041 1042
HLT_LP 215 1040 1041 1049 1054 1059 1064 1069
INT_10 222 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358
1359 1360 1361 1379 1384
LANGUAGE 4
LTCH_DATA 206 487 492
LTCH_DATA_ENB 226 465 487 492 497 502
MAXNETS 415# 1855
MAXTEST 1849# 1852
MEM 163 443
MEMBUSY 369
MEMH 164 459 562 565
MEM_BUSY 303 443 1343
MEM_PAR_ERR 355 1299
MEM_REF_ERR 389
MNT_CLK 283 474 475
MNT_ENBH 121 282
MNT_ENBL 281 473 474 475
MSCSLD 3#
MSEC_EN 212 1419 1420
MSTRCLK 119 120 121#
MSTR_CLK 121 125
N 91 92 95 97 98 100
NES_TBL 1539#
NET_FAULTS 1855
NET_NAMES 404#
NEXM 320 443 445 446
NEXM_LTCH 162 443 445
NTWK 394# 416 417 418 419 427 428 429 436 437 443 444
445 446 454 459 464 465 466 473 474 475 482 487
492 497 502 507 512 513 514 515 523 528 529 530
531 532 533 534 545 546 547 548 549 550 551 562
563 564 565 573 574 580 581 587 588 594 599 600
601 602 603 604 605 616 617 618 619 620 621 622
633 634 635 636 637 638 639 640 641 642 643 644
645 646 647 666 667 668 669 670 671 672 673 674
675 676 677 678 679 680 699 700 701 702 703 704
705 706 707 708 709 710 711 712 713 732 733 734
735 736 737 738 739 740 741 742 743 744 745 746
765 766 767 768 769 770 771 772 773 774 775 776
777 778 779 798 799 800 801 802 803 804 805 806
807 808 809 810 811 812 831 832 833 834 835 836
837 838 839 840 841 842 843 844 845 864 865 866
867 868 869 870 871 872 873 874 875 876 877 878
897 898 899 900 908 909 910 911 919 920 921 922
930 931 932 933 941 946 951 956 961 966 971 976
981 986 991 996 1001 1002 1008 1013 1018 1023 1028 1029
1035 1040 1041 1042 1049 1054 1059 1064 1069 1074 1075 1076
1077 1078 1079 1080 1081 1082 1095 1096 1097 1104 1105 1106
1113 1114 1115 1122 1123 1124 1131 1132 1133 1134 1135 1136
1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1166 1167
1168 1169 1177 1182 1187 1188 1189 1190 1198 1199 1205 1206
1207 1214 1219 1224 1229 1234 1235 1236 1237 1245 1246 1247
1254 1259 1260 1266 1271 1272 1273 1274 1275 1276 1277 1278
1290 1291 1292 1299 1300 1306 1307 1308 1315 1316 1322 1323
1329 1330 1336 1337 1343 1348 1349 1350 1351 1352 1353 1354
1355 1356 1357 1358 1359 1360 1361 1379 1384 1389 1390 1391
1398 1399 1405 1406 1412 1413 1419 1420 1426 1431 1432
N_ 81 85 406
PDLY1 127
PDLY2 128
PDLY3 119 129
PDLY4 130
PDLY5 120 131
PE 330 419 1214 1219 1224 1229 1235 1236 1237
PE_DET 156 1235 1246 1254 1259 1260
PE_LTCH 155 419 1214 1219 1224 1229 1234 1235 1236 1245 1246 1247
1254 1259 1260 1300
PF 258
PF_1 253 513 1167 1389 1390 1391
PF_ST_1 252 1389 1390 1391
PIREQ 106 107 108 109 110 111 112 390
PIREQ1 106 335
PIREQ2 107 334
PIREQ3 108 370
PIREQ4 109 338
PIREQ5 110 354
PIREQ6 111 362
PIREQ7 112 377
PI_REQ1 106# 1348 1355 1379 1384
PI_REQ2 107# 1349 1356
PI_REQ3 108# 1350 1357
PI_REQ4 109# 1351 1358
PI_REQ5 110# 1352 1359
PI_REQ6 111# 1353 1360
PI_REQ7 112# 1354 1361
PNL_RST 243 417 418
RAM_ERROR 323 1292
RAM_ER_DLY 160 1219 1292
RAM_ER_LTCH 161 1292
RCLKD 117# 416 417 418 443
RCLKH 118# 436 437
RCLK_CSL 113 114 117 118 120#
RCLK_ENB0 324 464 465 466
RCV_PAR_LFT 302
RCV_PAR_RT 285
RDATA_00 352 602 619
RDATA_01 360 601 618
RDATA_02 375 600 617
RDATA_03 387 599 616
RDATA_04 348 640 673
RDATA_05 340 639 672
RDATA_06 371 638 671
RDATA_07 344 637 670
RDATA_08 356 636 669
RDATA_09 383 635 668
RDATA_10 379 634 667
RDATA_11 364 633 666
RDATA_12 349 706 739
RDATA_13 341 705 738
RDATA_14 372 704 737
RDATA_15 345 703 736
RDATA_16 357 702 735
RDATA_17 384 701 734
RDATA_18 380 700 733
RDATA_19 365 699 732
RDATA_20 350 772 805
RDATA_21 342 771 804
RDATA_22 373 770 803
RDATA_23 346 769 802
RDATA_24 358 768 801
RDATA_25 385 767 800
RDATA_26 381 766 799
RDATA_27 366 765 798
RDATA_28 351 838 871
RDATA_29 343 837 870
RDATA_30 374 836 869
RDATA_31 347 835 868
RDATA_32 359 834 867
RDATA_33 386 833 866
RDATA_34 382 832 865
RDATA_35 367 831 864
RD_0 165 562 564 565 573 604 605 621 622 646 647 679
680 712 713 745 746 778 779 811 812 844 845 877
878
RD_100 166 416 417 418 533 534 550 551
RD_300 167 427 428 429 436 443 445 446
RD_302 168 464 465 466
RD_DATA 260 1431 1432
RD_DLY 261 1166 1167 1169 1431 1432
READ_DLY 262 1166 1167 1169 1431 1432
RECEIVE_PE 336 1290
REC_BUS_PE 153 1214 1219 1224 1229 1236 1247
REC_PE 146 1271 1272 1273 1274 1275 1276 1277 1278 1290
REC_PE_LTCH 151 1290
REG204 201 1035
REG210 208 482
REQ_CTL 211 436
RESETB_H 247 482
RESETB_L 246 427 429
RESETH 248 416 417 418
RESETL_H 245
RESETL_L 244 443 444
RPAR_LEFT 337 1132 1134 1136 1138 1140 1142 1144 1146
RPAR_RIGHT 368 1131 1133 1135 1137 1139 1141 1143 1145
RST1 242 417 418
RST_LTCH 157 416 417 418
RST_XCVR 298 416 417 418
RTN_DATA 225 487 562 563 573 574 580 581 587 588
RUN 328 1074 1077 1080
RUN_1 218 1074 1077 1095 1104 1113 1122
RUN_DRVR 219
R_BADATA 353 531 548
R_CLK_A 307 711 713 744 746 778 779 811 812 844 845 877
878
R_CLK_B 308 604 605 621 622 646 647 679 680 710 713 743
746
R_CLK_CSL 120 134
R_CLK_D 117 311
R_CLK_E 113 114 117 312
R_CLK_ENB 229 464 465 487 492 497 502 507
R_CLK_H 118 309
R_CLK_L 310 562 563 565 573 574
R_CLK 133 514 515 1166 1167 1168 1169
R_COMADR 361 530 547
R_DATA 388 528 545
R_IODATA 376 529 546
R_PAR_LFT 300 1132 1134 1136 1138 1140 1142 1144 1146
R_PAR_RT 299 1131 1133 1135 1137 1139 1141 1143 1145
R_RESET 333 416 417 418
SHFT_LOGIC 255 1322 1323 1329 1330 1336 1337
SING_CLK 250 514 515 523 1168 1177 1182
SS_MODE 200
STAT_RD 231 532 603 641 707 773 839 941 946 951 956 961
966 971 976 981
STK_RESET 197 1426
T100_E1 1419# 1422
T100_E2 1420# 1423
T100_ES 1422# 1535
T101_E1 1426# 1428
T101_ES 1428# 1536
T102_E1 1431# 1434
T102_E2 1432# 1435
T102_ES 1434# 1537
T10_ES 489# 1445
T10_E1 487# 489
T11_ES 494# 1446
T11_E1 492# 494
T12_ES 499# 1447
T12_E1 497# 499
T13_ES 504# 1448
T13_E1 502# 504
T14_ES 509# 1449
T14_E1 507# 509
T15_ES 517# 1450
T15_E1 512# 517
T15_E2 513# 518
T15_E3 514# 519
T15_NE1 515# 520
T15_NES 520# 1553
T16_ES 525# 1451
T16_E1 523# 525
T17_ES 536# 1452
T17_E1 528# 536
T17_E2 529# 537
T17_E3 530# 538
T17_E4 531# 539
T17_E5 532# 540
T17_E6 533# 541
T17_NE1 534# 542
T17_NES 542# 1555
T18_ES 553# 1453
T18_E1 545# 553
T18_E2 546# 554
T18_E3 547# 555
T18_E4 548# 556
T18_E5 549# 557
T18_E6 550# 558
T18_NE1 551# 559
T18_NES 559# 1556
T19_ES 567# 1454
T19_E1 562# 567
T19_E2 563# 568
T19_E3 564# 569
T19_NE1 565# 570
T19_NES 570# 1557
T1_E1 416# 421
T1_E2 417# 422
T1_E3 419# 423
T1_ES 421# 1436
T1_NES 424# 1539
T1_NE1 418# 424
T20_ES 576# 1455
T20_E1 573# 576
T20_E2 574# 577
T21_ES 583# 1456
T21_E1 580# 583
T21_E2 581# 584
T22_ES 590# 1457
T22_E1 587# 590
T22_E2 588# 591
T23_ES 596# 1458
T23_E1 594# 596
T24_ES 607# 1459
T24_E1 599# 607
T24_E2 600# 608
T24_E3 601# 609
T24_E4 602# 610
T24_E5 603# 611
T24_E6 604# 612
T24_NE1 605# 613
T24_NES 613# 1562
T25_ES 624# 1460
T25_E1 616# 624
T25_E2 617# 625
T25_E3 618# 626
T25_E4 619# 627
T25_E5 620# 628
T25_E6 621# 629
T25_NE1 622# 630
T25_NES 630# 1563
T26_ES 649# 1461
T26_E1 633# 649
T26_E10 642# 658
T26_E11 643# 659
T26_E12 644# 660
T26_E13 645# 661
T26_E14 646# 662
T26_E2 634# 650
T26_E3 635# 651
T26_E4 636# 652
T26_E5 637# 653
T26_E6 638# 654
T26_E7 639# 655
T26_E8 640# 656
T26_E9 641# 657
T26_NE1 647# 663
T26_NES 663# 1564
T27_ES 682# 1462
T27_E1 666# 682
T27_E10 675# 691
T27_E11 676# 692
T27_E12 677# 693
T27_E13 678# 694
T27_E14 679# 695
T27_E2 667# 683
T27_E3 668# 684
T27_E4 669# 685
T27_E5 670# 686
T27_E6 671# 687
T27_E7 672# 688
T27_E8 673# 689
T27_E9 674# 690
T27_NE1 680# 696
T27_NES 696# 1565
T28_ES 715# 1463
T28_E1 699# 715
T28_E10 708# 724
T28_E11 709# 725
T28_E12 710# 726
T28_E13 711# 727
T28_E14 712# 728
T28_E2 700# 716
T28_E3 701# 717
T28_E4 702# 718
T28_E5 703# 719
T28_E6 704# 720
T28_E7 705# 721
T28_E8 706# 722
T28_E9 707# 723
T28_NE1 713# 729
T28_NES 729# 1566
T29_ES 748# 1464
T29_E1 732# 748
T29_E10 741# 757
T29_E11 742# 758
T29_E12 743# 759
T29_E13 744# 760
T29_E14 745# 761
T29_E2 733# 749
T29_E3 734# 750
T29_E4 735# 751
T29_E5 736# 752
T29_E6 737# 753
T29_E7 738# 754
T29_E8 739# 755
T29_E9 740# 756
T29_NE1 746# 762
T29_NES 762# 1567
T2_E1 427# 431
T2_E2 428# 432
T2_ES 431# 1437
T2_NES 433# 1540
T2_NE1 429# 433
T30_ES 781# 1465
T30_E1 765# 781
T30_E10 774# 790
T30_E11 775# 791
T30_E12 776# 792
T30_E13 777# 793
T30_E14 778# 794
T30_E2 766# 782
T30_E3 767# 783
T30_E4 768# 784
T30_E5 769# 785
T30_E6 770# 786
T30_E7 771# 787
T30_E8 772# 788
T30_E9 773# 789
T30_NE1 779# 795
T30_NES 795# 1568
T31_ES 814# 1466
T31_E1 798# 814
T31_E10 807# 823
T31_E11 808# 824
T31_E12 809# 825
T31_E13 810# 826
T31_E14 811# 827
T31_E2 799# 815
T31_E3 800# 816
T31_E4 801# 817
T31_E5 802# 818
T31_E6 803# 819
T31_E7 804# 820
T31_E8 805# 821
T31_E9 806# 822
T31_NE1 812# 828
T31_NES 828# 1569
T32_ES 847# 1467
T32_E1 831# 847
T32_E10 840# 856
T32_E11 841# 857
T32_E12 842# 858
T32_E13 843# 859
T32_E14 844# 860
T32_E2 832# 848
T32_E3 833# 849
T32_E4 834# 850
T32_E5 835# 851
T32_E6 836# 852
T32_E7 837# 853
T32_E8 838# 854
T32_E9 839# 855
T32_NE1 845# 861
T32_NES 861# 1570
T33_ES 880# 1468
T33_E1 864# 880
T33_E10 873# 889
T33_E11 874# 890
T33_E12 875# 891
T33_E13 876# 892
T33_E14 877# 893
T33_E2 865# 881
T33_E3 866# 882
T33_E4 867# 883
T33_E5 868# 884
T33_E6 869# 885
T33_E7 870# 886
T33_E8 871# 887
T33_E9 872# 888
T33_NE1 878# 894
T33_NES 894# 1571
T34_ES 902# 1469
T34_E1 897# 902
T34_E2 898# 903
T34_E3 899# 904
T34_E4 900# 905
T35_ES 913# 1470
T35_E1 908# 913
T35_E2 909# 914
T35_E3 910# 915
T35_E4 911# 916
T36_ES 924# 1471
T36_E1 919# 924
T36_E2 920# 925
T36_E3 921# 926
T36_E4 922# 927
T37_ES 935# 1472
T37_E1 930# 935
T37_E2 931# 936
T37_E3 932# 937
T37_E4 933# 938
T38_ES 943# 1473
T38_E1 941# 943
T39_ES 948# 1474
T39_E1 946# 948
T3_E1 436# 439
T3_ES 439# 1438
T3_NES 440# 1541
T3_NE1 437# 440
T40_ES 953# 1475
T40_E1 951# 953
T41_ES 958# 1476
T41_E1 956# 958
T42_ES 963# 1477
T42_E1 961# 963
T43_ES 968# 1478
T43_E1 966# 968
T44_ES 973# 1479
T44_E1 971# 973
T45_ES 978# 1480
T45_E1 976# 978
T46_ES 983# 1481
T46_E1 981# 983
T47_ES 988# 1482
T47_E1 986# 988
T48_ES 993# 1483
T48_E1 991# 993
T49_ES 998# 1484
T49_E1 996# 998
T4_E1 443# 448
T4_E2 445# 449
T4_ES 448# 1439
T4_NES 450# 1542
T4_NE1 444# 450
T4_NE2 446# 451
T50_ES 1004# 1485
T50_E1 1001# 1004
T50_NE1 1002# 1005
T50_NES 1005# 1588
T51_ES 1010# 1486
T51_E1 1008# 1010
T52_ES 1015# 1487
T52_E1 1013# 1015
T53_ES 1020# 1488
T53_E1 1018# 1020
T54_ES 1025# 1489
T54_E1 1023# 1025
T55_ES 1031# 1490
T55_E1 1028# 1031
T55_NE1 1029# 1032
T55_NES 1032# 1593
T56_ES 1037# 1491
T56_E1 1035# 1037
T57_ES 1044# 1492
T57_E1 1040# 1044
T57_E2 1041# 1045
T57_NE1 1042# 1046
T57_NES 1046# 1595
T58_ES 1051# 1493
T58_E1 1049# 1051
T59_ES 1056# 1494
T59_E1 1054# 1056
T5_E1 454# 456
T5_ES 456# 1440
T60_ES 1061# 1495
T60_E1 1059# 1061
T61_ES 1066# 1496
T61_E1 1064# 1066
T62_ES 1071# 1497
T62_E1 1069# 1071
T63_ES 1084# 1498
T63_E1 1074# 1084
T63_E2 1075# 1085
T63_E3 1076# 1086
T63_E4 1077# 1087
T63_E5 1078# 1088
T63_E6 1079# 1089
T63_NE1 1080# 1090
T63_NE2 1081# 1091
T63_NE3 1082# 1092
T63_NES 1090# 1601
T64_ES 1099# 1499
T64_E1 1095# 1099
T64_E2 1096# 1100
T64_E3 1097# 1101
T65_ES 1108# 1500
T65_E1 1104# 1108
T65_E2 1105# 1109
T65_E3 1106# 1110
T66_ES 1117# 1501
T66_E1 1113# 1117
T66_E2 1114# 1118
T66_E3 1115# 1119
T67_ES 1126# 1502
T67_E1 1122# 1126
T67_E2 1123# 1127
T67_E3 1124# 1128
T68_ES 1148# 1503
T68_E1 1131# 1148
T68_E10 1140# 1157
T68_E11 1141# 1158
T68_E12 1142# 1159
T68_E13 1143# 1160
T68_E14 1144# 1161
T68_E15 1145# 1162
T68_E16 1146# 1163
T68_E2 1132# 1149
T68_E3 1133# 1150
T68_E4 1134# 1151
T68_E5 1135# 1152
T68_E6 1136# 1153
T68_E7 1137# 1154
T68_E8 1138# 1155
T68_E9 1139# 1156
T69_ES 1171# 1504
T69_E1 1166# 1171
T69_E2 1167# 1172
T69_E3 1168# 1173
T69_E4 1169# 1174
T6_E1 459# 461
T6_ES 461# 1441
T70_ES 1179# 1505
T70_E1 1177# 1179
T71_ES 1184# 1506
T71_E1 1182# 1184
T72_ES 1192# 1507
T72_E1 1187# 1192
T72_E2 1188# 1193
T72_E3 1189# 1194
T72_E4 1190# 1195
T73_ES 1201# 1508
T73_E1 1198# 1201
T73_E2 1199# 1202
T74_ES 1209# 1509
T74_E1 1205# 1209
T74_E2 1206# 1210
T74_E3 1207# 1211
T75_ES 1216# 1510
T75_E1 1214# 1216
T76_ES 1221# 1511
T76_E1 1219# 1221
T77_ES 1226# 1512
T77_E1 1224# 1226
T78_ES 1231# 1513
T78_E1 1229# 1231
T79_ES 1239# 1514
T79_E1 1234# 1239
T79_E2 1235# 1240
T79_E3 1236# 1241
T79_NE1 1237# 1242
T79_NES 1242# 1617
T7_E1 464# 468
T7_E2 465# 469
T7_ES 468# 1442
T7_NES 470# 1545
T7_NE1 466# 470
T80_ES 1249# 1515
T80_E1 1245# 1249
T80_E2 1246# 1250
T80_E3 1247# 1251
T81_ES 1256# 1516
T81_E1 1254# 1256
T82_ES 1262# 1517
T82_E1 1259# 1262
T82_E2 1260# 1263
T83_ES 1268# 1518
T83_E1 1266# 1268
T84_ES 1280# 1519
T84_E1 1271# 1280
T84_E2 1272# 1281
T84_E3 1273# 1282
T84_E4 1274# 1283
T84_E5 1275# 1284
T84_E6 1276# 1285
T84_E7 1277# 1286
T84_E8 1278# 1287
T85_ES 1294# 1520
T85_E1 1290# 1294
T85_E2 1291# 1295
T85_E3 1292# 1296
T86_ES 1302# 1521
T86_E1 1299# 1302
T86_E2 1300# 1303
T87_ES 1310# 1522
T87_E1 1306# 1310
T87_E2 1307# 1311
T87_NE1 1308# 1312
T87_NES 1312# 1625
T88_ES 1318# 1523
T88_E1 1315# 1318
T88_E2 1316# 1319
T89_ES 1325# 1524
T89_E1 1322# 1325
T89_E2 1323# 1326
T8_E1 473# 477
T8_E2 474# 478
T8_ES 477# 1443
T8_NES 479# 1546
T8_NE1 475# 479
T90_ES 1332# 1525
T90_E1 1329# 1332
T90_E2 1330# 1333
T91_ES 1339# 1526
T91_E1 1336# 1339
T91_E2 1337# 1340
T92_ES 1345# 1527
T92_E1 1343# 1345
T93_ES 1363# 1528
T93_E1 1348# 1363
T93_E10 1357# 1372
T93_E11 1358# 1373
T93_E12 1359# 1374
T93_E13 1360# 1375
T93_E14 1361# 1376
T93_E2 1349# 1364
T93_E3 1350# 1365
T93_E4 1351# 1366
T93_E5 1352# 1367
T93_E6 1353# 1368
T93_E7 1354# 1369
T93_E8 1355# 1370
T93_E9 1356# 1371
T94_ES 1381# 1529
T94_E1 1379# 1381
T95_ES 1386# 1530
T95_E1 1384# 1386
T96_ES 1393# 1531
T96_E1 1389# 1393
T96_E2 1390# 1394
T96_E3 1391# 1395
T97_ES 1401# 1532
T97_E1 1398# 1401
T97_E2 1399# 1402
T98_ES 1408# 1533
T98_E1 1405# 1408
T98_E3 1406# 1409
T99_ES 1415# 1534
T99_E1 1412# 1415
T99_E2 1413# 1416
T9_E1 482# 484
T9_ES 484# 1444
TCLKA 113# 416 417 418
TCLKB 114# 464 466
TCLKC 115# 436 437
TCLKD 116# 436 437 464 466
TCLK_CSL 113 114 115 116 119#
TEN_INT 321 1306 1307 1308
TEN_INT_LTCH 213 1306 1307 1315 1316
TESTS_FAILED 1852
TEST_DISP 1747#
TRAP_EN 194 1398 1399
TST1 1643* 1747
TST10 1652 1756
TST100 1742 1846
TST101 1743 1847
TST102 1744 1848
TST11 1653 1757
TST12 1654 1758
TST13 1655 1759
TST14 1656 1760
TST15 1657 1761
TST16 1658 1762
TST17 1659 1763
TST18 1660 1764
TST19 1661 1765
TST2 1644 1748
TST20 1662 1766
TST21 1663 1767
TST22 1664 1768
TST23 1665 1769
TST24 1666 1770
TST25 1667 1771
TST26 1668 1772
TST27 1669 1773
TST28 1670 1774
TST29 1671 1775
TST3 1645 1749
TST30 1672 1776
TST31 1673 1777
TST32 1674 1778
TST33 1675 1779
TST34 1676 1780
TST35 1677 1781
TST36 1678 1782
TST37 1679 1783
TST38 1680 1784
TST39 1681 1785
TST4 1646 1750
TST40 1682 1786
TST41 1683 1787
TST42 1684 1788
TST43 1685 1789
TST44 1686 1790
TST45 1687 1791
TST46 1688 1792
TST47 1689 1793
TST48 1690 1794
TST49 1691 1795
TST5 1647 1751
TST50 1692 1796
TST51 1693 1797
TST52 1694 1798
TST53 1695 1799
TST54 1696 1800
TST55 1697 1801
TST56 1698 1802
TST57 1699 1803
TST58 1700 1804
TST59 1701 1805
TST6 1648 1752
TST60 1702 1806
TST61 1703 1807
TST62 1704 1808
TST63 1705 1809
TST64 1706 1810
TST65 1707 1811
TST66 1708 1812
TST67 1709 1813
TST68 1710 1814
TST69 1711 1815
TST7 1649 1753
TST70 1712 1816
TST71 1713 1817
TST72 1714 1818
TST73 1715 1819
TST74 1716 1820
TST75 1717 1821
TST76 1718 1822
TST77 1719 1823
TST78 1720 1824
TST79 1721 1825
TST8 1650 1754
TST80 1722 1826
TST81 1723 1827
TST82 1724 1828
TST83 1725 1829
TST84 1726 1830
TST85 1727 1831
TST86 1728 1832
TST87 1729 1833
TST88 1730 1834
TST89 1731 1835
TST9 1651 1755
TST90 1732 1836
TST91 1733 1837
TST92 1734 1838
TST93 1735 1839
TST94 1736 1840
TST95 1737 1841
TST96 1738 1842
TST97 1739 1843
TST98 1740 1844
TST99 1741 1845
T_CLK_A 113 316
T_CLK_B 114 317 487 492 497 502
T_CLK_C 115 318
T_CLK_CSL 119 132
T_CLK_D 116 319
T_CLK_EN 230 986 996
T_CLK 126 514 515
T_CNT_DN 263 1166 1167 1169
T_COUNT_DONE 264 1187 1188 1189 1190 1198 1199 1205 1206 1207
T_ENB_A 236 711 744 778 811 844 877
T_ENB 235 533 550 604 621 646 679 710 743
WRT100 169 416 418
WRT102 170 844 845 877 878
WRT104 171 778 779 811 812
WRT106 172 712 713 745 746
WRT110 173 646 647 679 680
WRT112 174 604 605 621 622
WRT114 175 443 445 533 550
WRT116 176 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358
1359 1360 1361
WRT204 177 1001 1002 1018
WRT205 178
WRT206 179 514 515
WRT210 180 427 428 429 443
WRT212 181 1074 1075 1076 1080 1081 1082
WRT_DLY 259 1166 1167 1169
W_ 72 76 77 99 396
X 91 94 95
XMIT_ADR 203 533 604 646
XMIT_DATA 202 532 550 603 621 641 679 707 773 839
XMIT_ENBS 238 897 898 899 900 908 909 910 911 919 920 921
922 930 931 932 933
XMIT_PAR_LFT 301 1132 1134 1136 1138 1140 1142 1144 1146
XMIT_PAR_RT 284 1131 1133 1135 1137 1139 1141 1143 1145
X_D1 233 532 603 621 641 679 707 773 839
TIME: 6 SEC.
CORE: 17K