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klad.sources/mcod4t.mac
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XLIST
EDIT=0
VERSION=1
DEFINE NAME (EDT,VER),<
LALL
LIST
TITLE MCODE4 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 1 VERSION EDT'.'VER
>
NAME \EDIT,\VERSION
COMMENT $
MCODE4 IS THE 1ST PART OF A 4 PART MICRODIAGNOSTIC OF THE HIGH SPEED
DATA PATH. IT IS MAINLY A LOGIC TEST (AS OPPOSED TO A FUNCTIONAL TEST)
WHICH DOES THE FOLLOWING:
(1) TESTS THE READING AND WRITING OF THE CONTROL AND STATUS REGISTERS.
(2) VERIFIES THE DATA FORMATTER CONTROL ROM CONTENTS.
(3) TESTS THE HANDSHAKING LOGIC BETWEEN THE DATA PATH AND THE
MASSBUS AND CHANNEL BUS INTERFACES.
(4) TESTS THE MAJORITY OF THE DATA FORMATTER CONTROL LOGIC.
THE TESTS ARE INDEPENDENT OF THE MASSBUS AND CHANNEL BUS INTERFACES,
EXCEPT FOR THE "FMTR END XFER", "RUN DATA", AND "MSTR END XFER" TESTS,
WHICH REQUIRE THE GENERATION OF "SLVE WOR END XFER" ON THE CB BOARD.
ALL TESTS WHICH INVOLVE THE BASE CLOCK OR THE CLOCK PHASES ARE EXECUTED
IN SINGLE STEPPING MODE TO ALLOW EXAMINATION OF SIGNAL STATES DURING THE TEST.
NOTE: ALL DOCUMENTATION USES THE TERM "SET" TO DENOTE THE ASSERTION OF A
SIGNAL AND "CLEAR" TO DENOTE ITS NEGATION, WHETHER OR NOT THE SIGNAL
IS ASSERTED HIGH OR LOW.
$
RPTCNT= 100 ;SET REPEAT COUNT TO 100 TIMES
SUBTTL DATA PATH BIT REGISTER DEFINITIONS
;DEFINE THE DATA PATH REGISTERS
REG0=0 ;REGISTER 0 (READ ONLY)
REG1=1
REG2=2
REG3=3 ;READ ONLY
MCLO=4 ;MASSBUS COUNTER BITS 7-0
MCHI=5 ;MASSBUSS COUNTER BITS 15-8
BCLO=6 ;BYTE COUNTER BITS 7-0
BCHI=7 ;BYTE COUNTER BITS 15-8
DFRMAD=10 ;DF ROM ADDRESS BITS 7-0
RMDALO=11 ;DF ROM DATA BITS 7-0 (READ ONLY)
RMDAHI=12 ;DF ROM DATA BITS 15-8 (READ ONLY)
ARLO=13 ;ASSEMBLY REGISTER BITS 7-0
ARHI=14 ;ASSEMBLY REGISTER BITS 15-8
REG15=15 ;READ ONLY
REG16=16 ;READ ONLY
REG17=17 ;READ ONLY
LDRMDA=11 ;LOAD ROM DATA PULSE (WRITE ONLY)
CLKPLS=12 ;BASE CLOCK PULSE (WRITE ONLY)
HSDPIN=13 ;HS DP INIT PULSE (WRITE ONLY)
SETRUN=14 ;SET RUN PULSE (WRITE ONLY)
;REGISTER 0
UBPEFG=1B35 ;MICROBUS PARITY ERROR FLAG
DPPEFG=1B34 ;DATA PATH PARITY ERROR FLAG
BCOVF=1B33 ;BYTE COUNT OVERFLOW FLAG
MCOVF=1B32 ;MASSBUS COUNTER OVERFLOW FLAG
;REGISTER 1
DXHISP=1B35 ;DX HIGH SPEED
BCLKEN=1B34 ;BASE CLOCK ENABLE
DSLVRQ=1B33 ;DIAGNOSTIC SLAVE REQUEST
DMSTRQ=1B32 ;DIAGNOSTIC MASTER REQUEST
SLVACK=1B31 ;SLAVE ACK
MSTACK=1B30 ;MASTER ACK
SLVRQ=1B29 ;SLAVE REQUEST
MSTRQ=1B28 ;MASTER REQUEST
;REGISTER 2
RMADR8=1B35 ;ROM ADDR BIT 8
SEBCOV=1B34 ;SLVE END ON BC OVFL EN
MEMCOV=1B33 ;MSTR END ON MC OVFL EN
MEONFE=1B32 ;MSTR END ON FMTR END EN
SRHDOF=1B29 ;SLVE REQ HLDOFF
MRHDOF=1B28 ;MASTER REQ HLDOFF
;REGISTER 3
NSEXFR=1B34 ;NOT SLVE END XFER
NMEXFR=1B33 ;NOT MSTR END XFER
NFEXFR=1B32 ;NOT FMTR END XFER
;REGISTER 4 (MASSBUS COUNTER 7-0 - MCLO)
MCLOBT=377B35 ;BITS 7-0 OF MASSBUS COUNTER
;REGISTER 5 (MASSBUS COUNTER 15-8 - MCHI)
MCHIBT=377B35 ;BITS 15-8 OF MASSBUS COUNTER
;REGISTER 6 (BYTE COUNTER 7-0 - BCLO)
BCLOBT=377B35 ;BITS 7-0 OF BYTE COUNTER
;REGISTER 7 (BYTE COUNTER 15-8 - BCHI)
BCHIBT=377B35 ;BITS 15-8 OF BYTE COUNTER
;REGISTER 10 (DF ROM ADR 7-0 - DFRMAD)
RMADLO=377B35 ;BITS 7-0 OF DF ROM ADDRESS
;REGISTER 11 (DF ROM DATA 7-0 - RMDALO)
RDLOBT=377B35 ;BITS 7-0 OF DF ROM DATA
;REGISTER 12 (DF ROM DATA 15-8 - RMDAHI)
RDLOBT=377B35 ;BITS 15-8 OF DF ROM DATA
;REGISTER 13 (ASSEMBLY REGISTER 7-0 - ARLO)
ARLOBT=377B35 ;BITS 7-0 OF ASSEMBLY REGISTER
;REGISTER 14 (ASSEMBLY REGISTER 15-8 - ARHI)
ARHIBT=377B35 ;BITS 15-8 OF ASSEMBLY REGISTER
;REGISTER 15
AR1716=3B35 ;BITS 17-16 OF ASSEMBLY REGISTER
NCLRAR=1B33 ;NOT CLEAR ASSEMBLY REG
NENMDM=1B32 ;NOT ENABLE MUX/DEMUX
LDCB=1B31 ;LOAD CHANNEL BUFFER
LDSB=1B30 ;LOAD SILO BUFFER
EXTRUN=1B29 ;EXTEND RUN
;REGISTER 16
SLVEPE=1B35 ;SLVE PARITY ERROR
MSTRPE=1B34 ;MSTR PARITY ERROR
NCLRN=1B33 ;NOT CLR RUN
NOTRUN=1B32 ;NOT RUN
DFCPH0=1B31 ;DF CLK PH 0
DFCPH1=1B30 ;DF CLK PH 1
NRNDAT=1B29 ;NOT RUN DATA
;REGISTER 17
SLVRDY=1B35 ;SLAVE RDY
SLRDY1=1B34 ;SLAVE RDY DLY 1
SLRDY2=1B33 ;SLAVE RDY DLY 2
MSTRDY=1B32 ;MASTER RDY
MSRDY1=1B31 ;MASTER RDY DLY 1
MSRDY2=1B30 ;MASTER RDY DLY 2
;DEFINE SOME CHANNEL BUS INTERFACE REGISTERS WHICH ARE REFERENCED
CSR0=0
CSR1=1
TOR0=2
TOR1=3
DRLO=6
CBILO=7
BORLO=11
CLKDRL=6 ;WRITE TO REG 6 CLOCKS DRLO REG
SLAK25=4 ;WRITE TO REG 4 GENERATES "SLVE ACK DL25"
;DEFINE SOME CHANNEL BUS INTERFACE REGISTER BITS WHICH ARE USED
CHANL=1B35 ;CHANNEL MODE BIT
LOOPEN=1B33 ;LOOP ENABLE BIT
DISACK=1B32 ;DIAG SLVE ACK
EVPAR=1B30 ;EVEN PARITY FORCED
STAINL=1B35 ;STA IN LOOPED BACK
SRVINL=1B28 ;SRV IN LOOPED BACK
CLRFLG=1B34 ;CLEARS REG 0 FLAGS
;ROM ADDRESSES WITH DIAGNOSTIC DATA
ZERADR=340 ;ADDR OF 1ST ROM LOC AFTER OPERATIONAL PROGRAMS
DIAGAD=310 ;ADDR OF 1ST DIAG ROM LOC
DMXSHF=310
MUXSHF=314
ZEROS=320
ONES=321
CC0=322
CC1=MSK0
CC2=323
CC4=324
CC5=325
CC8=326
MSK0=327
MSK1=330
MSK2=331
MSK3=332
MSK4=333
MSK5=334
MSK6=335
MSK7=336
MSK8=337
MSK1S=MSHF0
DSHF0=340
DSHF1=341
DSHF2=342
DSHF3=343
DSHF4=344
DSHF5=345
DSHF6=346
DSHF7=347
DSHF10=350
DSHF11=351
DSHF12=352
DSHF13=353
DSHF14=354
DSHF15=355
DSHF16=356
DSHF17=357
MSHF0=360
MSHF1=361
MSHF2=362
MSHF3=363
MSHF4=364
MSHF5=365
MSHF6=366
MSHF7=367
MSHF10=370
MSHF11=371
MSHF12=372
MSHF13=373
MSHF14=374
MSHF15=375
MSHF16=376
MSHF17=377
;OPERATIONAL ROM PROGRAMS
WINCM=0
RINCMF=10
RINCR1=27
RINCR2=22
RINCR3=21
RINCR4=20
WCDMP=30
RCDMPF=40
RCDMR1=57
RCDMR2=53
RCDMR3=52
RCDMR4=51
RCDMR5=50
WHIDN=60
RHIDNF=100
RHIDR1=137
RHIDR2=131
RHIDR3=130
RHIDR4=127
RHIDR5=136
RHIDR6=123
RHIDR7=122
RHIDR8=121
RHIDR9=120
WASC6=140
RASC6F=150
RAS6R1=177
RAS6R2=176
RAS6R3=163
RAS6R4=162
RAS6R5=161
RAS6R6=160
WAS71=200
RAS71F=210
RA71R1=227
RA71R2=223
RA71R3=222
RA71R4=221
RA71R5=220
WAS72=230
RAS72F=240
RA72R1=257
RA72R2=253
RA72R3=252
RA72R4=251
RA72R5=250
WEM1=260
REM1F=264
REM1R1=271
REM1R2=270
WEM2=274
REM2F=300
REM2R1=305
REM2R2=304
WCOBOL=310
RCOBLF=320
RCBLR1=337
RCBLR2=332
RCBLR3=331
RCBLR4=330