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Trailing-Edge - PDP-10 Archives - bb-4157h-bm_fortran20_v10_16mt9 - fortran-documentation/fortra.bwr
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                       Warnings about Fortran-20 V10



   1.0  KNOWN BUGS AND DEFICIENCIES

   None



   2.0  MANDATORY PATCHES FOR RELATED PRODUCTS

   2.1  Required Microcode

   Microcode version 326 or later must be used with Fortran  V10  and  LINK
   V6.   This  microcode  properly  handles global byte pointers, which are
   used extensively by runtime programs generated by Fortran.



   2.2  TOPS-20 V5.1 SPR 20-19299, PCO 20-MONITO-555

   PCO-MONITO-555 fixes the following problem:

   If a non-zero section is created with SMAP%, but no pages are created in
   that  section,  the SSAVE JSYS would fail to record the empty section in
   the directory area of the .EXE file.  Consequently,  the  program  would
   fail with an '?Illegal memory read' when that section was referenced.

   Since Fortran-20 creates just such a section whenever  /EXTEND  is  used
   and  no DATA statement initializes any .LARG.  variable, there is a high
   probability that this problem would appear with Fortran programs  unless
   the patch is entered.



   2.3  TOPS-20 Splice Fork JSYS

   Autopatch Tape #8 contains a patch to Tops-20 V5.1 which allows LINK  to
   use  the  SPLFK%  JSYS.   This JSYS is used to prevent the creation of a
   temporary EXE file during the linking process.  While  the  creation  of
   this EXE file does no harm, it does take up disk space.
                                                                     Page 2


   3.0  KNOWN DEFICIENCIES IN RELATED PRODUCTS

   3.1  DDT Version 43 With Tops-20 Release 5.1

   DDT version 43 was written for Tops-20 release 6.0, and was not intended
   for use with release 5.1.  Thus, use of DDT V43 with Tops-20 release 5.1
   is unsupported.



   3.2  Swap Space

   The disk swap space will be used at a greater rate when /EXTEND programs
   are  executed.   The system administrator should consider increasing the
   swap space if several multi-section programs are to be executed.



   3.3  Memory Cache Page Clashing

   The memory caching algorithm on a 2060 can cause 'page clashing', or the
   assignment of the same physical memory location to more than one virtual
   memory location.  This could cause programs to run much slower.  A  cure
   is  to re-arrange the allocation of memory used by programs (e.g.  shift
   the .LARG. psect up one section).

   This is not a problem on the 2065.

   [End of FORTRA.BWR]