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klad.sources/msdpmt.xrf
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1 %TITLE 'STIRS TESTS FOR M8621 (DPM) BOARD'
2
3 MODULE MSDPMT (
4 LANGUAGE(BLISS36)
5 ) =
6
7 BEGIN
8
9 !
10 ! COPYRIGHT (C) 1979 BY
11 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
12 !
13 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
14 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
15 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
16 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
17 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
18 ! TRANSFERRED.
19 !
20 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
21 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
22 ! CORPORATION.
23 !
24 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
25 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
26 !
27
28 !++
29 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
30 !
31 ! ABSTRACT:
32 !
33 ! THIS MODULE CONTAIN THE TEST ROUTINES FOR THE KS10 STIMULUS/RESPONSE
34 ! (STIRS) DIAGNOSTIC FOR THE M8621 (DPM) BOARD. IT ALSO CONTAINS SEVERAL
35 ! SUPPORTING SUBROUTINES. THE TEST ROUTINES ARE EXECUTED UNDER CONTROL
36 ! OF THE 'MSSTRC' MODULE. THIS MODULE IS LINKED WITH THE 'MSSTRC' AND
37 ! 'MSDPMD' MODULES TO PRODUCE THE 'MSDPM.EXE' FILE.
38 !
39 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
40 !
41 ! AUTHOR: ARON INSINGA, CREATION DATE: 01-SEP-78
42 !
43 ! MODIFIED BY:
44 !
45 ! ARON INSINGA, 23-MAY-79; VERSION 0.1
46 ! ARON INSINGA, 09-NOV-79; VERSION 1.1
47 ! ARON INSINGA, 23-MAR-80; VERSION 1.2
48 !--
49
50 !
51 ! TABLE OF CONTENTS:
52 !
53
54 FORWARD ROUTINE
55 SPEC_DIALOGUE: NOVALUE, ! SPECIAL FEATURES DIALOGUE
56 SPEC_ASK: NOVALUE, ! SPECIAL FEATURES ASKER
57 SPEC_PRT, ! SPECIAL FEATURES PRINTER
58 TEST_INIT: NOVALUE, ! INITIALIZE STATE OF KS10
59 PF_DISPATCH, ! DETERMINE CAUSE OF PAGE FAIL
60 PF_TRAP, ! REINITIALIZE AFTER PAGE FAIL
61 PF_NAME, ! MAP PF_TRAP CODE TO A STRING
62 SERIAL, ! SERIALLY GET THE VALUE IN Q
63 SCAD_Q, ! GET SCAD VALUE OUT OF Q
64 TST1: NOVALUE, ! DBM MUX #,,# STUCK
65 TST2: NOVALUE, ! DBM MUX DP-SWAPPED STUCK
66 TST3: NOVALUE, ! DBM MUX DP STUCK
67 TST4: NOVALUE, ! SCAD A, SCADA S# STUCK
68 TST5: NOVALUE, ! SCAD DECREMENT 0, 1, 1777
69 TST6: NOVALUE, ! SCAD DOUBLE 0, 1777
70 TST7: NOVALUE, ! SC STUCK
71 TST8: NOVALUE, ! SCADA PTR44
72 TST9: NOVALUE, ! SCADA BYTES STUCK
73 TST10: NOVALUE, ! SCAD OR, B, FE STUCK
74 TST11: NOVALUE, ! SCADB DP SHIFT STUCK
75 TST12: NOVALUE, ! SCADB DP SIZE STUCK
76 TST13: NOVALUE, ! SCADB DP EXP 0, 1777, 1000, 777
77 TST14: NOVALUE, ! DBM MUX BYTES STUCK
78 TST15: NOVALUE, ! DBM MUX BYTE INSERT STUCK
79 TST16: NOVALUE, ! SCAD AND STUCK
80 TST17: NOVALUE, ! SCAD 0, 1777 ADD, SUB, SUBB
81 TST18: NOVALUE, ! VMA EASY BITS STUCK HIGH, LOW
82 TST19: NOVALUE, ! DBM MUX EXP STUCK
83 TST20: NOVALUE, ! MORE VMA FLAGS STUCK
84 TST21: NOVALUE, ! READ & WRITE AC0 VIA VMA
85 TST22: NOVALUE, ! ASK MMC IF ACCESS WAS TO M[0]
86 TST23: NOVALUE, ! READ 0, -1 FROM MEM LOC 0
87 TST24: NOVALUE, ! WRITE 0, -1 TO MEM LOC 0
88 TST25: NOVALUE, ! DPM ADDR STUCK LOW (PHYSICAL)
89 TST26: NOVALUE, ! -VMA STUCK LOW
90 TST27: NOVALUE, ! MEM BITS (# CONTROL)
91 TST28: NOVALUE, ! MEM BITS (DP CONTROL)
92 TST29: NOVALUE, ! MEM BITS (DROM CONTROL)
93 TST30: NOVALUE, ! MEM EN: #<16:17> &C.
94 TST31: NOVALUE, ! BUS REQUEST A (DPM MUX SEL 2)
95 TST32: NOVALUE, ! PT I/O, DPM MUX ADR IN
96 TST33: NOVALUE, ! PT ADR
97 TST34: NOVALUE, ! PT VALID, WRITABLE
98 TST35: NOVALUE, ! VMA USER, VMA PREV LOGIC
99 TST36: NOVALUE, ! PT USER & EXEC/USER PF
100 TST37: NOVALUE, ! WRITABLE ON, WRITE-TEST OFF PF
101 TST38: NOVALUE, ! NXM PF
102 TST39: NOVALUE, ! BAD DATA PF
103 TST40: NOVALUE, ! PAGING OK
104 TST41: NOVALUE, ! PT SWEEP
105 TST42: NOVALUE, ! CD BASIC OPERATION, ENABLES
106 TST43: NOVALUE, ! CD RAM DATA I/O PINS
107 TST44: NOVALUE, ! CD RAM ADDR PINS STUCK
108 TST45: NOVALUE, ! CD SWEEP
109 TST46: NOVALUE, ! CD COMPARATOR OUT STUCK HIGH
110 TST47: NOVALUE, ! CD VALID STUCK HIGH
111 TST48: NOVALUE, ! PT RAM (PAGE #, USER)
112 TST49: NOVALUE, ! PT RAM (VALID, WRITABLE)
113 TST50: NOVALUE, ! CD RAM (PAGE #, USER)
114 TST51: NOVALUE, ! CD RAM (VALID)
115 TST52: NOVALUE, ! PT RAM (CACHABLE)
116 TST53: NOVALUE, ! MEMORY BUS PARITY ERROR
117 TST54: NOVALUE, ! APR FLAGS
118 TST55: NOVALUE, ! APR ENABLES
119 TST56: NOVALUE, ! PT PARITY PINS
120 TST57: NOVALUE, ! PT RAM (PARITY)
121 TST58: NOVALUE, ! CD PARITY PINS
122 TST59: NOVALUE, ! CD RAM (PARITY)
123 TST60: NOVALUE, ! PXCT REG & MUX
124 TST61: NOVALUE, ! PXCT TO XR PREV
125 TST62: NOVALUE, ! SC SIGN
126 TST63: NOVALUE, ! FE SIGN
127 TST64: NOVALUE, ! MSEC OUTPUTS
128 TST65: NOVALUE; ! MSEC TIMING
129
130 !
131 ! INCLUDE FILES:
132 !
133
134 REQUIRE
135 'KSU.R36'; ! KS-10 MICROCODE MACROS
136
137 !
138 ! COPYRIGHT (c) 1977, 1978 BY
139 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
140 !
141 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
142 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
143 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
144 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
145 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
146 ! TRANSFERRED.
147 !
148 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
149 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
150 ! CORPORATION.
151 !
152 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
153 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
154 !
155
156
157 !++
158 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
159 !
160 ! ABSTRACT:
161 !
162 ! THESE MACROS ALLOW YOU TO WRITE MICROINSTRUCTIONS IN A SYMBOLIC FORM
163 ! (DIFFERENT THAN THE NORMAL MICRO CROSS ASSEMBLER) FOR USE AS LITERAL
164 ! VALUES WITHIN A BLISS-36 PROGRAM. MACROS ARE NECESSARY (AS OPPOSED
165 ! TO ARITHMETIC EXPRESSIONS) TO HANDLE SOME FIELDS' DEFAULT VALUES IN
166 ! THE "RIGHT WAY"; THEY DEFAULT TO THE VALUE WHICH MAY HAVE BEEN SET IN
167 ! OTHER FIELDS. ALSO, IT ALLEVIATES YOU FROM HAVING TO REMEMBER WHICH
168 ! OF THE 3 36-BIT PDP-10 WORDS THE FIELD GOES INTO.
169 !
170 ! FUNCTIONAL DESCRIPTION:
171 !
172 ! TO CREATE A MICROINSTRUCTION, CALL THE MACROS FOR THE FIELDS WHICH
173 ! YOU DESIRE TO SPECIFY EXPLICITLY. SOME OF THEM REQUIRE ARGUMENTS;
174 ! SOME OF THEM CALL OTHERS WITH THE APPROPRIATE ARGUMENT. THESE WILL
175 ! EXPAND TO THE NULL LEXEME (THAT IS, THEY GO AWAY). FINALLY, THE
176 ! U MACRO IS CALLED. IT HANDLES THE TRICKY DEFAULTS, EXPANDS TO 3
177 ! DECIMAL CONSTANTS SEPPARATED BY COMMAS, AND RESETS THE COMPILETIME
178 ! VARIABLES BACK TO THEIR INITIAL VALUES (MOSTLY, THE MICROINSTRUCTION
179 ! WITH ALL OF THE SIMPLE FIELDS WITH THEIR DEFAULT VALUES). THE U
180 ! MACRO MAY BE CALLED AS THE ARGUMENT OF A PLIT. IT MAY BE CALLED SEVERAL
181 ! TIMES WITH A COMMA BETWEEN EACH ONE (AND THE FIELD-SETTING MACROS
182 ! BEFORE EACH ONE) TO MAKE A PLIT WITH A BLOCK OF SEVERAL MICROINSTRUCTIONS
183 ! SINCE THE HOOKS INTO CSL WILL PERMIT LOADING SEVERAL MICROINSTRUCTIONS
184 ! INTO CONTIGUOUS CRAM LOCATIONS WITH ONE CALL. MACROS MAY BE DEFINED
185 ! WHICH SET MANY OF THE FIELDS (JUST LIKE IN MICRO) BY HAVING IT CALL THE
186 ! DESIRED FIELD-SETTING MACROS.
187 !
188 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
189 !
190 ! AUTHOR: ARON INSINGA, CREATION DATE: 22-AUG-78
191 !
192 ! MODIFIED BY:
193 !
194 ! ARON INSINGA, 28-AUG-78: VERSION 0.1
195 !--
196
197 !
198 ! TABLE OF CONTENTS:
199 !
200 ! JUMP FIELD
201 ! 2901 ALU FUNCTION
202 ! LEFT SOURCE
203 ! RIGHT SOURCE
204 ! DESTINATION (DP, Q, B)
205 ! DATA PATH ADDRESS A
206 ! DATA PATH ADDRESS B
207 ! RAMFILE ADDRESS
208 ! D-BUS SELECT
209 ! DBM SELECT
210 ! FICTICOUS PARITY-VALIDATE BIT
211 ! CLOCK LEFT HALF OF THE MACHINE
212 ! STORE PARITY FOR LEFT 2901'S
213 ! CHECK LEFT HALF D-BUS PARITY
214 ! CLOCK RIGHT HALF OF THE MACHINE
215 ! STORE PARITY FOR RIGHT 2901'S
216 ! CHECK RIGHT HALF D-BUS PARITY
217 ! SPEC
218 ! SPEC FIELD REDEFINED FOR 7-BIT BYTE STUFF
219 ! SPEC FIELD REDEFINED TO CONTROL SHIFT PATHS
220 ! DISPATCH
221 ! SKIP STUFF
222 ! TIME FIELD
223 ! RANDOM CONTROL BITS
224 ! INJECT A CARRY
225 ! LOAD SC FROM SCAD
226 ! LOAD FE FROM SCAD
227 ! WRITE THE RAM FILE
228 ! START/FINISH MEMORY/I/O CYCLE UNDER CONTROL OF NUMBER FIELD
229 ! THIS MICROINSTRUCTION IS DOING A DIVIDE
230 ! MULTIPRECISION STEP IN DIVIDE, DEAD, DFSB (?)
231 ! FAST SHIFT
232 ! CALL
233 ! MAGIC NUMBER FIELD (#)
234 ! SCAD (SHIFT-COUNT ADDER) FUNCTION
235 ! SCAD A-INPUT MUX
236 ! SCAD B-INPUT MUX
237 ! SCAD NUMBER FIELD
238 ! MICROINSTRUCTION BUILDER
239 !
240 ! MICROINSTRUCTION WITH DEFAULT FIELDS
241 ! MICROINSTRUCTION-FIELD-EXPLICITLY-SET BITS
242 ! MICROINSTRUCTION BEING BUILT
243 !
244
245 !
246 ! MACROS:
247 !
248
249 MACRO
250
251 ! JUMP FIELD
252 U_J(O_CRAM_ADDR) =
253 %ASSIGN(U_0,U_0 OR ((%O %STRING(O_CRAM_ADDR))^24)) %,
254
255 ! 2901 ALU FUNCTION
256 U_ALU(FUNC) =
257 %ASSIGN(U_0,(U_0 AND %O'777707777777') OR ((FUNC)^21)) %,
258
259 U_ALU_ADD = U_ALU(0) %,
260 U_ALU_SUB = U_ALU(1) %,
261 U_ALU_RSUB = U_ALU(2) %,
262 U_ALU_OR = U_ALU(3) %,
263 U_ALU_AND = U_ALU(4) %,
264 U_ALU_MASK = U_ALU(5) %,
265 U_ALU_XOR = U_ALU(6) %,
266 U_ALU_XNOR = U_ALU(7) %,
267
268 ! LEFT SOURCE
269 U_LSRC(SRC) =
270 %ASSIGN(U_0,(U_0 AND %O'777770777777') OR ((SRC)^18)) %,
271
272 U_LSRC_AQ = U_LSRC(0) %,
273 U_LSRC_AB = U_LSRC(1) %,
274 U_LSRC_0Q = U_LSRC(2) %,
275 U_LSRC_0B = U_LSRC(3) %,
276 U_LSRC_0A = U_LSRC(4) %,
277 U_LSRC_DA = U_LSRC(5) %,
278 U_LSRC_DQ = U_LSRC(6) %,
279 U_LSRC_D0 = U_LSRC(7) %,
280
281 ! RIGHT SOURCE
282 U_RSRC(SRC) =
283 %ASSIGN(U_0,(U_0 AND %O'777777077777') OR ((SRC)^15))
284 %ASSIGN(U_SET,U_SET OR U_SET_RSRC) %,
285
286 U_RSRC_AQ = U_RSRC(0) %,
287 U_RSRC_AB = U_RSRC(1) %,
288 U_RSRC_0Q = U_RSRC(2) %,
289 U_RSRC_0B = U_RSRC(3) %,
290 U_RSRC_0A = U_RSRC(4) %,
291 U_RSRC_DA = U_RSRC(5) %,
292 U_RSRC_DQ = U_RSRC(6) %,
293 U_RSRC_D0 = U_RSRC(7) %,
294
295 ! DESTINATION (DP, Q, B)
296 U_DEST(DEST) =
297 %ASSIGN(U_0,(U_0 AND %O'777777707777') OR ((DEST)^12)) %,
298
299 U_DEST_A = U_DEST(0) %,
300 U_DEST_AD = U_DEST(1) %,
301 U_DEST_Q_AD = U_DEST(2) %,
302 U_DEST_PASS = U_DEST(3) %,
303 U_DEST_Q_MUL2 = U_DEST(4) %,
304 U_DEST_AD_MUL2 = U_DEST(5) %,
305 U_DEST_Q_DIV2 = U_DEST(6) %,
306 U_DEST_AD_DIV2 = U_DEST(7) %,
307
308 ! DATA PATH ADDRESS A
309 U_A(DP) =
310 %ASSIGN(U_0,U_0 OR ((DP)^6)) %,
311
312 U_A_MAG = U_A(0) %,
313 U_A_PC = U_A(1) %,
314 U_A_HR = U_A(2) %,
315 U_A_AR = U_A(3) %,
316 U_A_ARX = U_A(4) %,
317 U_A_BR = U_A(5) %,
318 U_A_BRX = U_A(6) %,
319 U_A_ONE = U_A(7) %,
320 U_A_EBR = U_A(8) %,
321 U_A_UBR = U_A(9) %,
322 U_A_MASK = U_A(10) %,
323 U_A_FLG = U_A(11) %,
324 U_A_PI = U_A(12) %,
325 U_A_XWD1 = U_A(13) %,
326 U_A_T0 = U_A(14) %,
327 U_A_T1 = U_A(15) %,
328
329 ! DATA PATH ADDRESS B
330 U_B(DP) =
331 %ASSIGN(U_0,U_0 OR (DP)) %,
332
333 U_B_MAG = U_B(0) %,
334 U_B_PC = U_B(1) %,
335 U_B_HR = U_B(2) %,
336 U_B_AR = U_B(3) %,
337 U_B_ARX = U_B(4) %,
338 U_B_BR = U_B(5) %,
339 U_B_BRX = U_B(6) %,
340 U_B_ONE = U_B(7) %,
341 U_B_EBR = U_B(8) %,
342 U_B_UBR = U_B(9) %,
343 U_B_MASK = U_B(10) %,
344 U_B_FLG = U_B(11) %,
345 U_B_PI = U_B(12) %,
346 U_B_XWD1 = U_B(13) %,
347 U_B_T0 = U_B(14) %,
348 U_B_T1 = U_B(15) %,
349
350 ! RAMFILE ADDRESS
351 U_RAM(SEL) =
352 %ASSIGN(U_1,(U_1 AND %O'77777777777') OR ((SEL)^33)) %,
353
354 U_RAM_AC = U_RAM(0) %,
355 U_RAM_AC_FN = U_RAM(1) %,
356 U_RAM_XR = U_RAM(2) %,
357 U_RAM_VMA = U_RAM(4) %,
358 U_RAM_RAM = U_RAM(6) %,
359 U_RAM_N = U_RAM(7) %,
360
361 ! D-BUS SELECT
362 U_DBUS(SEL) =
363 %ASSIGN(U_1,(U_1 AND %O'747777777777') OR ((SEL)^30)) %,
364
365 U_DBUS_PC_FLAGS = U_DBUS(0) %, ! LEFT HALF
366 U_DBUS_PI_NEW = U_DBUS(0) %, ! BITS 19:21
367 U_DBUS_VMA = U_DBUS(0) %, ! BITS 27:35
368 U_DBUS_DP = U_DBUS(1) %,
369 U_DBUS_RAM = U_DBUS(2) %,
370 U_DBUS_DBM = U_DBUS(3) %,
371
372 ! DBM SELECT
373 U_DBM(SEL) =
374 %ASSIGN(U_1,(U_1 AND %O'770777777777') OR ((SEL)^27)) %,
375
376 U_DBM_SCAD = U_DBM(0) %, ! LEFT HALF
377 U_DBM_PF_DISP = U_DBM(0) %, ! BITS 18:21
378 U_DBM_APR_FLAGS = U_DBM(0) %, ! BITS 22:35
379 U_DBM_BYTES = U_DBM(1) %,
380 U_DBM_EXP = U_DBM(2) %, ! LEFT HALF
381 U_DBM_MSEC = U_DBM(2) %, ! RIGHT HALF
382 U_DBM_DP = U_DBM(3) %,
383 U_DBM_DP_SWAP = U_DBM(4) %,
384 U_DBM_VMA = U_DBM(5) %,
385 U_DBM_MEM = U_DBM(6) %,
386 U_DBM_N = U_DBM(7) %,
387
388 ! FICTICOUS PARITY-VALIDATE BIT
389 U_ALU_PARITY_OK =
390 %ASSIGN(U_3,U_3 OR (1^35)) %,
391
392 ! CLOCK LEFT HALF OF THE MACHINE
393 U_NO_CLKL =
394 %ASSIGN(U_1,U_1 AND %O'777377777777') %,
395
396 ! STORE PARITY FOR LEFT 2901'S
397 U_GENL =
398 %ASSIGN(U_1,U_1 OR (1^25))
399 %ASSIGN(U_SET,U_SET OR U_SET_GENL) %,
400
401 ! CHECK LEFT HALF D-BUS PARITY
402 U_CHKL =
403 %ASSIGN(U_1,U_1 OR (1^24)) %,
404
405 ! CLOCK RIGHT HALF OF THE MACHINE
406 U_NO_CLKR =
407 %ASSIGN(U_1,U_1 AND %O'777737777777') %,
408
409 ! STORE PARITY FOR RIGHT 2901'S
410 U_GENR =
411 %ASSIGN(U_1,U_1 OR (1^22))
412 %ASSIGN(U_SET,U_SET OR U_SET_GENR) %,
413
414 ! CHECK RIGHT HALF D-BUS PARITY
415 U_CHKR =
416 %ASSIGN(U_1,U_1 OR (1^21)) %,
417
418 ! SPEC
419 U_SPEC(X) =
420 %ASSIGN(U_1,U_1 OR ((X)^15)) %,
421
422 U_SPEC_N = U_SPEC(%O'10') %,
423 U_SPEC_CLRCLK = U_SPEC(%O'11') %,
424 U_SPEC_CLRIOLAT = U_SPEC(%O'12') %,
425 U_SPEC_CLRIOBSY = U_SPEC(%O'13') %,
426 U_SPEC_LDPAGE = U_SPEC(%O'14') %,
427 U_SPEC_NICOND = U_SPEC(%O'15') %,
428 U_SPEC_LDPXCT = U_SPEC(%O'16') %,
429 U_SPEC_WAIT = U_SPEC(%O'17') %,
430 U_SPEC_PREV = U_SPEC(%O'20') %,
431 U_SPEC_LOADXR = U_SPEC(%O'21') %,
432 U_SPEC_APRFLAGS = U_SPEC(%O'23') %,
433 U_SPEC_CLRCSH = U_SPEC(%O'24') %,
434 U_SPEC_APR_EN = U_SPEC(%O'25') %,
435 U_SPEC_MEMCLR = U_SPEC(%O'27') %,
436 U_SPEC_SWEEP = U_SPEC(%O'34') %,
437 U_SPEC_PXCT_OFF = U_SPEC(%O'36') %,
438 U_SPEC_INHCRY18 = U_SPEC(%O'40') %,
439 U_SPEC_LOADIR = U_SPEC(%O'41') %,
440 U_SPEC_LDPI = U_SPEC(%O'43') %,
441 U_SPEC_ASHOV = U_SPEC(%O'44') %,
442 U_SPEC_EXPTST = U_SPEC(%O'45') %,
443 U_SPEC_FLAGS = U_SPEC(%O'46') %,
444 U_SPEC_LDACBLK = U_SPEC(%O'47') %,
445 U_SPEC_LDINST = U_SPEC(%O'61') %,
446
447 ! SPEC FIELD REDEFINED FOR 7-BIT BYTE STUFF
448 U_BYTE(X) =
449 %ASSIGN(U_1,(U_1 AND %O'777777077777') OR ((X)^15)) %,
450
451 U_BYTE_1 = U_BYTE(1) %,
452 U_BYTE_2 = U_BYTE(2) %,
453 U_BYTE_3 = U_BYTE(3) %,
454 U_BYTE_4 = U_BYTE(4) %,
455 U_BYTE_5 = U_BYTE(5) %,
456
457 ! SPEC FIELD REDEFINED TO CONTROL SHIFT PATHS
458 U_SHSTYLE(X) =
459 %ASSIGN(U_1,(U_1 AND %O'777777077777') OR ((X)^15)) %,
460
461 U_SHSTYLE_NORM = U_SHSTYLE(0) %,
462 U_SHSTYLE_ZERO = U_SHSTYLE(1) %,
463 U_SHSTYLE_ONES = U_SHSTYLE(2) %,
464 U_SHSTYLE_ROT = U_SHSTYLE(3) %,
465 U_SHSTYLE_ASHC = U_SHSTYLE(4) %,
466 U_SHSTYLE_LSHC = U_SHSTYLE(5) %,
467 U_SHSTYLE_DIV = U_SHSTYLE(6) %,
468 U_SHSTYLE_ROTC = U_SHSTYLE(7) %,
469
470 ! DISPATCH
471 U_DISP(X) =
472 %ASSIGN(U_1,(U_1 AND %O'777777700777') OR ((X)^9)) %,
473
474 U_DISP_CONSOLE = U_DISP(%O'00') %,
475 U_DISP_DROM = U_DISP(%O'12') %,
476 U_DISP_AREAD = U_DISP(%O'13') %,
477 U_DISP_DP_LEFT = U_DISP(%O'31') %,
478 U_DISP_NORM = U_DISP(%O'34') %,
479 U_DISP_DP = U_DISP(%O'35') %,
480 U_DISP_ADISP = U_DISP(%O'36') %,
481 U_DISP_BDISP = U_DISP(%O'37') %,
482 U_DISP_RETURN = U_DISP(%O'41') %,
483 U_DISP_MUL = U_DISP(%O'62') %,
484 U_DISP_PAGEFAIL = U_DISP(%O'63') %,
485 U_DISP_NICOND = U_DISP(%O'64') %,
486 U_DISP_BYTE = U_DISP(%O'65') %,
487 U_DISP_EAMODE = U_DISP(%O'66') %,
488 U_DISP_SCAD0 = U_DISP(%O'67') %,
489
490 ! SKIP STUFF
491 U_SKIP(X) =
492 %ASSIGN(U_1,(U_1 AND %O'777777777007') OR ((X)^3)) %,
493
494 U_SKIP_IOLGL = U_SKIP(%O'04') %,
495 U_SKIP_LLE = U_SKIP(%O'12') %,
496 U_SKIP_CRY0 = U_SKIP(%O'31') %,
497 U_SKIP_ADLEQ0 = U_SKIP(%O'32') %,
498 U_SKIP_ADREQ0 = U_SKIP(%O'33') %,
499 U_SKIP_KERNEL = U_SKIP(%O'34') %,
500 U_SKIP_FPD = U_SKIP(%O'35') %,
501 U_SKIP_AC0 = U_SKIP(%O'36') %,
502 U_SKIP_INT = U_SKIP(%O'37') %,
503 U_SKIP_LE = U_SKIP(%O'42') %,
504 U_SKIP_CRY2 = U_SKIP(%O'51') %,
505 U_SKIP_DP0 = U_SKIP(%O'52') %,
506 U_SKIP_DP18 = U_SKIP(%O'53') %,
507 U_SKIP_IOT = U_SKIP(%O'54') %,
508 U_SKIP_JFCL = U_SKIP(%O'55') %,
509 U_SKIP_CRY1 = U_SKIP(%O'56') %,
510 U_SKIP_TXXX = U_SKIP(%O'57') %,
511 U_SKIP_TRAP_CYC = U_SKIP(%O'61') %,
512 U_SKIP_ADEQ0 = U_SKIP(%O'62') %,
513 U_SKIP_SC = U_SKIP(%O'63') %,
514 U_SKIP_EXECUTE = U_SKIP(%O'64') %,
515 U_SKIP_IO_BUSY = U_SKIP(%O'65') %,
516 U_SKIP_CONTINUE = U_SKIP(%O'66') %,
517 U_SKIP_1_MS = U_SKIP(%O'67') %,
518
519 ! TIME FIELD [O.E. "UT" = MDN.E. "OUT"]
520 U_T(X) =
521 %ASSIGN(U_1,(U_1 AND %O'777777777774') OR (X)) %,
522
523 ! RANDOM CONTROL BITS
524
525 ! INJECT A CARRY
526 U_CRY38 =
527 %ASSIGN(U_2,U_2 OR (1^35)) %,
528
529 ! LOAD SC FROM SCAD
530 U_LOADSC =
531 %ASSIGN(U_2,U_2 OR (1^34)) %,
532
533 ! LOAD FE FROM SCAD
534 U_LOADFE =
535 %ASSIGN(U_2,U_2 OR (1^33)) %,
536
537 ! WRITE THE RAM FILE
538 U_FMWRITE =
539 %ASSIGN(U_2,U_2 OR (1^32)) %,
540
541 ! START/FINISH MEMORY/I/O CYCLE UNDER CONTROL OF NUMBER FIELD
542 U_MEM =
543 %ASSIGN(U_2,U_2 OR (1^31)) %,
544
545 ! THIS MICROINSTRUCTION IS DOING A DIVIDE
546 U_DIVIDE =
547 %ASSIGN(U_2,U_2 OR (1^30)) %,
548
549 ! MULTIPRECISION STEP IN DIVIDE, DEAD, DFSB (?)
550 U_MULTI_PREC =
551 %ASSIGN(U_2,U_2 OR (1^29)) %,
552
553 ! FAST SHIFT
554 U_MULTI_SHIFT =
555 %ASSIGN(U_2,U_2 OR (1^28)) %,
556
557 ! CALL
558 U_CALL =
559 %ASSIGN(U_2,U_2 OR (1^27)) %,
560
561 ! MAGIC NUMBER FIELD (#)
562 U_N(O_N) =
563 %ASSIGN(U_2,U_2 OR (%O %STRING(O_N))) %,
564
565 ! MAGIC NUMBER FIELD REDEFINED FOR SHIFT-COUNT ADDER (SCAD) CONTROL
566
567 ! SCAD FUNCTION
568 U_SCAD(X) =
569 %ASSIGN(U_2,(U_2 AND %O'777777077777') OR ((X)^15)) %,
570
571 U_SCAD_A_MUL2 = U_SCAD(0) %,
572 U_SCAD_OR = U_SCAD(1) %,
573 U_SCAD_SUBB = U_SCAD(2) %,
574 U_SCAD_SUB = U_SCAD(3) %,
575 U_SCAD_ADD = U_SCAD(4) %,
576 U_SCAD_AND = U_SCAD(5) %,
577 U_SCAD_A_DEC = U_SCAD(6) %,
578 U_SCAD_A = U_SCAD(7) %,
579
580 ! SCAD A INPUT MUX
581 U_SCADA(X) =
582 %ASSIGN(U_2,(U_2 AND %O'777777707777') OR ((X)^12)) %,
583
584 U_SCADA_SC = U_SCADA(0) %,
585 U_SCADA_SN = U_SCADA(1) %,
586 U_SCADA_PTR44 = U_SCADA(2) %,
587 U_SCADA_BYTE1 = U_SCADA(3) %,
588 U_SCADA_BYTE2 = U_SCADA(4) %,
589 U_SCADA_BYTE3 = U_SCADA(5) %,
590 U_SCADA_BYTE4 = U_SCADA(6) %,
591 U_SCADA_BYTE5 = U_SCADA(7) %,
592
593 ! SCAD B INPUT MUX
594 U_SCADB(X) =
595 %ASSIGN(U_2,(U_2 AND %O'777777771777') OR ((X)^10)) %,
596
597 U_SCADB_FE = U_SCADB(0) %,
598 U_SCADB_EXP = U_SCADB(1) %,
599 U_SCADB_SHIFT = U_SCADB(2) %,
600 U_SCADB_SIZE = U_SCADB(3) %,
601
602 ! SCAD/SMALL NUMBER FIELD
603 U_SN(O_SN) =
604 %ASSIGN(U_2,(U_2 AND %O'777777776000') OR (%O %STRING(O_SN))) %,
605
606 ! MICROINSTRUCTION BUILDER
607 ! HANDLE DEFAULTS FOR FIELDS WHICH DEFAULT TO OTHER FIELDS.
608 ! EXPAND OUT TO THE 3 WORDS (108 BIT FORMAT) WITH COMMAS.
609 ! RESET ALL THE COMPILETIME VARIABLES TO THEIR ORIGINAL VALUES.
610 U =
611
612 ! DEFAULT RSRC = LSRC
613 %IF (U_SET AND U_SET_RSRC) EQL 0
614 %THEN
615 %ASSIGN(U_0,U_0 OR ((U_0^(-3)) AND %O'700000'))
616 %FI
617
618 ! DEFAULT GENL = ALU_PARITY_OK
619 %IF (U_SET AND U_SET_GENL) EQL 0
620 %THEN
621 %ASSIGN(U_1,U_1 OR ((U_3^(-10)) AND %O'000200000000'))
622 %FI
623
624 ! DEFAULT GENR = ALU_PARITY_OK
625 %IF (U_SET AND U_SET_GENR) EQL 0
626 %THEN
627 %ASSIGN(U_1,U_1 OR ((U_3^(-13)) AND %O'000020000000'))
628 %FI
629
630 U_0,U_1,U_2
631
632 %ASSIGN(U_0,U_0_DEFAULT)
633 %ASSIGN(U_1,U_1_DEFAULT)
634 %ASSIGN(U_2,U_2_DEFAULT)
635 %ASSIGN(U_3,U_3_DEFAULT)
636 %ASSIGN(U_SET,0) %;
637
638 !
639 ! EQUATED SYMBOLS:
640 !
641
642 LITERAL
643
644 ! MICROINSTRUCTION WITH DEFAULT FIELDS
645 U_0_DEFAULT = %O'000044030000',
646 U_1_DEFAULT = %O'417440070703',
647 U_2_DEFAULT = %O'000000000000',
648 U_3_DEFAULT = %O'000000000000',
649
650 ! MICROINSTRUCTION-FIELD-EXPLICITLY-SET BITS
651 U_SET_RSRC = %O'1',
652 U_SET_GENL = %O'2',
653 U_SET_GENR = %O'4';
654
655 COMPILETIME
656
657 ! MICROINSTRUCTION BEING BUILT
658 U_0 = U_0_DEFAULT,
659 U_1 = U_1_DEFAULT,
660 U_2 = U_2_DEFAULT,
661 U_3 = U_3_DEFAULT,
662 U_SET = 0;
663
664 ! END OF "KSU.R36"
665
666
667 REQUIRE
668 'STIRSD.R36'; ! COMMON STIRS DECLARATIONS
669
670 !
671 ! COPYRIGHT (c) 1977, 1978 BY
672 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
673 !
674 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
675 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
676 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
677 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
678 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
679 ! TRANSFERRED.
680 !
681 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
682 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
683 ! CORPORATION.
684 !
685 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
686 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
687 !
688
689 !++
690 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
691 !
692 ! ABSTRACT:
693 !
694 ! THESE ARE THE COMMON DECLARATIONS WHICH ARE USED BY THE TEST MODULES
695 ! FOR THE DIFFERENT STIRS DIAGNOSTICS.
696 !
697 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
698 !
699 ! AUTHOR: ARON INSINGA, CREATION DATE: 01-SEP-78
700 !
701 ! MODIFIED BY:
702 !
703 ! ARON INSINGA, 23-MAY-79: VERSION 0.1
704 !--
705
706 !
707 ! MACROS:
708 !
709
710 MACRO
711 LOAD_U(CRAM_ADDR,SOURCE_ADDR) = LOADUC(%O %STRING(CRAM_ADDR),SOURCE_ADDR) %,
712 LC(O_CRAM_ADDR) = LCA(%O %STRING(O_CRAM_ADDR)) %,
713 SET_C(O_CRAM_ADDR) = SETNXT(%O %STRING(O_CRAM_ADDR)) %,
714 STEP_U_NEXT(N) = (CP(N);EX_NXT) %,
715 BEGIN_XLIST = BEGIN SWITCHES LIST(NOSOURCE); %,
716 END_LIST = SWITCHES LIST(SOURCE); END %,
717 DM(ADDR,DATA) = MEM_DEPOSIT(%O %STRING(ADDR),%O %STRING(DATA)) %,
718 EM(ADDR) = MEM_EXAMINE(%O %STRING(ADDR)) %,
719 DI(ADDR,DATA) = IO_DEPOSIT(%O %STRING(ADDR),%O %STRING(DATA)) %,
720 EI(ADDR) = IO_EXAMINE(%O %STRING(ADDR)) %,
721 EX_NXT = EXNEXT() %,
722 RD_0 = REG_EXAMINE(%O'0')%,
723 RD_1 = REG_EXAMINE(%O'1')%,
724 RD_2 = REG_EXAMINE(%O'2')%,
725 RD_3 = REG_EXAMINE(%O'3')%,
726 RD_100 = REG_EXAMINE(%O'100')%,
727 RD_101 = REG_EXAMINE(%O'101')%,
728 RD_102 = REG_EXAMINE(%O'102')%,
729 RD_103 = REG_EXAMINE(%O'103')%,
730 RD_300 = REG_EXAMINE(%O'300')%,
731 RD_301 = REG_EXAMINE(%O'301')%,
732 RD_303 = REG_EXAMINE(%O'303')%;
733
734 !
735 ! EQUATED SYMBOLS:
736 !
737
738 BUILTIN
739 POINT,
740 SCANI,
741 REPLACEI;
742
743 EXTERNAL ROUTINE
744 CONTROL: NOVALUE,
745 MEMSIZE,
746 ERR: NOVALUE,
747 ERRCA: NOVALUE,
748 ERRCAS: NOVALUE,
749 ERRS: NOVALUE,
750 ERRM: NOVALUE,
751 ERMCA: NOVALUE,
752 ERMCAS: NOVALUE,
753 ERMS: NOVALUE,
754 NOERR: NOVALUE,
755 FAILURE: NOVALUE,
756 LOOP_CHK,
757 FLP_CHK,
758 CHK_ERR_MSG: NOVALUE,
759 WAIT: NOVALUE,
760 SEND_LINE,
761 REPEAT: NOVALUE,
762 PTSTNUM: NOVALUE,
763 CP: NOVALUE,
764 CP_NOSS: NOVALUE,
765 SEND_NUL,
766 SETNXT: NOVALUE,
767 EXNEXT,
768 WR_CRAM,
769 X1,
770 LOADUC: NOVALUE,
771 MR: NOVALUE,
772 PE: NOVALUE,
773 CE: NOVALUE,
774 CS: NOVALUE,
775 CH: NOVALUE,
776 TP: NOVALUE,
777 TE: NOVALUE,
778 EJ,
779 SC_0: NOVALUE,
780 EC,
781 LCA: NOVALUE,
782 DC_035: NOVALUE,
783 MOD_FLD: NOVALUE,
784 DM_CHK,
785 MEM_DEPOSIT: NOVALUE,
786 MEM_EXAMINE,
787 EM_CHK,
788 DN: NOVALUE,
789 IO_DEPOSIT: NOVALUE,
790 IO_EXAMINE,
791 EI_CHK,
792 REG_EXAMINE,
793 WRT100: NOVALUE,
794 WRT102: NOVALUE,
795 WRT103: NOVALUE,
796 WRT104: NOVALUE,
797 WRT105: NOVALUE,
798 WRT106: NOVALUE,
799 WRT107: NOVALUE,
800 WRT110: NOVALUE,
801 WRT111: NOVALUE,
802 WRT112: NOVALUE,
803 WRT113: NOVALUE,
804 WRT114: NOVALUE,
805 WRT115: NOVALUE,
806 WRT116: NOVALUE,
807 WRT204: NOVALUE,
808 WRT205: NOVALUE,
809 WRT206: NOVALUE,
810 WRT210: NOVALUE,
811 WRT212: NOVALUE,
812 SYNC_CLK: NOVALUE,
813 TICK: NOVALUE;
814
815 EXTERNAL
816 NO_SUBSET,
817 LPONTST,
818 TIMOUT,
819 RPT_ERR_FLAG,
820 ERRFLG;
821
822 ! END OF "STIRSD.R36"
823
824
825 REQUIRE
826 'CSLMAC.R36'; ! CSL INTERFACE MACROS
827
828 !
829 ! COPYRIGHT (c) 1977, 1978 BY
830 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
831 !
832 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
833 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
834 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
835 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
836 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
837 ! TRANSFERRED.
838 !
839 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
840 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
841 ! CORPORATION.
842 !
843 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
844 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
845 !
846
847 !++
848 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
849 !
850 ! ABSTRACT:
851 !
852 ! THIS FILE CONTAINS MACROS WHICH ARE USED TO COMMUNICATE WITH THE
853 ! 'CSL' PROGRAM. THE MACROS EXPAND TO LUUO CALLS WHICH PERFORM TTY
854 ! INPUT AND OUTPUT AND SEND ASCIZ COMMAND LINES TO THE 8080.
855 !
856 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
857 !
858 ! AUTHOR: RICH MURATORI , CREATION DATE: 12-DEC-78
859 !
860 ! MODIFIED BY:
861 !
862 ! RICH MURATORI, 12-DEC-78 : VERSION 0.1
863 !--
864
865 BUILTIN UUO;
866
867 LITERAL
868 ER_AC = 1,
869 EI_AC = 2,
870 EJ_AC = 3,
871 EK_AC = 4,
872 EB_AC = 5,
873 EC_AC = 6,
874 EM_AC = 7,
875 PM_AC = 8,
876 X1A_AC = 9,
877 X1B_AC = 10;
878
879
880 !MACROS TO DEFINE PRINTING CALLS MADE TO 'CSL' PROGRAM VIA UUO
881
882 BIND CR_LF = UPLIT(%CHAR(13,10,0));
883
884 MACRO
885 PRINT_CRLF = BEGIN
886 AC0 = CR_LF;
887 UUO(0,31,15,0);
888 END%,
889 PNTSIX(MSGWORD) = BEGIN
890 AC0 = MSGWORD;
891 UUO(0,31,0,2);
892 END%,
893 PRINT_MSG(MSGADR)= BEGIN
894 AC0 = MSGADR;
895 UUO(0,31,15,0);
896 END%,
897 PRINT_WORD(ADDR) = BEGIN
898 AC0 = ADDR;
899 UUO(0,31,0,0);
900 END%,
901 PRINT_TXT(TEXT) = BEGIN
902 AC0 = UPLIT(%ASCIZ TEXT);
903 UUO(0,31,15,0);
904 END%,
905 PTXT_CRLF(TEXT) = BEGIN
906 AC0 = UPLIT(%STRING(TEXT,%CHAR(13,10,0)));
907 UUO(0,31,15,0);
908 END%,
909 PRINT_DEC(NUM) = BEGIN
910 AC0 = NUM;
911 UUO(0,31,13,0);
912 END%,
913 PRT_CRLF_F = BEGIN
914 AC0 = CR_LF;
915 UUO(0,31,15,1);
916 END%,
917 PRT_MSG_F(MSGADR)= BEGIN
918 AC0 = MSGADR;
919 UUO(0,31,15,1);
920 END%,
921 PRT_TXT_F(TEXT) = BEGIN
922 AC0 = UPLIT(%ASCIZ TEXT);
923 UUO(0,31,15,1);
924 END%,
925 PTXT_CRLF_F(TEXT) = BEGIN
926 AC0 = UPLIT(%STRING(TEXT,%CHAR(13,10,0)));
927 UUO(0,31,15,1);
928 END%,
929 PRT_DEC_F(NUM) = BEGIN
930 AC0 = NUM;
931 UUO(0,31,13,1);
932 END%,
933 PRINT_OCT_1(NUM)= BEGIN
934 AC0 = NUM;
935 UUO(0,31,1,0);
936 END%,
937 PRINT_OCT_2(NUM)= BEGIN
938 AC0 = NUM;
939 UUO(0,31,2,0);
940 END%,
941 PRINT_OCT_3(NUM)= BEGIN
942 AC0 = NUM;
943 UUO(0,31,3,0);
944 END%,
945 PRINT_OCT_4(NUM)= BEGIN
946 AC0 = NUM;
947 UUO(0,31,4,0);
948 END%,
949 PRINT_OCT_5(NUM)= BEGIN
950 AC0 = NUM;
951 UUO(0,31,5,0);
952 END%,
953 PRINT_OCT_6(NUM)= BEGIN
954 AC0 = NUM;
955 UUO(0,31,6,0);
956 END%,
957 PRINT_OCT_7(NUM)= BEGIN
958 AC0 = NUM;
959 UUO(0,31,7,0);
960 END%,
961 PRINT_OCT_8(NUM)= BEGIN
962 AC0 = NUM;
963 UUO(0,31,8,0);
964 END%,
965 PRINT_OCT_11(NUM)= BEGIN
966 AC0 = NUM;
967 UUO(0,31,11,0);
968 END%,
969 PRINT_OCT_12(NUM)= BEGIN
970 AC0 = NUM;
971 UUO(0,31,12,0);
972 END%,
973 POCT_SUP(NUM) = BEGIN
974 AC0 = NUM;
975 UUO(0,31,14,3);
976 END%,
977 PBELL = UUO(0,31,1,7)%,
978
979 !MACROS TO DEFINE UUO CALLS TO 'CSL' PROGRAM FOR TTY INPUT
980
981 TT_ALTM = UUO(1,31,7,3)%,
982 TTI_YES = UUO(1,31,1,3)%,
983 TTI_CLR = UUO(0,31,10,3)%,
984 TTI_DEC = UUO(1,31,4,3)%,
985
986 !MACRO TO DEFINE END OF PROGRAM UUO
987
988 EOP_UUO = UUO(0,31,14,4)%,
989
990 !MACROS TO DEFINE UUO CALLS TO 'CSL' TO SEND CMD STRINGS WITH RESPONSE
991
992 SEND_ER_LINE = UUO(0,1,ER_AC,0)%,
993 SEND_EI_LINE = UUO(0,1,EI_AC,0)%,
994 SEND_EJ_LINE = UUO(0,1,EJ_AC,0)%,
995 SEND_EK_LINE = UUO(0,1,EK_AC,0)%,
996 SEND_EB_LINE = UUO(0,1,EB_AC,0)%,
997 SEND_EC_LINE = UUO(0,1,EC_AC,0)%,
998 SEND_EM_LINE = UUO(0,1,EM_AC,0)%,
999 SEND_PM_LINE = UUO(0,1,PM_AC,0)%,
1000 SEND_X1A_LINE = UUO(0,1,X1A_AC,0)%,
1001 SEND_X1B_LINE = UUO(0,1,X1B_AC,0)%,
1002
1003 !MACRO TO DEFINE UUO CALL TO 'CSL' PROGRAM TO SEND ASCIZ CMD STRING
1004
1005 SEND_CMD_LINE = UUO(0,1,0,0)%,
1006
1007 !MACRO TO DEFINE UUO CALL TO 'CSL' PROGRAM TO SEND ASCIZ CMD LINE
1008
1009 SEND_UUO_1 = UUO(0,1,1,0)%,
1010
1011 !MACRO TO DEFINE ERROR MESSAGE CHECK CALL TO 'CSL'
1012
1013 MSG_CHK_UUO = UUO(0,3,0,0)%,
1014
1015 !MACRO TO DEFINE 'CSL' UUO TO PASS CONTROL-T INFO
1016
1017 SEND_INFO = UUO(0,3,1,0)%,
1018
1019 !MACROS TO DEFINE FILE HANDLING UUOS TO 'CSL' PROGRAM
1020
1021 FSELECT(FILNAM_ADR) = (AC0 = FILNAM_ADR;
1022 UUO(1,31,5,4))%,
1023 FRDPAG = UUO(1,31,8,4)%;
1024
1025 !8080 ERROR MESSAGE FORMATS WHICH ARE CHECKED FOR.
1026
1027 BIND
1028 HALTED = UPLIT(%ASCIZ '%HLTD'),
1029 MEM_REF_ERR = UPLIT(%ASCIZ '?MRE'),
1030 PAR_ERR = UPLIT(%ASCIZ '?PAR_ERR');
1031
1032 ! END OF 'CSL.MAC'
1033
1034 REQUIRE
1035 'REGBIT.R36'; ! 8080 REGISTER BIT-NAMES
1036
1037 !
1038 ! COPYRIGHT (c) 1977, 1978 BY
1039 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
1040 !
1041 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
1042 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
1043 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
1044 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
1045 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
1046 ! TRANSFERRED.
1047 !
1048 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
1049 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
1050 ! CORPORATION.
1051 !
1052 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
1053 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
1054 !
1055
1056 !++
1057 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
1058 !
1059 ! ABSTRACT:
1060 !
1061 ! THIS FILE CONTAINS SYMBOLIC BIT DEFINITIONS FOR THE KS10 8080 I/O
1062 ! REGISTERS. IT IS USED AS A 'REQUIRE' FILE FOR THE STIRS DIAGNOSTICS.
1063 !
1064 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
1065 !
1066 ! AUTHOR: RICH MURATORI , CREATION DATE: 3-JAN-79
1067 !
1068 ! MODIFIED BY:
1069 !
1070 ! RICH MURATORI, 3-JAN-79 : VERSION 0.1
1071 !--
1072
1073 LITERAL
1074
1075 !WRITE REGISTER 100
1076
1077 FORCE_PAR = 1^1, !FORCE PARITY RIGHT
1078 EN_1MS = 1^2, !1 MSEC ENABLE
1079 CACHE_ENB = 1^3, !CACHE ENABLE
1080 DP_PE_DET = 1^4, !DP PE DETECT
1081 CRM_PE_DET = 1^5, !CRM PE DETECT
1082 PE_DET_ENB = 1^6, !PE DETECT ENABLE
1083 RESET = 1^7, !RESET
1084
1085 !WRITE REGISTER 102/103
1086
1087 DATA35 = 1^0, !KS10 BUS DATA BIT 35
1088 DATA34 = 1^1, !KS10 BUS DATA BIT 34
1089 DATA33 = 1^2, !KS10 BUS DATA BIT 33
1090 DATA32 = 1^3, !KS10 BUS DATA BIT 32
1091 DATA31 = 1^4, !KS10 BUS DATA BIT 31
1092 DATA30 = 1^5, !KS10 BUS DATA BIT 30
1093 DATA29 = 1^6, !KS10 BUS DATA BIT 29
1094 DATA28 = 1^7, !KS10 BUS DATA BIT 28
1095
1096 !WRITE REGISTER 104/105
1097
1098 DATA27 = 1^0, !KS10 BUS DATA BIT 27
1099 DATA26 = 1^1, !KS10 BUS DATA BIT 26
1100 DATA25 = 1^2, !KS10 BUS DATA BIT 25
1101 DATA24 = 1^3, !KS10 BUS DATA BIT 24
1102 DATA23 = 1^4, !KS10 BUS DATA BIT 23
1103 DATA22 = 1^5, !KS10 BUS DATA BIT 22
1104 DATA21 = 1^6, !KS10 BUS DATA BIT 21
1105 DATA20 = 1^7, !KS10 BUS DATA BIT 20
1106
1107 !WRITE REGISTER 106/107
1108
1109 DATA19 = 1^0, !KS10 BUS DATA BIT 19
1110 DATA18 = 1^1, !KS10 BUS DATA BIT 18
1111 DATA17 = 1^2, !KS10 BUS DATA BIT 17
1112 DATA16 = 1^3, !KS10 BUS DATA BIT 16
1113 DATA15 = 1^4, !KS10 BUS DATA BIT 15
1114 DATA14 = 1^5, !KS10 BUS DATA BIT 14
1115 DATA13 = 1^6, !KS10 BUS DATA BIT 13
1116 DATA12 = 1^7, !KS10 BUS DATA BIT 12
1117
1118 !WRITE REGISTER 110/111
1119
1120 DATA11 = 1^0, !KS10 BUS DATA BIT 11
1121 DATA10 = 1^1, !KS10 BUS DATA BIT 10
1122 DATA9 = 1^2, !KS10 BUS DATA BIT 9
1123 DATA8 = 1^3, !KS10 BUS DATA BIT 8
1124 DATA7 = 1^4, !KS10 BUS DATA BIT 7
1125 DATA6 = 1^5, !KS10 BUS DATA BIT 6
1126 DATA5 = 1^6, !KS10 BUS DATA BIT 5
1127 DATA4 = 1^7, !KS10 BUS DATA BIT 4
1128
1129 !WRITE REGISTER 112/113
1130
1131 DATA3 = 1^0, !KS10 BUS DATA BIT 3
1132 DATA2 = 1^1, !KS10 BUS DATA BIT 2
1133 DATA1 = 1^2, !KS10 BUS DATA BIT 1
1134 DATA0 = 1^3, !KS10 BUS DATA BIT 0
1135
1136 !WRITE REGISTER 114/115
1137
1138 DATA_CYCLE = 1^0, !DATA CYCLE
1139 IO_DATA = 1^1, !I/O DATA CYCLE
1140 COM_ADR = 1^2, !COM/ADR CYCLE
1141 BAD_DATA = 1^3, !BAD DATA CYCLE
1142
1143 !WRITE REGISTER 116
1144
1145 CSL_INT = 1^0, !CSL INTERRUPT THE 10
1146
1147 !WRITE REGISTER 204
1148
1149 CRAM_RESET = 1^0, !CRAM RESET
1150 STK_RESET = 1^1, !STACK RESET
1151 DP_RESET = 1^2, !DP RESET
1152 SS_MODE = 1^3, !SINGLE STEP MODE
1153 CRAM_ADR_LD = 1^4, !CRAM ADR LOAD
1154 CRAM_WRT = 1^5, !CRAM WRITE
1155
1156 !WRITE REGISTER 205
1157
1158 DIAG1 = 1^0, !DIAG FN BIT 1
1159 DIAG2 = 1^1, !DIAG FN BIT 2
1160 DIAG4 = 1^2, !DIAG FN BIT 4
1161 DIAG10 = 1^3, !DIAG FN BIT 10
1162 TRAP_ENB = 1^4, !TRAP ENABLE
1163 CLR_INT = 1^5, !CLEAR 10 INTERRUPT
1164 MNT_CLK_ENB = 1^6, !MAINT CLK ENABLE
1165 MAINT_CLK = 1^7, !MAINT CLK PULSE
1166
1167 !WRITE REGISTER 206
1168
1169 CLK_RUN = 1^0, !CLOCK RUN
1170 SINGLE_CLK = 1^1, !SINGLE CLOCK
1171
1172 !WRITE REGISTER 210
1173
1174 CLOSE_LATCH = 1^0, !CLOSE LATCHS
1175 LATCH_DATA = 1^1, !LATCH DATA (1)
1176 CRA_R_CLK = 1^2, !CRA R CLK ENB (1)
1177 CRA_T_CLK = 1^3, !CRA T CLK ENB (1)
1178 XMIT_DATA = 1^4, !XMIT DATA (1)
1179 XMIT_ADR = 1^5, !XMIT ADR (1)
1180 BUS_REQ = 1^6, !BUS REQ
1181 MEM = 1^7, !MEM
1182
1183 !WRITE REGISTER 212
1184
1185 CONTINUE = 1^0, !CONTINUE
1186 EXECUTE = 1^1, !EXECUTE
1187 RUN = 1^2, !RUN
1188
1189
1190
1191 !READ REGISTER 0
1192
1193 RDATA35 = 1^0, !KS10 BUS DATA BIT 35
1194 RDATA34 = 1^1, !KS10 BUS DATA BIT 34
1195 RDATA33 = 1^2, !KS10 BUS DATA BIT 33
1196 RDATA32 = 1^3, !KS10 BUS DATA BIT 32
1197 RDATA31 = 1^4, !KS10 BUS DATA BIT 31
1198 RDATA30 = 1^5, !KS10 BUS DATA BIT 30
1199 RDATA29 = 1^6, !KS10 BUS DATA BIT 29
1200 RDATA28 = 1^7, !KS10 BUS DATA BIT 28
1201
1202 !READ REGISTER 1
1203
1204 RDATA27 = 1^0, !KS10 BUS DATA BIT 27
1205 RDATA26 = 1^1, !KS10 BUS DATA BIT 26
1206 RDATA25 = 1^2, !KS10 BUS DATA BIT 25
1207 RDATA24 = 1^3, !KS10 BUS DATA BIT 24
1208 RDATA23 = 1^4, !KS10 BUS DATA BIT 23
1209 RDATA22 = 1^5, !KS10 BUS DATA BIT 22
1210 RDATA21 = 1^6, !KS10 BUS DATA BIT 21
1211 RDATA20 = 1^7, !KS10 BUS DATA BIT 20
1212
1213 !READ REGISTER 2
1214
1215 RDATA19 = 1^0, !KS10 BUS DATA BIT 19
1216 RDATA18 = 1^1, !KS10 BUS DATA BIT 18
1217 RDATA17 = 1^2, !KS10 BUS DATA BIT 17
1218 RDATA16 = 1^3, !KS10 BUS DATA BIT 16
1219 RDATA15 = 1^4, !KS10 BUS DATA BIT 15
1220 RDATA14 = 1^5, !KS10 BUS DATA BIT 14
1221 RDATA13 = 1^6, !KS10 BUS DATA BIT 13
1222 RDATA12 = 1^7, !KS10 BUS DATA BIT 12
1223
1224 !READ REGISTER 3
1225
1226 RDATA11 = 1^0, !KS10 BUS DATA BIT 11
1227 RDATA10 = 1^1, !KS10 BUS DATA BIT 10
1228 RDATA9 = 1^2, !KS10 BUS DATA BIT 9
1229 RDATA8 = 1^3, !KS10 BUS DATA BIT 8
1230 RDATA7 = 1^4, !KS10 BUS DATA BIT 7
1231 RDATA6 = 1^5, !KS10 BUS DATA BIT 6
1232 RDATA5 = 1^6, !KS10 BUS DATA BIT 5
1233 RDATA4 = 1^7, !KS10 BUS DATA BIT 4
1234
1235 !READ REGISTER 100
1236
1237 ADPT2_PE = 1^0, !UNIBUS ADAPTER 2 PARITY ERR
1238 CRA_PE = 1^1, !CRA PARITY ERR
1239 DP_PE = 1^2, !DP PARITY ERR
1240 MEM_PE = 1^3, !MEM PARITY ERR
1241 CRAM_PE = 1^4, !CRAM PARITY ERR
1242 ADPT3_PE = 1^6, !UNIBUS ADAPTER 3 PARITY ERR
1243 REC_PE = 1^7, !RECEIVED PARITY ERR
1244
1245 !READ REGISTER 101
1246
1247 MMC_REF_ERR = 1^0, !MEM REFRESH ERR
1248 PI_REQ_7 = 1^1, !PI REQ 7
1249 PI_REQ_6 = 1^2, !PI REQ 6
1250 PI_REQ_5 = 1^3, !PI REQ 5
1251 PI_REQ_4 = 1^4, !PI REQ 4
1252 PI_REQ_3 = 1^5, !PI REQ 3
1253 PI_REQ_2 = 1^6, !PI REQ 2
1254 PI_REQ_1 = 1^7, !PI REQ 1
1255
1256 !READ REGISTER 102
1257
1258 RDATA = 1^0, !DATA CYCLE
1259 RIO_DATA = 1^1, !I/O DATA CYCLE
1260 RCOM_ADR = 1^2, !COM/ADR CYCLE
1261 RBAD_DATA = 1^3, !BAD DATA CYCLE
1262 RIO_BUSY = 1^4, !I/O BUSY
1263 RMEM_BUSY = 1^5, !MEM BUSY
1264 RRESET = 1^6, !RESET
1265 RAC_LO = 1^7, !AC LO
1266
1267 !READ REGISTER 103
1268
1269 RDATA3 = 1^0, !KS10 BUS DATA BIT 3
1270 RDATA2 = 1^1, !KS10 BUS DATA BIT 2
1271 RDATA1 = 1^2, !KS10 BUS DATA BIT 1
1272 RDATA0 = 1^3, !KS10 BUS DATA BIT 0
1273 PAR_LEFT = 1^4, !PARITY LEFT
1274 PAR_RIGHT = 1^5, !PARITY RIGHT
1275 ADPT4_PE = 1^6, !UNIBUS ADAPTER 4 PARITY ERR
1276 ADPT1_PE = 1^7, !UNIBUS ADAPTER 1 PARITY ERR
1277
1278 !READ REGISTER 300
1279
1280 CONTINUE_H = 1^0, !CONTINUE
1281 EXECUTE_B = 1^1, !EXECUTE
1282 RUN_1 = 1^2, !RUN
1283 HALT_LOOP = 1^3, !DPM HALT LOOP
1284 KLINIK_LEN = 1^4, !KLINIK LENGTH (SW)
1285 KLINIK_BIT = 1^5, !KLINIK BIT # (SW)
1286 CTY_CHAR_LEN = 1^6, !CTY CHARACTER LENGTH (SW)
1287 CTY_BIT = 1^7, !CTY BIT # (SW)
1288
1289 !READ REGISTER 301
1290
1291 DATA_ACK = 1^0, !DATA ACK
1292 BOOT = 1^1, !BOOT (SW)
1293 CONS_ENB = 1^2, !CONSOLE ENABLE (SW)
1294 PE_1 = 1^3, !PE(1)
1295 BUSREQ = 1^4, !BUS REQUEST
1296 NEXM = 1^6, !NEXM
1297 TEN_INT = 1^7, !10 INTERRUPT
1298
1299 !READ REGISTER 302
1300
1301 KLINIK_CARR = 1^0, !KLINIK CARRIER
1302 TERM_CARR = 1^1, !TERMINAL CARRIER
1303 REM_DIAG_ENB = 1^2, !REMOTE DIAG ENB
1304 REM_DIAG_PRO = 1^3, !REMOTE DIAG PROT
1305
1306 !READ REGISTER 303
1307
1308 RAM_ERR = 1^0, !RAM ERROR
1309 DP_CLK_ENBL = 1^1, !DPE/M CLK ENABLE
1310 CR_CLK_ENB = 1^2, !CRA/M CLK ENABLE
1311 R_CLK_ENB0 = 1^3; !R CLK ENB (0) H
1312
1313 ! END OF 'REGBIT.R36'
1314
1315 !
1316 ! MACROS:
1317 !
1318
1319 MACRO
1320 POWER_OF_2(X) = (((X) AND ((X)-1)) EQL 0) %, ! FAMOUS "C" HACK
1321 SINGLE_BIT(X,Y) = POWER_OF_2((X) XOR (Y)) %, ! 1 BIT DIFFERS
1322 IFN = IF 0 NEQ %, ! IF NON-ZERO
1323 N_FLD3 = 0,12 %, ! CRAM # LOW
1324 N_FLD4 = 12,6 %, ! CRAM # HIGH
1325 SET_CRAM_ADR = SETNXT %, ! CONSOLE DISP
1326 LOAD_TST_U = LOADUC(TST_U_ADR,TST_U) %, ! TEST U-CODE
1327 CYCLE(N) = TICK(4 * (N)) %, ! T-CLK: 4 MAINT
1328 V_AC_DP = U_DBUS_DP U_RAM_AC U_FMWRITE %, ! AC0 <-- DP
1329 V_AC_DBM = U_DBUS_DBM U_RAM_AC U_FMWRITE %, ! AC0 <-- DBM
1330 V_D_AC = U_DBUS_RAM U_RAM_AC %, ! D <-- AC0
1331 V_DP_0 = U_A_T1 U_LSRC_0A U_ALU_AND %, ! DP <-- 0
1332 V_DP__1 = U_A_T1 U_B_T1 U_LSRC_AB U_ALU_XNOR %, ! DP <-- -1
1333 V_DP_D = U_LSRC_D0 U_ALU_OR %, ! DP <-- D
1334 V_DP_Q = U_LSRC_0Q U_ALU_OR %, ! DP <-- Q
1335 V_DP_T0 = U_A_T0 U_LSRC_0A U_ALU_OR %, ! DP <-- T0
1336 V_DP_T1 = U_A_T1 U_LSRC_0A U_ALU_OR %, ! DP <-- T1
1337 V_DP_R(X) = U_A(X) U_LSRC_0A U_ALU_OR %, ! DP <-- R(X)
1338 V_SCAD_0 = U_SN(0) U_SCADA_SN U_SCAD_A %, ! SCAD <-- 0
1339 V_SCAD__1 = U_SN(1777) U_SCADA_SN U_SCAD_A %, ! SCAD <-- 1777
1340 V_D_N(N) = U_N(N) U_DBM_N U_DBUS_DBM %, ! D <-- #,,#
1341 V_DP_NN(N) = V_D_N(N) U_LSRC_D0 U_ALU_OR %, ! DP <-- #,,#
1342 V_DP_N(N) = ! DP <-- 0,,#
1343 V_D_N(N) U_A_BRX U_LSRC_0A U_RSRC_D0 U_ALU_OR %,
1344 V_GEN = U_GENR U_GENL %,
1345 V_CHK = U_CHKR U_CHKL %,
1346 ERROR_LOOP(LOOPN) =
1347 DO (ZORK = .ZORK) WHILE %NAME(LOOP,LOOPN): %,
1348 EXIT_LOOP(LOOPN,ERRN) =
1349 IFN LOOP_CHK(ERRN) THEN LEAVE %NAME(LOOP,LOOPN) WITH 1 %,
1350 PAGING_ON =
1351 (SET_CRAM_ADR(PE1_ADR); CP_NOSS(2)) %,
1352 PAGING_OFF =
1353 (SET_CRAM_ADR(PE0_ADR); CP_NOSS(2)) %;
1354
1355 !
1356 ! EQUATED SYMBOLS:
1357 !
1358
1359 GLOBAL BIND
1360 MSGFIL = UPLIT(%SIXBIT 'MSDPM',%SIXBIT 'MSG'),
1361 PRGNAM = UPLIT(%ASCIZ 'KS10 STIMULUS-RESPONSE DIAGNOSTIC FOR THE M8621/DPM BOARD');
1362
1363 GLOBAL LITERAL
1364 TEST_VERSION = 1, ! PDP-10 DIAGNOSTIC-STYLE VERSION #
1365 TEST_EDIT = 2; ! PDP-10 DIAGNOSTIC-STYLE PATCH #
1366
1367 LITERAL
1368 O1777 = %O'1777', ! 10-BIT (SCAD) -1
1369 O1776 = %O'1776', ! 10-BIT (SCAD) -2
1370 O7777 = %O'7777'; ! PAGE-FAIL U-TRAP CRAM ADDR
1371
1372 !
1373 ! OWN STORAGE:
1374 !
1375
1376 OWN
1377 K_MEM, ! MEMORY SIZE IN K-WORDS
1378 MAX_MEM_ADR, ! ADDRESS OF LAST WORD IN MEMORY
1379 MAX_PAG: VECTOR[2], ! LAST PAGE IN MEMORY; COMPLEMENT
1380 INH_CD_RAM: INITIAL(1), ! INHIBIT CACHE DIRECTORY RAM TEST
1381 INH_PT_RAM: INITIAL(1), ! INHIBIT PAGE TABLE RAM TEST
1382 FORCE_MODE: VECTOR[2] ! FORCE EXEC/USER # FIELD 4
1383 INITIAL(%O'20', %O'40'),
1384 FORCE_NAME: VECTOR[2] ! NAME FOR MODE WE GET INTO
1385 INITIAL(UPLIT(%ASCIZ 'EXEC'), UPLIT(%ASCIZ 'USER')),
1386 ERRINFO: VECTOR[15], ! ERROR MESSAGE VARIABLES
1387 ZORK: INITIAL(69); ! KEEP COMPILER HAPPY (DUMMY)
1388
1389 !
1390 ! BUILT-IN FUNCTIONS:
1391 !
1392
1393 BUILTIN
1394 FIRSTONE; ! BLISSIFICATED JFFO
1395
1396 GLOBAL ROUTINE SPEC_DIALOGUE: NOVALUE =
1397
1398 !++
1399 ! FUNCTIONAL DESCRIPTION:
1400 !
1401 ! ONCE-ONLY TEST-SPECIFIC INITIALIZATION DIALOGUE
1402 !
1403 ! FORMAL PARAMETERS:
1404 !
1405 ! NONE
1406 !
1407 ! IMPLICIT INPUTS:
1408 !
1409 ! ASK FOR MEMORY SIZE (IN K-WORDS)
1410 !
1411 ! IMPLICIT OUTPUTS:
1412 !
1413 ! SET K_MEM TO MEMORY SIZE IN K-WORDS
1414 ! SET MAX_MEM_ADR TO ADDRESS OF LAST MEMORY LOCATION
1415 ! SET MAX_PAG[0] TO PAGE NUMBER OF LAST PAGE IN MEMORY
1416 ! SET MAX_PAG[1] TO PAGE NUMBER OF LAST PAGE IN MEMORY
1417 ! WHICH IS THE COMPLEMENT OF MAX_PAG[0]
1418 !
1419 ! ROUTINE VALUE:
1420 !
1421 ! NONE
1422 !
1423 ! SIDE EFFECTS:
1424 !
1425 ! NONE
1426 !
1427 !--
1428
1429 BEGIN
1430
1431 K_MEM = MEMSIZE(); ! ASK USER ABOUT CONFIGURATION
1432 MAX_MEM_ADR = ((.K_MEM - 1) ^ 10) OR 1023;
1433 MAX_PAG[0] = .MAX_MEM_ADR ^ (-9);
1434 MAX_PAG[1] = (NOT .MAX_PAG[0]) AND ((1 ^ (36 - FIRSTONE(.MAX_PAG[0]))) - 1);
1435
1436 END;
1437
1438 GLOBAL ROUTINE SPEC_ASK: NOVALUE =
1439
1440 !++
1441 ! FUNCTIONAL DESCRIPTION:
1442 !
1443 ! SPECIAL-FEATURES-ACTIVATED ASKER
1444 !
1445 ! FORMAL PARAMETERS:
1446 !
1447 ! NONE
1448 !
1449 ! IMPLICIT INPUTS:
1450 !
1451 ! NONE
1452 !
1453 ! IMPLICIT OUTPUTS:
1454 !
1455 ! INH_CD_RAM IS SET IF WE SHOULD INHIBIT CACHE DIRECTORY RAM TEST
1456 ! INH_PT_RAM IS SET IF WE SHOULD INHIBIT PAGE TABLE RAM TEST
1457 !
1458 ! ROUTINE VALUE:
1459 !
1460 ! NONE
1461 !
1462 ! SIDE EFFECTS:
1463 !
1464 ! NONE
1465 !
1466 !--
1467
1468 BEGIN
1469
1470 REGISTER
1471 AC0 = 0;
1472
1473 PRT_TXT_F('INHIBIT CACHE DIRECTORY RAM CONTENTS TESTING? ');
1474 INH_CD_RAM = TTI_YES;
1475
1476 PRT_TXT_F('INHIBIT PAGE TABLE RAM CONTENTS TESTING? ');
1477 INH_PT_RAM = TTI_YES;
1478
1479 END;
1480
1481 GLOBAL ROUTINE SPEC_PRT =
1482
1483 !++
1484 ! FUNCTIONAL DESCRIPTION:
1485 !
1486 ! SPECIAL-FEATURES-ACTIVATED PRINTER
1487 !
1488 ! FORMAL PARAMETERS:
1489 !
1490 ! NONE
1491 !
1492 ! IMPLICIT INPUTS:
1493 !
1494 ! NONE
1495 !
1496 ! IMPLICIT OUTPUTS:
1497 !
1498 ! NONE
1499 !
1500 ! ROUTINE VALUE:
1501 !
1502 ! IT WE DIDN'T PRINT ANYTHING THEN 1 ELSE 0
1503 !
1504 ! SIDE EFFECTS:
1505 !
1506 ! NONE
1507 !
1508 !--
1509
1510 BEGIN
1511
1512 REGISTER
1513 AC0 = 0;
1514
1515 IFN .INH_CD_RAM
1516 THEN
1517 PTXT_CRLF_F('CACHE DIRECTORY RAM CONTENTS TESTING INHIBITED');
1518
1519 IFN .INH_PT_RAM
1520 THEN
1521 PTXT_CRLF_F('PAGE TABLE RAM CONTENTS TESTING INHIBITED');
1522
1523 (.INH_CD_RAM OR .INH_PT_RAM)
1524
1525 END;
1526
1527 !
1528 ! EQUATED SYMBOLS:
1529 !
1530 ! THIS SHOULD BE IN 'TEST_INIT', BUT IS INCLUDED
1531 ! HERE SO THAT THE REST OF THE WORLD WILL SEE IT
1532 !
1533
1534 BIND
1535 SU_ADR = %O'0', ! SU = SERIAL_U
1536 SU = PLIT
1537 (
1538 %(0000)% U_B_T1 V_DP_Q U_DEST_Q_MUL2 U_SKIP_DP0 U,
1539 %(0001)% U_B_T1 V_DP_Q U_DEST_Q_MUL2 U_SKIP_DP0 U
1540 ),
1541 TIU = PLIT
1542 (
1543 %(3700)% U_J(3701) V_DP_0 U_SPEC_LDACBLK U,
1544 %(3701)% U_J(3702) V_DP_0 U_DBUS_DP U_SPEC_LOADIR U,
1545 %(3702)% U_J(3703) V_DP__1 V_AC_DP U,
1546 %(3703)% U_J(3704) V_D_AC V_DP_D U_B_AR U_DEST_AD U,
1547 %(3704)% U_J(3705) U_A_AR U_B_ARX U_LSRC_0A U_ALU_OR U_DEST_AD U,
1548 %(3705)% U_J(3706) U_A_ARX U_B_ARX U_LSRC_AB U_ALU_ADD U_DEST_AD U,
1549 %(3706)% U_J(3707) U_A_ARX U_ALU_XNOR U_LSRC_0A V_AC_DP U,
1550 %(3707)% U_J(3710) V_D_AC V_DP_D U_B_BR U_DEST_AD U,
1551 %(3710)% U_J(3711) V_DP_0 U_B_BRX U_DEST_AD U_SPEC_APR_EN U,
1552 %(3711)% U_J(3712) V_DP_0 U_DBM_N U_N(0) U_SPEC_FLAGS U,
1553 %(3712)% U_J(3713) U_SPEC_CLRCLK U,
1554 %(3713)% U_J(3714) V_DP__1 U_SPEC_LDPI U,
1555 %(3714)% U_J(3714) V_DP_0 U_SPEC_MEMCLR U
1556 ),
1557 TIU_ADR = %O'3700', ! TIU = TEST_INIT_U
1558 TIU_CNT = 18, ! EXTRA CLOCK PULSE NEEDED
1559 ! + 5 MORE TO CLEAR ALLEGED PAGE FAILS?
1560 TIU_MEMCLR = TIU_ADR + %O'14', ! BASMAJI FUCKS WITH THIS
1561 PFU_ADR = %O'3757', ! PFU = PAGE_FAIL_U
1562 PE0_ADR = %O'3761', ! PE0 = PAGING_ENABLE_0
1563 PE1_ADR = %O'3763', ! PE1 = PAGING_ENABLE_1
1564 PFU = PLIT
1565 (
1566 %(3757)% U_J(3760) U_SKIP_INT U, ! FIND REASON FOR PAGE FAIL
1567 %(3760)% U_DBM_PF_DISP U_DBUS_DBM V_DP_D U_DISP_DP_LEFT U,
1568 %(3761)% U_J(3762) V_DP_0 U, ! DISABLE PAGING
1569 %(3762)% V_DP_0 U_SPEC_APR_EN U,
1570 %(3763)% U_J(3764) V_DP_N(10000) U, ! ENABLE PAGING
1571 %(3764)% V_DP_N(10000) U_SPEC_APR_EN U
1572 ),
1573 PHU_ADR = %O'3777', ! PHU = PAGE_HANG_U
1574 PHU = PLIT
1575 (
1576 %(7777)% U_J(7777) U_NO_CLKR U_NO_CLKL U
1577 );
1578
1579 GLOBAL ROUTINE TEST_INIT: NOVALUE =
1580
1581 !++
1582 ! FUNCTIONAL DESCRIPTION:
1583 !
1584 ! ONCE-ONLY INITIALIZATIONS FOR ALL TESTS
1585 !
1586 ! FORMAL PARAMETERS:
1587 !
1588 ! NONE
1589 !
1590 ! IMPLICIT INPUTS:
1591 !
1592 ! NONE
1593 !
1594 ! IMPLICIT OUTPUTS:
1595 !
1596 ! NONE
1597 !
1598 ! ROUTINE VALUE:
1599 !
1600 ! NONE
1601 !
1602 ! SIDE EFFECTS:
1603 !
1604 ! ERROR REPORTING IS ENABLED
1605 ! AN 'MR' (MASTER RESET) IS DONE
1606 ! THE MILLISECOND CLOCK MICRO-INTERRUPT IS DISABLED
1607 ! THE SERIAL & INITIALIZATION MICROCODE IS LOADED
1608 ! AC BLOCK NUMBER = 0
1609 ! IR = 0
1610 ! USER FLAG = 0
1611 ! USER I/O FLAG = 0
1612 ! CLEAR MILLISECOND CLOCK
1613 ! PI LEVEL = 7 (NON-INTERRUPTABLE)
1614 !
1615 ! THE FOLLOWING REGISTERS IN THE 2901 ARE SACRED TO THE WORLD:
1616 ! AR (2901 REG 3) = 3777777777777.0 = -1
1617 ! ((D_INPUT XOR AR) EQL 0) EQV (D_INPUT EQL 777777777777)
1618 ! ARX (2901 REG 4) = 3777777777776.0 = -2
1619 ! ((D_INPUT XOR ARX) EQL 0) EQV (D_INPUT EQL 777777777776)
1620 ! BR (2901 REG 5) = 0000000000001.0 = 1
1621 ! BRX (2901 REG 6) = 0000000000000.0 = 0
1622 !
1623 !--
1624
1625 BEGIN
1626
1627 RPT_ERR_FLAG = 0;
1628 MR(); ! DO A RESET TO RESET MOST OF THE WORLD
1629 WRT212(0); ! CLEAR CSL EXECUTE
1630 TE(0); ! DISABLE MSEC CLK MICRO-INTERRUPTS
1631 CE(0); ! DISABLE CACHE
1632 SEND_NUL(); ! FLUSH IT DOWN THE TUBES (DO IT NOW!)
1633 RPT_ERR_FLAG = 1;
1634 SC_0(); ! TURN OFF SOFT CRAM ERROR RECOVERY
1635 PE(0); ! SET PARITY DETECTION FLAG BITS
1636 ! 1: DP, PAGE TABLE; 2: CRAM; 4: ?
1637 MEM_DEPOSIT(0,6969696969); ! ANYTHING TO GET VALID PARITY IN LOC 0
1638 LOADUC(SU_ADR,SU); ! SHIFT DATA OUT 2901 SIGN-BIT
1639 LOADUC(TIU_ADR,TIU); ! RANDOM INITIALIZATION STUFF
1640 LOADUC(PFU_ADR,PFU); ! PAGE FAULT; DETERMINE CAUSE
1641 LOADUC(PHU_ADR,PHU); ! PAGE FAULT; DIE CONSISTANTLY
1642 SET_CRAM_ADR(TIU_ADR);
1643 CP_NOSS(TIU_CNT);
1644 PAGING_OFF;
1645 SEND_NUL(); ! FLUSH IT DOWN THE TUBES (DO IT NOW!)
1646
1647 END;
1648
1649 ROUTINE PF_DISPATCH =
1650
1651 !++
1652 ! FUNCTIONAL DESCRIPTION:
1653 !
1654 ! DETERMINE CAUSE OF PAGE FAIL
1655 !
1656 ! THE REAL PAGE FAIL DISPATCH DOESN'T WORK -- WE
1657 ! HAVE TO FAKE IT JUST LIKE THE KS10 MICROCODE BY
1658 ! ROUTING THE PAGE FAIL CODE THROUGH THE ADDER
1659 ! AND DISPATCHING ON THE DATA PATH (LEFT)
1660 !
1661 ! FORMAL PARAMETERS:
1662 !
1663 ! NONE
1664 !
1665 ! IMPLICIT INPUTS:
1666 !
1667 ! NONE
1668 !
1669 ! IMPLICIT OUTPUTS:
1670 !
1671 ! NONE
1672 !
1673 ! ROUTINE VALUE:
1674 !
1675 ! PAGE FAIL DISPATCH ADDRESS
1676 !
1677 ! SIDE EFFECTS:
1678 !
1679 ! THE PAGE FAIL DISPATCH MICROCODE IS EXECUTED
1680 !
1681 !--
1682
1683 BEGIN
1684
1685 SET_CRAM_ADR(PFU_ADR);
1686
1687 IF STEP_U_NEXT(1) ! U-CODE SKIP SETS LOW BIT OF CRAM ADDR
1688 THEN
1689 -1 ! INTERRUPT REQUEST
1690 ELSE
1691 STEP_U_NEXT(1) ! SOME OTHER CAUSE
1692
1693 END;
1694
1695 ROUTINE PF_TRAP =
1696
1697 !++
1698 ! FUNCTIONAL DESCRIPTION:
1699 !
1700 ! DETERMINE CAUSE OF, AND REINITIALIZE AFTER, PAGE FAIL
1701 !
1702 ! FORMAL PARAMETERS:
1703 !
1704 ! NONE
1705 !
1706 ! IMPLICIT INPUTS:
1707 !
1708 ! NONE
1709 !
1710 ! IMPLICIT OUTPUTS:
1711 !
1712 ! NONE
1713 !
1714 ! ROUTINE VALUE:
1715 !
1716 ! PAGE FAIL DISPATCH ADDRESS
1717 !
1718 ! SIDE EFFECTS:
1719 !
1720 ! AN 'MR' (MASTER RESET) IS DONE
1721 ! THE 'TEST_INIT' MICROCODE IS REEXECUTED
1722 !
1723 !--
1724
1725 BEGIN
1726
1727 LOCAL
1728 PF_CAUSE;
1729
1730 PF_CAUSE = PF_DISPATCH(); ! FIND OUT WHY IT HAPPENED
1731 MR(); ! DO A RESET TO RESET MOST OF THE WORLD
1732 SET_CRAM_ADR(TIU_ADR); ! AND DO ALL OF THE OTHER CRAP AGAIN
1733 CP_NOSS(TIU_CNT);
1734 SEND_NUL(); ! FLUSH IT DOWN THE TUBES (DO IT NOW!)
1735
1736 .PF_CAUSE
1737
1738 END;
1739
1740 ROUTINE PF_NAME(PF_CAUSE) =
1741
1742 !++
1743 ! FUNCTIONAL DESCRIPTION:
1744 !
1745 ! TRANSLATE PAGE FAIL DISPATCH TO A MEANINGFUL STRING
1746 !
1747 ! FORMAL PARAMETERS:
1748 !
1749 ! NONE
1750 !
1751 ! IMPLICIT INPUTS:
1752 !
1753 ! NONE
1754 !
1755 ! IMPLICIT OUTPUTS:
1756 !
1757 ! NONE
1758 !
1759 ! ROUTINE VALUE:
1760 !
1761 ! ADDRESS OF ASCIZ STRING DESCRIBING PAGE FAIL CAUSE
1762 ! SEE KS10 U-CODE AT LABEL 'PFD' (SEQUENCE 7968)
1763 !
1764 ! SIDE EFFECTS:
1765 !
1766 ! NONE
1767 !
1768 !--
1769
1770 BEGIN
1771
1772 CASE .PF_CAUSE FROM -1 TO %O'17' OF
1773 SET
1774 [-1]: UPLIT(%ASCIZ 'INTERRUPT REQUEST');
1775 [%O'01']: UPLIT(%ASCIZ 'INTERRUPT OR TIMEOUT');
1776 [%O'03']: UPLIT(%ASCIZ 'BAD DATA');
1777 [%O'05']: UPLIT(%ASCIZ 'NXM ERROR');
1778 [%O'07']: UPLIT(%ASCIZ 'NXM AND BAD DATA');
1779 [%O'10']: UPLIT(%ASCIZ 'WRITE VIOLATION');
1780 [%O'11']: UPLIT(%ASCIZ 'NO PAGE FAIL OCCURED');
1781 [%O'12']: UPLIT(%ASCIZ 'PAGE NOT VALID');
1782 [%O'13']: UPLIT(%ASCIZ 'EXEC/USER MISMATCH');
1783 [INRANGE]: UPLIT(%ASCIZ 'UNKNOWN PAGE FAIL DISPATCH');
1784 [OUTRANGE]: UPLIT(%ASCIZ 'INVALID PAGE FAIL DISPATCH');
1785 TES
1786
1787 END;
1788
1789 ROUTINE SERIAL( %( SKIP_COUNT, )% EXAMINE_COUNT) =
1790
1791 !++
1792 ! FUNCTIONAL DESCRIPTION:
1793 !
1794 ! SHIFT Q LEFT 2+SKIP_COUNT BITS TO GET BIT #SKIP_COUNT IN 2901 SIGN.
1795 ! SHIFT Q LEFT EXAMINE_COUNT TIMES, CHECKING THE SIGN BIT
1796 ! AND RECONSTRUCTING THE VALUE.
1797 !
1798 ! FORMAL PARAMETERS:
1799 !
1800 ! EXAMINE_COUNT IS THE NUMBER OF BITS IN THE FIELD WE WANT
1801 !
1802 ! IMPLICIT INPUTS:
1803 !
1804 ! CRAM ADDRESS SHOULD BE AT 0
1805 ! THE NUMBER WE WANT IS IN Q
1806 !
1807 ! IMPLICIT OUTPUTS:
1808 !
1809 ! NONE
1810 !
1811 ! ROUTINE VALUE:
1812 !
1813 ! THE FIELD THAT WAS IN Q, RIGHT JUSTIFIED
1814 !
1815 ! SIDE EFFECTS:
1816 !
1817 ! Q IS MUNGED UP
1818 !
1819 !--
1820
1821 BEGIN
1822
1823 LOCAL
1824 Q_REG;
1825
1826 Q_REG = 0;
1827 CP_NOSS(2 %( + .SKIP_COUNT )% );
1828 INCR Q_BIT_NUMBER FROM 1 TO .EXAMINE_COUNT DO
1829 Q_REG = (.Q_REG^1) OR STEP_U_NEXT(1);
1830
1831 .Q_REG
1832
1833 END;
1834
1835 ROUTINE SCAD_Q =
1836
1837 !++
1838 ! FUNCTIONAL DESCRIPTION:
1839 !
1840 ! USE SERIAL TO GET THE VALUE OF Q AND PICK THE SCAD
1841 ! VALUE OUT OF THE HIGH HALF AND REARRANGE THE BITS.
1842 !
1843 ! FORMAL PARAMETERS:
1844 !
1845 ! NONE
1846 !
1847 ! IMPLICIT INPUTS:
1848 !
1849 ! THE OUTPUT OF THE SCAD HAS BEEN LOADED INTO Q
1850 !
1851 ! IMPLICIT OUTPUTS:
1852 !
1853 ! NONE
1854 !
1855 ! ROUTINE VALUE:
1856 !
1857 ! VALUE OF THE OUTPUT OF THE SCAD THAT WAS IN Q
1858 !
1859 ! SIDE EFFECTS:
1860 !
1861 ! NONE
1862 !
1863 !--
1864
1865 BEGIN
1866
1867 LOCAL
1868 CEREAL_VAL,
1869 SCAD_VAL;
1870
1871 CEREAL_VAL = SERIAL(18);
1872 SCAD_VAL = 0;
1873 SCAD_VAL<9,1> = .CEREAL_VAL<0,1>;
1874 SCAD_VAL<0,9> = .CEREAL_VAL<9,9>;
1875
1876 .SCAD_VAL
1877
1878 END;
1879
1880 GLOBAL ROUTINE TST1: NOVALUE =
1881
1882 !++
1883 ! FUNCTIONAL DESCRIPTION:
1884 !
1885 ! PASS 0 THRU THE #,,# INPUT TO DBM MUX
1886 ! PASS -1 THRU THE #,,# INPUT TO DBM MUX
1887 !
1888 !--
1889
1890 BEGIN
1891
1892 MACRO
1893 INFO_TUA = 0,0,36,0 %,
1894 INFO_CP = 1,0,36,0 %,
1895 INFO_COR = 2,0,36,0 %;
1896
1897 LOCAL
1898 OK,
1899 COR,
1900 ACT;
1901
1902 LABEL
1903 LOOP1,
1904 LOOP2;
1905
1906 BIND
1907 TST_U_ADR = %O'4',
1908 TST_U = PLIT
1909 (
1910 %(0004)% U_N(0) U_DBM_N U_DBUS_DBM V_DP_D U_DEST_Q_AD U_SKIP_ADEQ0 U,
1911 %(0005)% U_J(6) U_N(777777) U_DBM_N U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
1912 %(0006)% U_A_AR U_LSRC_AQ U_ALU_XOR U_SKIP_ADEQ0 U
1913 ),
1914 TUA_0 = TST_U_ADR + 0,
1915 TUA_1 = TST_U_ADR + 1;
1916
1917 OWN
1918 INFO: BLOCKVECTOR[2,3] INITIAL
1919 (
1920 TUA_0, 1, 0,
1921 TUA_1, 2, -1
1922 );
1923
1924 OK = 1;
1925 LOAD_TST_U;
1926
1927 INCR SUBTEST FROM 0 TO 1 DO
1928 ERROR_LOOP(1)
1929 (
1930 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
1931 IF STEP_U_NEXT(.INFO[.SUBTEST,INFO_CP]) EQL 0
1932 THEN
1933 (
1934 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
1935 ACT = SERIAL(36);
1936 ERRCAS
1937 (
1938 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
1939 1,.COR,.ACT,12,ERRINFO
1940 );
1941 OK = 0;
1942 );
1943 EXIT_LOOP(1,1);
1944 EXIT_LOOP(1,2);
1945 0
1946 );
1947
1948 IFN .OK
1949 THEN
1950 (
1951 NOERR(1);
1952 NOERR(2);
1953 );
1954
1955 !*MESSAGE 1
1956 !*STIMULUS:
1957 !* LOAD \O0 FROM #-FIELD THRU DBM MUX
1958 !*RESPONSE:
1959 !* OUTPUT OF DBM MUX SHOULD BE \O0
1960
1961 !]ERROR 1
1962 !]DBM_N NTWK
1963
1964 !]NO ERROR 1
1965 !]DBM_N NTWK
1966
1967 !]ERROR 2
1968 !]DBM_SEL_N NTWK
1969
1970 !]NO ERROR 2
1971 !]DBM_SEL_N NTWK
1972
1973 END;
1974
1975 GLOBAL ROUTINE TST2: NOVALUE =
1976
1977 !++
1978 ! FUNCTIONAL DESCRIPTION:
1979 !
1980 ! PASS 0 THRU THE DP-SWAPPED INPUT TO DBM MUX
1981 ! PASS -1 THRU THE DP-SWAPPED INPUT TO DBM MUX
1982 !
1983 !--
1984
1985 BEGIN
1986
1987 MACRO
1988 INFO_TUA = 0,0,36,0 %,
1989 INFO_CP = 1,0,36,0 %,
1990 INFO_COR = 2,0,36,0 %;
1991
1992 LOCAL
1993 OK,
1994 COR,
1995 ACT;
1996
1997 LABEL
1998 LOOP1,
1999 LOOP2;
2000
2001 BIND
2002 TST_U_ADR = %O'13',
2003 TST_U = PLIT
2004 (
2005 %(0013)% U_J(14) V_DP_0 U_DBM_DP_SWAP V_AC_DBM U,
2006 %(0014)% V_D_AC V_DP_D U_DEST_Q_AD U_SKIP_ADEQ0 U,
2007 %(0015)% U_J(16) V_DP__1 U_DBM_DP_SWAP V_AC_DBM U,
2008 %(0016)% U_J(17) V_D_AC V_DP_D U_DEST_Q_AD U,
2009 %(0017)% U_ALU_XOR U_LSRC_AQ U_A_AR U_SKIP_ADEQ0 U
2010 ),
2011 TUA_0 = TST_U_ADR + 0,
2012 TUA_1 = TST_U_ADR + 2;
2013
2014 OWN
2015 INFO: BLOCKVECTOR[2,3] INITIAL
2016 (
2017 TUA_0, 2, 0,
2018 TUA_1, 3, -1
2019 );
2020
2021 OK = 1;
2022 LOAD_TST_U;
2023
2024 INCR SUBTEST FROM 0 TO 1 DO
2025 ERROR_LOOP(1)
2026 (
2027 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
2028 IF STEP_U_NEXT(.INFO[.SUBTEST,INFO_CP]) EQL 0
2029 THEN
2030 (
2031 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
2032 ACT = SERIAL(36);
2033 ERRCAS
2034 (
2035 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
2036 1,.COR,.ACT,12,ERRINFO
2037 );
2038 OK = 0;
2039 );
2040 EXIT_LOOP(1,1);
2041 EXIT_LOOP(1,2);
2042 0
2043 );
2044
2045 IFN .OK
2046 THEN
2047 (
2048 NOERR(1);
2049 NOERR(2);
2050 );
2051
2052 !*MESSAGE 1
2053 !*STIMULUS:
2054 !* LOAD \O0 ONTO DP-SWAPPED AND THRU DBM MUX
2055 !*RESPONSE:
2056 !* OUTPUT OF DBM MUX SHOULD BE \O0
2057
2058 !]ERROR 1
2059 !]DBM_DP_SWAP NTWK
2060
2061 !]NO ERROR 1
2062 !]DBM_DP_SWAP NTWK
2063
2064 !]ERROR 2
2065 !]DBM_SEL_DP_SWAP NTWK
2066
2067 !]NO ERROR 2
2068 !]DBM_SEL_DP_SWAP NTWK
2069
2070 END;
2071
2072 GLOBAL ROUTINE TST3: NOVALUE =
2073
2074 !++
2075 ! FUNCTIONAL DESCRIPTION:
2076 !
2077 ! PASS 0 THRU THE DP INPUT TO DBM MUX
2078 ! PASS -1 THRU THE DP INPUT TO DBM MUX
2079 !
2080 !--
2081
2082 BEGIN
2083
2084 MACRO
2085 INFO_TUA = 0,0,36,0 %,
2086 INFO_CP = 1,0,36,0 %,
2087 INFO_COR = 2,0,36,0 %;
2088
2089 LOCAL
2090 OK,
2091 COR,
2092 ACT;
2093
2094 LABEL
2095 LOOP1,
2096 LOOP2;
2097
2098 BIND
2099 TST_U_ADR = %O'26',
2100 TST_U = PLIT
2101 (
2102 %(0026)% U_J(27) V_DP_0 U_DBM_DP V_AC_DBM U,
2103 %(0027)% V_D_AC V_DP_D U_DEST_Q_AD U_SKIP_ADEQ0 U,
2104 %(0030)% U_J(31) V_DP__1 U_DBM_DP_SWAP V_AC_DBM U,
2105 %(0031)% U_J(32) V_D_AC V_DP_D U_DEST_Q_AD U,
2106 %(0032)% U_ALU_XOR U_LSRC_AQ U_A_AR U_SKIP_ADEQ0 U
2107 ),
2108 TUA_0 = TST_U_ADR + 0,
2109 TUA_1 = TST_U_ADR + 2;
2110
2111 OWN
2112 INFO: BLOCKVECTOR[2,3] INITIAL
2113 (
2114 TUA_0, 2, 0,
2115 TUA_1, 3, -1
2116 );
2117
2118 OK = 1;
2119 LOAD_TST_U;
2120
2121 INCR SUBTEST FROM 0 TO 1 DO
2122 ERROR_LOOP(1)
2123 (
2124 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
2125 IF STEP_U_NEXT(.INFO[.SUBTEST,INFO_CP]) EQL 0
2126 THEN
2127 (
2128 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
2129 ACT = SERIAL(36);
2130 ERRCAS
2131 (
2132 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
2133 1,.COR,.ACT,12,ERRINFO
2134 );
2135 OK = 0;
2136 );
2137 EXIT_LOOP(1,1);
2138 EXIT_LOOP(1,2);
2139 0
2140 );
2141
2142 IFN .OK
2143 THEN
2144 (
2145 NOERR(1);
2146 NOERR(2);
2147 );
2148
2149 !*MESSAGE 1
2150 !*STIMULUS:
2151 !* LOAD \O0 ONTO DP AND THRU DBM MUX
2152 !*RESPONSE:
2153 !* OUTPUT OF DBM MUX SHOULD BE \O0
2154
2155 !]ERROR 1
2156 !]DBM_DP NTWK
2157
2158 !]NO ERROR 1
2159 !]DBM_DP NTWK
2160
2161 !]ERROR 2
2162 !]DBM_SEL_DP NTWK
2163
2164 !]NO ERROR 2
2165 !]DBM_SEL_DP NTWK
2166
2167 END;
2168
2169 GLOBAL ROUTINE TST4: NOVALUE =
2170
2171 !++
2172 ! FUNCTIONAL DESCRIPTION:
2173 !
2174 ! PASS 0 FROM SCAD # THRU A-MUX TO Q
2175 ! PASS 1777 FROM SCAD # THRU A-MUX TO Q
2176 !
2177 !--
2178
2179 BEGIN
2180
2181 MACRO
2182 INFO_TUA = 0,0,36,0 %,
2183 INFO_CP = 1,0,36,0 %,
2184 INFO_COR = 2,0,36,0 %;
2185
2186 LOCAL
2187 OK,
2188 COR,
2189 ACT;
2190
2191 LABEL
2192 LOOP1,
2193 LOOP2;
2194
2195 BIND
2196 TST_U_ADR = %O'37',
2197 TST_U = PLIT
2198 (
2199 %(0037)% V_SCAD_0 U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
2200 %(0040)% V_SCAD__1 U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U
2201 ),
2202 TUA_0 = TST_U_ADR + 0,
2203 TUA_1 = TST_U_ADR + 1;
2204
2205 OWN
2206 INFO: BLOCKVECTOR[2,3] INITIAL
2207 (
2208 TUA_0, 1, 0,
2209 TUA_1, 1, O1777
2210 );
2211
2212 OK = 1;
2213 LOAD_TST_U;
2214
2215 INCR SUBTEST FROM 0 TO 1 DO
2216 ERROR_LOOP(1)
2217 (
2218 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
2219 CP(.INFO[.SUBTEST,INFO_CP]);
2220 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
2221 ACT = SCAD_Q();
2222 IF .COR NEQ .ACT
2223 THEN
2224 (
2225 ERRCAS
2226 (
2227 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
2228 1,.COR,.ACT,12,ERRINFO
2229 );
2230 OK = 0;
2231 );
2232 EXIT_LOOP(1,1);
2233 EXIT_LOOP(1,2);
2234 0
2235 );
2236
2237 IFN .OK
2238 THEN
2239 (
2240 NOERR(1);
2241 NOERR(2);
2242 );
2243
2244 !*MESSAGE 1
2245 !*STIMULUS:
2246 !* PASS \O0 FROM # THRU SCAD A-MUX AND SCAD
2247 !*RESPONSE:
2248 !* OUTPUT OF SCAD SHOULD BE \O0
2249
2250 !]ERROR 1
2251 !]SCAD_A SCADA_SN DBM_SCAD NTWK
2252
2253 !]NO ERROR 1
2254 !]SCAD_A SCADA_SN DBM_SCAD NTWK
2255
2256 !]ERROR 2
2257 !]SCAD_A SCADA_SEL_SN DBM_SEL_SCAD NTWK
2258
2259 !]NO ERROR 2
2260 !]SCAD_A SCADA_SEL_SN DBM_SEL_SCAD NTWK
2261
2262 END;
2263
2264 GLOBAL ROUTINE TST5: NOVALUE =
2265
2266 !++
2267 ! FUNCTIONAL DESCRIPTION:
2268 !
2269 ! PASS 0 FROM SCAD # TO A-MUX TO SCAD AND DECREMENT
2270 ! PASS 1 FROM SCAD # TO A-MUX TO SCAD AND DECREMENT
2271 ! PASS 1777 FROM SCAD # TO A-MUX TO SCAD AND DECREMENT
2272 !
2273 !--
2274
2275 BEGIN
2276
2277 MACRO
2278 INFO_N = 0,0,36,0 %,
2279 INFO_COR = 1,0,36,0 %;
2280
2281 LOCAL
2282 OK,
2283 COR,
2284 ACT;
2285
2286 LABEL
2287 LOOP1;
2288
2289 BIND
2290 TST_U_ADR = %O'41',
2291 TST_U = PLIT
2292 (
2293 %(0041)% U_SN(0) U_SCADA_SN U_SCAD_A_DEC U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
2294 %(0042)% U_SN(1) U_SCADA_SN U_SCAD_A_DEC U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
2295 %(0043)% U_SN(1777) U_SCADA_SN U_SCAD_A_DEC U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U
2296 );
2297
2298 OWN
2299 INFO: BLOCKVECTOR[3,2] INITIAL
2300 (
2301 0, O1777,
2302 1, 0,
2303 O1777, O1776
2304 );
2305
2306 LOAD_TST_U;
2307 OK = 1;
2308
2309 INCR SUBTEST FROM 0 TO 2 DO
2310 ERROR_LOOP(1)
2311 (
2312 ERRINFO[0] = .INFO[.SUBTEST,INFO_N];
2313 ERRINFO[1] = COR = .INFO[.SUBTEST,INFO_COR];
2314 SET_CRAM_ADR(TST_U_ADR + .SUBTEST);
2315 CP(1);
2316 ACT = SCAD_Q();
2317 IF .ACT NEQ .COR
2318 THEN
2319 (
2320 ERRCAS(1,1,.COR,.ACT,4,ERRINFO);
2321 OK = 0;
2322 );
2323 EXIT_LOOP(1,1);
2324 0
2325 );
2326
2327 IFN .OK THEN NOERR(1);
2328
2329 !*MESSAGE 1
2330 !*STIMULUS:
2331 !* PASS \O0 FROM # TO SCAD AND DECREMENT
2332 !*RESPONSE:
2333 !* OUTPUT OF SCAD SHOULD BE \O1
2334
2335 !]ERROR 1
2336 !]SCAD_A_DEC SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK
2337
2338 !]NO ERROR 1
2339 !]SCAD_A_DEC SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK
2340
2341 END;
2342
2343 GLOBAL ROUTINE TST6: NOVALUE =
2344
2345 !++
2346 ! FUNCTIONAL DESCRIPTION:
2347 !
2348 ! PASS 0 FROM SCAD # TO A-MUX TO SCAD AND DOUBLE
2349 ! PASS 1777 FROM SCAD # TO A-MUX TO SCAD AND DOUBLE
2350 !
2351 !--
2352
2353 BEGIN
2354
2355 MACRO
2356 INFO_N = 0,0,36,0 %,
2357 INFO_COR = 1,0,36,0 %;
2358
2359 LOCAL
2360 OK,
2361 COR,
2362 ACT;
2363
2364 LABEL
2365 LOOP1;
2366
2367 BIND
2368 TST_U_ADR = %O'44',
2369 TST_U = PLIT
2370 (
2371 %(0044)% U_SN(0) U_SCADA_SN U_SCAD_A_MUL2 U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
2372 %(0045)% U_SN(1777) U_SCADA_SN U_SCAD_A_MUL2 U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U
2373 );
2374
2375 OWN
2376 INFO: BLOCKVECTOR[2,2] INITIAL
2377 (
2378 0, 0,
2379 O1777, O1776
2380 );
2381
2382 LOAD_TST_U;
2383 OK = 1;
2384
2385 INCR SUBTEST FROM 0 TO 1 DO
2386 ERROR_LOOP(1)
2387 (
2388 ERRINFO[0] = .INFO[.SUBTEST,INFO_COR];
2389 ERRINFO[1] = COR = .INFO[.SUBTEST,INFO_COR];
2390 SET_CRAM_ADR(TST_U_ADR + .SUBTEST);
2391 CP(1);
2392 ACT = SCAD_Q();
2393 IF .ACT NEQ .COR
2394 THEN
2395 (
2396 ERRCAS(1,1,.COR,.ACT,4,ERRINFO);
2397 OK = 0;
2398 );
2399 EXIT_LOOP(1,1);
2400 0
2401 );
2402
2403 IFN .OK THEN NOERR(1);
2404
2405 !*MESSAGE 1
2406 !*STIMULUS:
2407 !* PASS \O0 FROM # TO SCAD AND DOUBLE
2408 !*RESPONSE:
2409 !* OUTPUT OF SCAD SHOULD BE \O1
2410
2411 !]ERROR 1
2412 !]SCAD_A_MUL2 SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK
2413
2414 !]NO ERROR 1
2415 !]SCAD_A_MUL2 SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK
2416
2417 END;
2418
2419 GLOBAL ROUTINE TST7: NOVALUE =
2420
2421 !++
2422 ! FUNCTIONAL DESCRIPTION:
2423 !
2424 ! LOAD 0 INTO SC, THEN PASS IT THRU SCAD
2425 ! LOAD 1777 INTO SC, THEN PASS IT THRU SCAD
2426 !
2427 !--
2428
2429 BEGIN
2430
2431 MACRO
2432 INFO_TUA = 0,0,36,0 %,
2433 INFO_COR = 1,0,36,0 %;
2434
2435 LOCAL
2436 OK,
2437 COR,
2438 ACT;
2439
2440 LABEL
2441 LOOP1;
2442
2443 BIND
2444 TST_U_ADR = %O'46',
2445 TST_U = PLIT
2446 (
2447 %(0046)% U_J(50) V_SCAD_0 U_LOADSC U,
2448 %(0047)% U_J(50) V_SCAD__1 U_LOADSC U,
2449 %(0050)% U_SCADA_SC U_SCAD_A U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U
2450 ),
2451 TUA_0 = TST_U_ADR + 0,
2452 TUA_1 = TST_U_ADR + 1;
2453
2454 OWN
2455 INFO: BLOCKVECTOR[2,2] INITIAL
2456 (
2457 TUA_0, 0,
2458 TUA_1, O1777
2459 );
2460
2461 OK = 1;
2462 LOAD_TST_U;
2463
2464 INCR SUBTEST FROM 0 TO 1 DO
2465 ERROR_LOOP(1)
2466 (
2467 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
2468 CP(2);
2469 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
2470 ACT = SCAD_Q();
2471 IF .COR NEQ .ACT
2472 THEN
2473 (
2474 ERRCAS
2475 (
2476 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
2477 1,.COR,.ACT,4,ERRINFO ! VERSION 1.1
2478 );
2479 OK = 0;
2480 );
2481 EXIT_LOOP(1,1);
2482 EXIT_LOOP(1,2);
2483 0
2484 );
2485
2486 IFN .OK
2487 THEN
2488 (
2489 NOERR(1);
2490 NOERR(2);
2491 );
2492
2493 !*MESSAGE 1
2494 !*STIMULUS:
2495 !* LOAD \O0 INTO SC, THEN PASS IT THRU SCAD
2496 !*RESPONSE:
2497 !* OUTPUT OF SCAD SHOULD BE \O0
2498
2499 !]ERROR 1
2500 !]SCAD_A SC SCADA_SC SCADA_SN DBM_SCAD NTWK
2501
2502 !]NO ERROR 1
2503 !]SCAD_A SC SCADA_SC SCADA_SN DBM_SCAD NTWK
2504
2505 !]ERROR 2
2506 !]SCAD_A SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK
2507
2508 !]NO ERROR 2
2509 !]SCAD_A SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK
2510
2511 END;
2512
2513 GLOBAL ROUTINE TST8: NOVALUE =
2514
2515 !++
2516 ! FUNCTIONAL DESCRIPTION:
2517 !
2518 ! PASS 44 FROM SCADA TO Q WITH 0 ON DP, 0 IN SC
2519 ! PASS 44 FROM SCADA TO Q WITH -1 ON DP, 1777 IN SC
2520 !
2521 !--
2522
2523 BEGIN
2524
2525 MACRO
2526 INFO_TUA = 0,0,36,0 %,
2527 INFO_COR = 1,0,36,0 %,
2528 INFO_DP = 2,0,36,0 %,
2529 INFO_SC = 3,0,36,0 %;
2530
2531 LOCAL
2532 OK,
2533 COR,
2534 ACT;
2535
2536 LABEL
2537 LOOP1;
2538
2539 BIND
2540 TST_U_ADR = %O'54',
2541 TST_U = PLIT
2542 (
2543 %(0054)% U_J(55) V_SCAD_0 U_LOADSC U,
2544 %(0055)% U_J(60) V_DP_0 U_SCADA_PTR44 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2545 %(0056)% U_J(57) V_SCAD__1 U_LOADSC U,
2546 %(0057)% U_J(60) V_DP__1 U_SCADA_PTR44 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2547 %(0060)% V_D_AC V_DP_D U_DEST_Q_AD U
2548 ),
2549 TUA_0 = TST_U_ADR + 0,
2550 TUA_1 = TST_U_ADR + 2;
2551
2552 OWN
2553 INFO: BLOCKVECTOR[2,4] INITIAL
2554 (
2555 TUA_0, %O'0440', 0, 0,
2556 TUA_1, %O'1447', -1, O1777
2557 );
2558
2559 OK = 1;
2560 LOAD_TST_U;
2561
2562 INCR SUBTEST FROM 0 TO 1 DO
2563 ERROR_LOOP(1)
2564 (
2565 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
2566 CP(3);
2567 ERRINFO[1] = .INFO[.SUBTEST,INFO_DP];
2568 ERRINFO[2] = .INFO[.SUBTEST,INFO_SC];
2569 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
2570 ACT = SCAD_Q();
2571 IF .COR NEQ .ACT
2572 THEN
2573 (
2574 ERRCAS
2575 (
2576 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
2577 1,.COR,.ACT,4,ERRINFO ! VERSION 1.1
2578 );
2579 OK = 0;
2580 );
2581 EXIT_LOOP(1,1);
2582 EXIT_LOOP(1,2);
2583 0
2584 );
2585
2586 IFN .OK
2587 THEN
2588 (
2589 NOERR(1);
2590 NOERR(2);
2591 );
2592
2593 !*MESSAGE 1
2594 !*STIMULUS:
2595 !* GET POINTER 44 FROM SCADA WITH \O1 ON DP, \O2 IN SC
2596 !*RESPONSE:
2597 !* OUTPUT OF SCAD SHOULD BE \O0
2598
2599 !]ERROR 1
2600 !]SCAD_A SCADA_44 SC SCADA_SC SCADA_SN DBM_SCAD NTWK
2601
2602 !]NO ERROR 1
2603 !]SCAD_A SCADA_44 SC SCADA_SC SCADA_SN DBM_SCAD NTWK
2604
2605 !]ERROR 2
2606 !]SCAD_A SCADA_SEL_44 SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK
2607
2608 !]NO ERROR 2
2609 !]SCAD_A SCADA_SEL_44 SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK
2610
2611 END;
2612
2613 GLOBAL ROUTINE TST9: NOVALUE =
2614
2615 !++
2616 ! FUNCTIONAL DESCRIPTION:
2617 !
2618 ! PASS 0 ON DP THRU SCADA BYTES
2619 ! PASS -1 ON DP THRU SCADA BYTES
2620 !
2621 !--
2622
2623 BEGIN
2624
2625 MACRO
2626 INFO_TUA = 0,0,36,0 %,
2627 INFO_DP = 1,0,36,0 %,
2628 INFO_COR = 2,0,36,0 %;
2629
2630 LOCAL
2631 OK,
2632 COR,
2633 ACT,
2634 COR_BYTE,
2635 ACT_BYTE,
2636 COR_PTR,
2637 ACT_PTR;
2638
2639 LABEL
2640 LOOP1;
2641
2642 BIND
2643 TST_U_ADR = %O'63',
2644 TST_U = PLIT
2645 (
2646 %(0063)% U_J(75) V_DP_0 U_SCADA_BYTE5 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2647 %(0064)% U_J(75) V_DP_0 U_SCADA_BYTE4 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2648 %(0065)% U_J(75) V_DP_0 U_SCADA_BYTE3 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2649 %(0066)% U_J(75) V_DP_0 U_SCADA_BYTE2 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2650 %(0067)% U_J(75) V_DP_0 U_SCADA_BYTE1 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2651 %(0070)% U_J(75) V_DP__1 U_SCADA_BYTE5 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2652 %(0071)% U_J(75) V_DP__1 U_SCADA_BYTE4 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2653 %(0072)% U_J(75) V_DP__1 U_SCADA_BYTE3 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2654 %(0073)% U_J(75) V_DP__1 U_SCADA_BYTE2 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2655 %(0074)% U_J(75) V_DP__1 U_SCADA_BYTE1 U_SCAD_A U_DBM_SCAD V_AC_DBM U,
2656 %(0075)% V_D_AC V_DP_D U_DEST_Q_AD U
2657 ),
2658 TUA_0 = TST_U_ADR + 0,
2659 TUA_1 = TST_U_ADR + 5;
2660
2661 OWN
2662 INFO: BLOCKVECTOR[2,3] INITIAL
2663 (
2664 TUA_0, 0, 0,
2665 TUA_1, -1, -2
2666 );
2667
2668 OK = 1;
2669 LOAD_TST_U;
2670
2671 INCR SUBTEST FROM 0 TO 1 DO
2672 ERROR_LOOP(1)
2673 (
2674 ERRINFO[1] = .INFO[.SUBTEST,INFO_DP];
2675 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
2676 ACT = 0;
2677 ACT_PTR = POINT(ACT,36,7);
2678 INCR BYTE_NUMBER FROM 0 TO 4 DO
2679 (
2680 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA] + .BYTE_NUMBER);
2681 CP(2);
2682 REPLACEI(ACT_PTR,SERIAL(7));
2683 );
2684 IF .ACT NEQ .COR
2685 THEN
2686 (
2687 ERMCAS(1,.COR,.ACT,12,ERRINFO);
2688 OK = 0;
2689 COR_PTR = POINT(COR,36,7);
2690 ACT_PTR = POINT(ACT,36,7);
2691 INCR BYTE_NUMBER FROM 0 TO 4 DO
2692 (
2693 COR_BYTE = SCANI(COR_PTR);
2694 ACT_BYTE = SCANI(ACT_PTR);
2695 FAILURE(.BYTE_NUMBER*2+SINGLE_BIT(.COR_BYTE,.ACT_BYTE)+1);
2696 );
2697 );
2698 EXIT_LOOP(1,1);
2699 0
2700 );
2701
2702 IFN .OK THEN INCR I FROM 1 TO 10 DO NOERR(.I);
2703
2704 !*MESSAGE 1
2705 !*STIMULUS:
2706 !* PUT \O1 ON DP AND PICK UP EACH BYTE FROM SCADA
2707 !*RESPONSE:
2708 !* WORD REBUILT FROM 5 BYTES SHOULD BE \O0
2709
2710 !]ERROR 1
2711 !]SCAD_A SCADA_44 SCADA_BYTE1 DBM_SCAD NTWK
2712
2713 !]NO ERROR 1
2714 !]SCAD_A SCADA_44 SCADA_BYTE1 DBM_SCAD NTWK
2715
2716 !]ERROR 2
2717 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE1 DBM_SEL_SCAD NTWK
2718
2719 !]NO ERROR 2
2720 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE1 DBM_SEL_SCAD NTWK
2721
2722 !]ERROR 3
2723 !]SCAD_A SCADA_44 SCADA_BYTE2 DBM_SCAD NTWK
2724
2725 !]NO ERROR 3
2726 !]SCAD_A SCADA_44 SCADA_BYTE2 DBM_SCAD NTWK
2727
2728 !]ERROR 4
2729 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE2 DBM_SEL_SCAD NTWK
2730
2731 !]NO ERROR 4
2732 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE2 DBM_SEL_SCAD NTWK
2733
2734 !]ERROR 5
2735 !]SCAD_A SCADA_44 SCADA_BYTE3 DBM_SCAD NTWK
2736
2737 !]NO ERROR 5
2738 !]SCAD_A SCADA_44 SCADA_BYTE3 DBM_SCAD NTWK
2739
2740 !]ERROR 6
2741 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE3 DBM_SEL_SCAD NTWK
2742
2743 !]NO ERROR 6
2744 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE3 DBM_SEL_SCAD NTWK
2745
2746 !]ERROR 7
2747 !]SCAD_A SCADA_44 SCADA_BYTE4 DBM_SCAD NTWK
2748
2749 !]NO ERROR 7
2750 !]SCAD_A SCADA_44 SCADA_BYTE4 DBM_SCAD NTWK
2751
2752 !]ERROR 8
2753 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE4 DBM_SEL_SCAD NTWK
2754
2755 !]NO ERROR 8
2756 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE4 DBM_SEL_SCAD NTWK
2757
2758 !]ERROR 9
2759 !]SCAD_A SCADA_44 SCADA_BYTE5 DBM_SCAD NTWK
2760
2761 !]NO ERROR 9
2762 !]SCAD_A SCADA_44 SCADA_BYTE5 DBM_SCAD NTWK
2763
2764 !]ERROR 10
2765 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE5 DBM_SEL_SCAD NTWK
2766
2767 !]NO ERROR 10
2768 !]SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE5 DBM_SEL_SCAD NTWK
2769
2770 END;
2771
2772 GLOBAL ROUTINE TST10: NOVALUE =
2773
2774 !++
2775 ! FUNCTIONAL DESCRIPTION:
2776 !
2777 ! LOAD 0 INTO FE, THEN PASS IT THRU SCAD BY OR'ING WITH 0
2778 ! LOAD 1777 INTO FE, THEN PASS IT THRU SCAD BY OR'ING WITH 0
2779 ! LOAD 0 INTO FE, THEN OR WITH 1777
2780 !
2781 !--
2782
2783 BEGIN
2784
2785 MACRO
2786 INFO_TUA = 0,0,36,0 %,
2787 INFO_COR = 1,0,36,0 %,
2788 INFO_FE = 2,0,36,0 %,
2789 INFO_A = 3,0,36,0 %;
2790
2791 LOCAL
2792 OK,
2793 COR,
2794 ACT;
2795
2796 LABEL
2797 LOOP1;
2798
2799 BIND
2800 TST_U_ADR = %O'1700',
2801 TST_U = PLIT
2802 (
2803 %(1700)% U_J(1702) V_SCAD_0 U_LOADFE U,
2804 %(1701)% U_J(1702) V_SCAD__1 U_LOADFE U,
2805 %(1702)% U_SCADA_SN U_SCADB_FE U_SCAD_OR U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
2806 %(1703)% U_J(1704) V_SCAD_0 U_LOADFE U,
2807 %(1704)% U_SN(1777) U_SCADA_SN U_SCADB_FE U_SCAD_OR U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U
2808 ),
2809 TUA_0 = TST_U_ADR + 0,
2810 TUA_1 = TST_U_ADR + 1,
2811 TUA_2 = TST_U_ADR + 3;
2812
2813 OWN
2814 INFO: BLOCKVECTOR[3,4] INITIAL
2815 (
2816 TUA_0, 0, 0, 0,
2817 TUA_1, O1777, O1777, 0,
2818 TUA_2, O1777, 0, O1777
2819 );
2820
2821 OK = 1;
2822 LOAD_TST_U;
2823
2824 INCR SUBTEST FROM 0 TO 2 DO
2825 ERROR_LOOP(1)
2826 (
2827 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
2828 CP(2);
2829 ERRINFO[2] = COR = .INFO[.SUBTEST,INFO_COR];
2830 ACT = SCAD_Q();
2831 IF .COR NEQ .ACT
2832 THEN
2833 (
2834 ERRINFO[0] = .INFO[.SUBTEST,INFO_FE];
2835 ERRINFO[1] = .INFO[.SUBTEST,INFO_A];
2836 ERRCAS
2837 (
2838 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
2839 1,.COR,.ACT,4,ERRINFO ! VERSION 1.1
2840 );
2841 OK = 0;
2842 );
2843 EXIT_LOOP(1,1);
2844 EXIT_LOOP(1,2);
2845 0
2846 );
2847
2848 IFN .OK
2849 THEN
2850 (
2851 NOERR(1);
2852 NOERR(2);
2853 );
2854
2855 !*MESSAGE 1
2856 !*STIMULUS:
2857 !* LOAD \O0 INTO FE; OR WITH \O1
2858 !*RESPONSE:
2859 !* OUTPUT OF SCAD SHOULD BE \O2
2860
2861 !]ERROR 1
2862 !]SCAD_OR SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK
2863
2864 !]NO ERROR 1
2865 !]SCAD_OR SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK
2866
2867 !]ERROR 2
2868 !]SCAD_OR SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK
2869
2870 !]NO ERROR 2
2871 !]SCAD_OR SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK
2872
2873 END;
2874
2875 GLOBAL ROUTINE TST11: NOVALUE =
2876
2877 !++
2878 ! FUNCTIONAL DESCRIPTION:
2879 !
2880 ! LOAD 0 ONTO DP AND PASS SCADB SHIFT THRU
2881 ! LOAD -1 ONTO DP AND PASS SCADB SHIFT THRU
2882 !
2883 !--
2884
2885 BEGIN
2886
2887 MACRO
2888 INFO_TUA = 0,0,36,0 %,
2889 INFO_COR = 1,0,36,0 %,
2890 INFO_DP = 2,0,36,0 %;
2891
2892 LOCAL
2893 OK,
2894 COR,
2895 ACT;
2896
2897 LABEL
2898 LOOP1,
2899 LOOP2;
2900
2901 BIND
2902 TST_U_ADR = %O'104',
2903 TST_U = PLIT
2904 (
2905 %(0104)% U_J(106) V_DP_0 U_SN(0) U_SCADA_SN U_SCADB_SHIFT U_SCAD_OR U_DBM_SCAD V_AC_DBM U,
2906 %(0105)% U_J(106) V_DP__1 U_SN(0) U_SCADA_SN U_SCADB_SHIFT U_SCAD_OR U_DBM_SCAD V_AC_DBM U,
2907 %(0106)% V_D_AC V_DP_D U_DEST_Q_AD U
2908 ),
2909 TUA_0 = TST_U_ADR + 0,
2910 TUA_1 = TST_U_ADR + 1;
2911
2912 OWN
2913 INFO: BLOCKVECTOR[2,3] INITIAL
2914 (
2915 TUA_0, 0, 0,
2916 TUA_1, O1777, -1
2917 );
2918
2919 OK = 1;
2920 LOAD_TST_U;
2921
2922 INCR SUBTEST FROM 0 TO 1 DO
2923 ERROR_LOOP(1)
2924 (
2925 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
2926 CP(2);
2927 ERRINFO[1] = COR = .INFO[.SUBTEST,INFO_COR];
2928 ACT = SCAD_Q();
2929 IF .COR NEQ .ACT
2930 THEN
2931 (
2932 ERRINFO[0] = .INFO[.SUBTEST,INFO_DP];
2933 ERRCAS
2934 (
2935 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
2936 1,.COR,.ACT,4,ERRINFO ! VERSION 1.1
2937 );
2938 OK = 0;
2939 );
2940 EXIT_LOOP(1,1);
2941 EXIT_LOOP(1,2);
2942 0
2943 );
2944
2945 IFN .OK
2946 THEN
2947 (
2948 NOERR(1);
2949 NOERR(2);
2950 );
2951
2952 !*MESSAGE 1
2953 !*STIMULUS:
2954 !* LOAD \O0 ONTO DP; PASS IT THRU SCADB SHIFT-COUNT
2955 !*RESPONSE:
2956 !* OUTPUT OF SCAD SHOULD BE \O1
2957
2958 !]ERROR 1
2959 !]SCAD_OR SCADB_SHIFT SCADA_SN DBM_SCAD NTWK
2960
2961 !]NO ERROR 1
2962 !]SCAD_OR SCADB_SHIFT SCADA_SN DBM_SCAD NTWK
2963
2964 !]ERROR 2
2965 !]SCAD_OR SCADB_SEL_SHIFT SCADA_SEL_SN DBM_SEL_SCAD NTWK
2966
2967 !]NO ERROR 2
2968 !]SCAD_OR SCADB_SEL_SHIFT SCADA_SEL_SN DBM_SEL_SCAD NTWK
2969
2970 END;
2971
2972 GLOBAL ROUTINE TST12: NOVALUE =
2973
2974 !++
2975 ! FUNCTIONAL DESCRIPTION:
2976 !
2977 ! LOAD 0 ONTO DP AND PASS SCADB SIZE THRU
2978 ! LOAD -1 ONTO DP AND PASS SCADB SIZE THRU
2979 !
2980 !--
2981
2982 BEGIN
2983
2984 MACRO
2985 INFO_TUA = 0,0,36,0 %,
2986 INFO_COR = 1,0,36,0 %,
2987 INFO_DP = 2,0,36,0 %;
2988
2989 LOCAL
2990 OK,
2991 COR,
2992 ACT;
2993
2994 LABEL
2995 LOOP1,
2996 LOOP2;
2997
2998 BIND
2999 TST_U_ADR = %O'111',
3000 TST_U = PLIT
3001 (
3002 %(0111)% U_J(113) U_SN(0) U_SCADA_SN U_SCADB_SIZE U_SCAD_OR U_DBM_SCAD V_AC_DBM U,
3003 %(0112)% U_J(113) V_DP__1 U_SN(0) U_SCADA_SN U_SCADB_SIZE U_SCAD_OR U_DBM_SCAD V_AC_DBM U,
3004 %(0113)% V_D_AC V_DP_D U_DEST_Q_AD U
3005 ),
3006 TUA_0 = TST_U_ADR + 0,
3007 TUA_1 = TST_U_ADR + 1;
3008
3009 OWN
3010 INFO: BLOCKVECTOR[2,3] INITIAL
3011 (
3012 TUA_0, 0, 0,
3013 TUA_1, %O'0770', -1
3014 );
3015
3016 OK = 1;
3017 LOAD_TST_U;
3018
3019 INCR SUBTEST FROM 0 TO 1 DO
3020 ERROR_LOOP(1)
3021 (
3022 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
3023 CP(2);
3024 ERRINFO[1] = COR = .INFO[.SUBTEST,INFO_COR];
3025 ACT = SCAD_Q();
3026 IF .COR NEQ .ACT
3027 THEN
3028 (
3029 ERRINFO[0] = .INFO[.SUBTEST,INFO_DP];
3030 ERRCAS
3031 (
3032 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
3033 1,.COR,.ACT,4,ERRINFO ! VERSION 1.1
3034 );
3035 OK = 0;
3036 );
3037 EXIT_LOOP(1,1);
3038 EXIT_LOOP(1,2);
3039 0
3040 );
3041
3042 IFN .OK
3043 THEN
3044 (
3045 NOERR(1);
3046 NOERR(2);
3047 );
3048
3049 !*MESSAGE 1
3050 !*STIMULUS:
3051 !* LOAD \O0 ONTO DP, PASS THRU SCADB BYTE-SIZE
3052 !*RESPONSE:
3053 !* OUTPUT OF SCAD SHOULD BE \O1
3054
3055 !]ERROR 1
3056 !]SCAD_OR SCADB_SIZE SCADA_SN DBM_SCAD NTWK
3057
3058 !]NO ERROR 1
3059 !]SCAD_OR SCADB_SIZE SCADA_SN DBM_SCAD NTWK
3060
3061 !]ERROR 2
3062 !]SCAD_OR SCADB_SEL_SIZE SCADA_SEL_SN DBM_SEL_SCAD NTWK
3063
3064 !]NO ERROR 2
3065 !]SCAD_OR SCADB_SEL_SIZE SCADA_SEL_SN DBM_SEL_SCAD NTWK
3066
3067 END;
3068
3069 GLOBAL ROUTINE TST13: NOVALUE =
3070
3071 !++
3072 ! FUNCTIONAL DESCRIPTION:
3073 !
3074 ! LOAD 0 ONTO DP AND PASS SCADB EXP THRU
3075 ! LOAD -1 ONTO DP AND PASS SCADB EXP THRU
3076 ! LOAD 400000,,400000 ONTO DP AND PASS SCADB EXP THRU
3077 ! LOAD 377777,,377777 ONTO DP AND PASS SCADB EXP THRU
3078 !
3079 !--
3080
3081 BEGIN
3082
3083 MACRO
3084 INFO_TUA = 0,0,36,0 %,
3085 INFO_CP = 1,0,36,0 %,
3086 INFO_COR = 2,0,36,0 %,
3087 INFO_DP = 3,0,36,0 %;
3088
3089 LOCAL
3090 OK,
3091 COR,
3092 ACT;
3093
3094 LABEL
3095 LOOP1;
3096
3097 BIND
3098 TST_U_ADR = %O'116',
3099 TST_U = PLIT
3100 (
3101 %(0116)% U_J(123) V_DP_0 U_SN(0) U_SCADA_SN U_SCADB_EXP U_SCAD_OR U_DBM_SCAD V_AC_DBM U,
3102 %(0117)% U_J(123) V_DP__1 U_SN(0) U_SCADA_SN U_SCADB_EXP U_SCAD_OR U_DBM_SCAD V_AC_DBM U,
3103 %(0120)% U_J(122) U_N(400000) U_DBM_N U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
3104 %(0121)% U_J(122) U_N(377777) U_DBM_N U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
3105 %(0122)% U_J(123) V_DP_Q U_SN(0) U_SCADA_SN U_SCADB_EXP U_SCAD_OR U_DBM_SCAD V_AC_DBM U,
3106 %(0123)% V_D_AC V_DP_D U_DEST_Q_AD U
3107 ),
3108 TUA_0 = TST_U_ADR + 0,
3109 TUA_1 = TST_U_ADR + 1,
3110 TUA_2 = TST_U_ADR + 2,
3111 TUA_3 = TST_U_ADR + 3;
3112
3113 OWN
3114 INFO: BLOCKVECTOR[4,4] INITIAL
3115 (
3116 TUA_0, 2, 0, 0,
3117 TUA_1, 2, 0, -1,
3118 TUA_2, 3, %O'377', %O'400000400000',
3119 TUA_3, 3, %O'377', %O'377777377777'
3120 );
3121
3122 OK = 1;
3123 LOAD_TST_U;
3124
3125 INCR SUBTEST FROM 0 TO 3 DO
3126 ERROR_LOOP(1)
3127 (
3128 ERRINFO[1] = COR = .INFO[.SUBTEST,INFO_COR];
3129 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
3130 CP(.INFO[.SUBTEST,INFO_CP]);
3131 ACT = SCAD_Q();
3132 IF .ACT NEQ .COR
3133 THEN
3134 (
3135 ERRINFO[0] = .INFO[.SUBTEST,INFO_DP];
3136 ERRCAS(1,1,.COR,.ACT,4,ERRINFO);
3137 OK = 0;
3138 );
3139 EXIT_LOOP(1,1);
3140 0
3141 );
3142
3143 IFN .OK THEN NOERR(1);
3144
3145 !*MESSAGE 1
3146 !*STIMULUS:
3147 !* LOAD \O0 ONTO DP, PASS THRU SCADB EXP
3148 !*RESPONSE:
3149 !* OUTPUT OF SCAD SHOULD BE \O1
3150
3151 !]ERROR 1
3152 !]SCADB_EXP SCAD_OR SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK
3153
3154 !]NO ERROR 1
3155 !]SCADB_EXP SCAD_OR SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK
3156
3157 END;
3158
3159 GLOBAL ROUTINE TST14: NOVALUE =
3160
3161 !++
3162 ! FUNCTIONAL DESCRIPTION:
3163 !
3164 ! LOAD 0 ONTO DP & SCAD; PASS THRU BYTES INPUT TO DBM MUX
3165 ! LOAD -1 ONTO DP & SCAD; PASS THRU BYTES INPUT TO DBM MUX
3166 !
3167 !--
3168
3169 BEGIN
3170
3171 MACRO
3172 INFO_TUA = 0,0,36,0 %,
3173 INFO_CP = 1,0,36,0 %,
3174 INFO_COR = 2,0,36,0 %;
3175
3176 LOCAL
3177 OK,
3178 COR,
3179 ACT;
3180
3181 LABEL
3182 LOOP1;
3183
3184 BIND
3185 TST_U_ADR = %O'131',
3186 TST_U = PLIT
3187 (
3188 %(0131)% U_J(132) V_DP_0 V_SCAD_0 U_DBM_BYTES V_AC_DBM U,
3189 %(0132)% V_D_AC V_DP_D U_DEST_Q_AD U_SKIP_ADEQ0 U,
3190 %(0133)% U_J(134) V_DP__1 V_SCAD__1 U_DBM_BYTES V_AC_DBM U,
3191 %(0134)% U_J(135) V_D_AC V_DP_D U_DEST_Q_AD U,
3192 %(0135)% U_A_AR U_LSRC_AQ U_ALU_XOR U_SKIP_ADEQ0 U
3193 ),
3194 TUA_0 = TST_U_ADR + 0,
3195 TUA_1 = TST_U_ADR + 2;
3196
3197 OWN
3198 INFO: BLOCKVECTOR[2,3] INITIAL
3199 (
3200 TUA_0, 2, 0,
3201 TUA_1, 3, -1
3202 );
3203
3204 OK = 1;
3205 LOAD_TST_U;
3206
3207 INCR SUBTEST FROM 0 TO 1 DO
3208 ERROR_LOOP(1)
3209 (
3210 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
3211 IF STEP_U_NEXT(.INFO[.SUBTEST,INFO_CP]) EQL 0
3212 THEN
3213 (
3214 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
3215 ACT = SERIAL(36);
3216 ERRCAS
3217 (
3218 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
3219 1,.COR,.ACT,12,ERRINFO
3220 );
3221 OK = 0;
3222 );
3223 EXIT_LOOP(1,1);
3224 0
3225 );
3226
3227 IFN .OK THEN NOERR(1);
3228
3229 !*MESSAGE 1
3230 !*STIMULUS:
3231 !* LOAD \O0 ONTO DP & SCAD; PASS THRU BYTES INPUT TO DBM MUX
3232 !*RESPONSE:
3233 !* OUTPUT OF DBM MUX SHOULD BE \O1
3234
3235 !]ERROR 1
3236 !]DBM_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3237
3238 !]NO ERROR 1
3239 !]DBM_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3240
3241 !]ERROR 2
3242 !]DBM_SEL_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3243
3244 !]NO ERROR 2
3245 !]DBM_SEL_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3246
3247 END;
3248
3249 GLOBAL ROUTINE TST15: NOVALUE =
3250
3251 !++
3252 ! FUNCTIONAL DESCRIPTION:
3253 !
3254 ! LOAD -1 ONTO DP, 0 THRU SCAD; INSERT INTO ALL BYTES
3255 ! LOAD 0 ONTO DP, 1777 THRU SCAD; INSERT INTO ALL BYTES
3256 !
3257 !--
3258
3259 BEGIN
3260
3261 MACRO
3262 INFO_TUA = 0,0,36,0 %,
3263 INFO_COR = 1,0,36,0 %,
3264 INFO_DP = 2,0,36,0 %,
3265 INFO_SCAD = 3,0,36,0 %;
3266
3267 LOCAL
3268 OK,
3269 COR,
3270 ACT;
3271
3272 LABEL
3273 LOOP1;
3274
3275 BIND
3276 TST_U_ADR = %O'140',
3277 TST_U = PLIT
3278 (
3279 %(0140)% U_J(141) U_A_T0 U_B_T0 U_LSRC_AB U_ALU_XNOR U_DEST_AD U,
3280 %(0141)% U_J(142) V_SCAD_0 U_DBM_DP U_BYTE_1 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3281 %(0142)% U_J(143) V_SCAD_0 U_DBM_DP U_BYTE_2 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3282 %(0143)% U_J(144) V_SCAD_0 U_DBM_DP U_BYTE_3 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3283 %(0144)% U_J(145) V_SCAD_0 U_DBM_DP U_BYTE_4 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3284 %(0145)% U_J(146) V_SCAD_0 U_DBM_DP U_BYTE_5 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3285 %(0146)% U_J(147) V_DP_T0 U_DEST_Q_AD U,
3286 %(0147)% U_A_AR U_LSRC_AQ U_ALU_ADD U_SKIP_ADEQ0 U,
3287 %(0150)% U_J(151) U_B_T0 U_LSRC_0B U_ALU_AND U_DEST_AD U,
3288 %(0151)% U_J(152) V_SCAD__1 U_DBM_DP U_BYTE_1 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3289 %(0152)% U_J(153) V_SCAD__1 U_DBM_DP U_BYTE_2 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3290 %(0153)% U_J(154) V_SCAD__1 U_DBM_DP U_BYTE_3 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3291 %(0154)% U_J(155) V_SCAD__1 U_DBM_DP U_BYTE_4 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3292 %(0155)% U_J(156) V_SCAD__1 U_DBM_DP U_BYTE_5 U_DBUS_DBM U_A_T0 U_B_T0 V_DP_D U_DEST_A U,
3293 %(0156)% U_J(157) V_DP_T0 U_DEST_Q_AD U,
3294 %(0157)% U_A_ARX U_LSRC_AQ U_ALU_XOR U_SKIP_ADEQ0 U
3295 ),
3296 TUA_0 = TST_U_ADR + 0,
3297 TUA_1 = TST_U_ADR + 8;
3298
3299 OWN
3300 INFO: BLOCKVECTOR[2,4] INITIAL
3301 (
3302 TUA_0, 1, -1, 0,
3303 TUA_1, -2, 0, O1777
3304 );
3305
3306 OK = 1;
3307 LOAD_TST_U;
3308
3309 INCR SUBTEST FROM 0 TO 1 DO
3310 ERROR_LOOP(1)
3311 (
3312 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
3313 IF STEP_U_NEXT(8) EQL 0
3314 THEN
3315 (
3316 ERRINFO[0] = .INFO[.SUBTEST,INFO_DP];
3317 ERRINFO[1] = .INFO[.SUBTEST,INFO_SCAD];
3318 ERRINFO[2] = COR = .INFO[.SUBTEST,INFO_COR];
3319 ACT = SERIAL(36);
3320 ERRCAS
3321 (
3322 (IF SINGLE_BIT(.COR<1,35>,.ACT<1,35>) THEN 1 ELSE 2),
3323 1,.COR,.ACT,12,ERRINFO
3324 );
3325 OK = 0;
3326 );
3327 EXIT_LOOP(1,1);
3328 0
3329 );
3330
3331 IFN .OK THEN NOERR(1);
3332
3333 !*MESSAGE 1
3334 !*STIMULUS:
3335 !* LOAD \O0 ONTO DP, \O1 THRU SCAD; INSERT INTO ALL BYTES
3336 !*RESPONSE:
3337 !* OUTPUT OF DBM MUX SHOULD BE \O2
3338
3339 !]ERROR 1
3340 !]DBM_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3341
3342 !]NO ERROR 1
3343 !]DBM_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3344
3345 !]ERROR 2
3346 !]DBM_SEL_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3347
3348 !]NO ERROR 2
3349 !]DBM_SEL_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK
3350
3351 END;
3352
3353 GLOBAL ROUTINE TST16: NOVALUE =
3354
3355 !++
3356 ! FUNCTIONAL DESCRIPTION:
3357 !
3358 ! LOAD 1777 INTO FE, THEN AND WITH 0
3359 ! LOAD 0 INTO FE, THEN AND WITH 1777
3360 ! LOAD 1777 INTO FE, THEN AND WITH 1777
3361 !
3362 !--
3363
3364 BEGIN
3365
3366 MACRO
3367 INFO_TUA = 0,0,36,0 %,
3368 INFO_COR = 1,0,36,0 %,
3369 INFO_FE = 2,0,36,0 %,
3370 INFO_A = 3,0,36,0 %;
3371
3372 LOCAL
3373 OK,
3374 COR,
3375 ACT;
3376
3377 LABEL
3378 LOOP1;
3379
3380 BIND
3381 TST_U_ADR = %O'204',
3382 TST_U = PLIT
3383 (
3384 %(0204)% U_J(205) V_SCAD__1 U_LOADFE U,
3385 %(0205)% U_SN(0) U_SCADA_SN U_SCADB_FE U_SCAD_AND U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
3386 %(0206)% U_J(210) V_SCAD_0 U_LOADFE U,
3387 %(0207)% U_J(210) V_SCAD__1 U_LOADFE U,
3388 %(0210)% U_SN(1777) U_SCADA_SN U_SCADB_FE U_SCAD_AND U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U
3389 ),
3390 TUA_0 = TST_U_ADR + 0,
3391 TUA_1 = TST_U_ADR + 2,
3392 TUA_2 = TST_U_ADR + 3;
3393
3394 OWN
3395 INFO: BLOCKVECTOR[3,4] INITIAL
3396 (
3397 TUA_0, 0, O1777, 0,
3398 TUA_1, 0, 0, O1777,
3399 TUA_2, O1777, O1777, O1777
3400 );
3401
3402 OK = 1;
3403 LOAD_TST_U;
3404
3405 INCR SUBTEST FROM 0 TO 2 DO
3406 ERROR_LOOP(1)
3407 (
3408 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
3409 CP(2);
3410 ERRINFO[0] = COR = .INFO[.SUBTEST,INFO_COR];
3411 ACT = SCAD_Q();
3412 IF .COR NEQ .ACT
3413 THEN
3414 (
3415 ERRINFO[0] = .INFO[.SUBTEST,INFO_FE];
3416 ERRINFO[1] = .INFO[.SUBTEST,INFO_A];
3417 ERRCAS
3418 (
3419 (IF SINGLE_BIT(.COR,.ACT) THEN 1 ELSE 2),
3420 1,.COR,.ACT,4,ERRINFO
3421 );
3422 OK = 0;
3423 );
3424 EXIT_LOOP(1,1);
3425 EXIT_LOOP(1,2);
3426 0
3427 );
3428
3429 IFN .OK
3430 THEN
3431 (
3432 NOERR(1);
3433 NOERR(2);
3434 );
3435
3436 !*MESSAGE 1
3437 !*STIMULUS:
3438 !* LOAD \O0 INTO FE, THEN AND WITH \O1
3439 !*RESPONSE:
3440 !* OUTPUT OF SCAD SHOULD BE \O2
3441
3442 !]ERROR 1
3443 !]SCAD_AND SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK
3444
3445 !]NO ERROR 1
3446 !]SCAD_AND SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK
3447
3448 !]ERROR 2
3449 !]SCAD_AND SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK
3450
3451 !]NO ERROR 2
3452 !]SCAD_AND SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK
3453
3454 END;
3455
3456 GLOBAL ROUTINE TST17: NOVALUE =
3457
3458 !++
3459 ! FUNCTIONAL DESCRIPTION:
3460 !
3461 ! LOAD 0, 1777 INTO SC, FE AND DO SCAD ADD, SUB, AND SUBB
3462 ! PUT RESULTS IN Q AND EXAMINE WITH SERIAL
3463 ! (ON SECOND THOUGHT, THIS IS NOT THE FASTEST ORDERING)
3464 !
3465 !--
3466
3467 BEGIN
3468
3469 MACRO
3470 INFO_FUNC = 0,0,36,0 %,
3471 INFO_A = 1,0,36,0 %,
3472 INFO_B = 2,0,36,0 %,
3473 INFO_CORR = 3,0,36,0 %;
3474
3475 LABEL
3476 LOOP1;
3477
3478 BIND
3479 TST_U_ADR = %O'220',
3480 TST_U = PLIT
3481 (
3482 %(0220)% V_SCAD_0 U_LOADSC U,
3483 %(0221)% V_SCAD_0 U_LOADFE U,
3484 %(0222)% V_SCAD__1 U_LOADSC U,
3485 %(0223)% V_SCAD__1 U_LOADFE U,
3486 %(0224)% U_SCADA_SC U_SCADB_FE U_SCAD_ADD U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
3487 %(0225)% U_SCADA_SC U_SCADB_FE U_SCAD_SUB U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
3488 %(0226)% U_SCADA_SC U_SCADB_FE U_SCAD_SUBB U_DBM_SCAD U_DBUS_DBM V_DP_D U_DEST_Q_AD U
3489 ),
3490 TUA_SC_0 = TST_U_ADR + 0,
3491 TUA_FE_0 = TST_U_ADR + 1,
3492 TUA_SC__1 = TST_U_ADR + 2,
3493 TUA_FE__1 = TST_U_ADR + 3,
3494 TUA_ADD = TST_U_ADR + 4,
3495 TUA_SUB = TST_U_ADR + 5,
3496 TUA_SUBB = TST_U_ADR + 6;
3497
3498 LOCAL
3499 OK_ADD,
3500 OK_SUB,
3501 OK_SUBB,
3502 SCAD_VAL;
3503
3504 OWN
3505 INFO: BLOCKVECTOR[12,4] INITIAL
3506 (
3507 TUA_ADD, TUA_SC_0, TUA_FE_0, 0,
3508 TUA_ADD, TUA_SC_0, TUA_FE__1, O1777,
3509 TUA_ADD, TUA_SC__1, TUA_FE_0, O1777,
3510 TUA_ADD, TUA_SC__1, TUA_FE__1, O1776,
3511 TUA_SUB, TUA_SC_0, TUA_FE_0, 0,
3512 TUA_SUB, TUA_SC_0, TUA_FE__1, 1,
3513 TUA_SUB, TUA_SC__1, TUA_FE_0, O1777,
3514 TUA_SUB, TUA_SC__1, TUA_FE__1, 0,
3515 TUA_SUBB, TUA_SC_0, TUA_FE_0, O1777,
3516 TUA_SUBB, TUA_SC_0, TUA_FE__1, 0,
3517 TUA_SUBB, TUA_SC__1, TUA_FE_0, O1776,
3518 TUA_SUBB, TUA_SC__1, TUA_FE__1, O1777
3519 );
3520
3521 LOAD_TST_U;
3522 OK_ADD = 1;
3523 OK_SUB = 1;
3524 OK_SUBB = 1;
3525
3526 INCR ERRN FROM 0 TO 11 DO
3527 ERROR_LOOP(1)
3528 (
3529 SET_CRAM_ADR(.INFO[.ERRN,INFO_A]);
3530 CP(2); ! EXTRA CLOCK PULSE NEEDED
3531 SET_CRAM_ADR(.INFO[.ERRN,INFO_B]);
3532 CP(2); ! EXTRA CLOCK PULSE NEEDED
3533 SET_CRAM_ADR(.INFO[.ERRN,INFO_FUNC]);
3534 CP(1);
3535 SCAD_VAL = SCAD_Q();
3536 IF .SCAD_VAL NEQ .INFO[.ERRN,INFO_CORR]
3537 THEN
3538 (
3539 ERRINFO[0] =
3540 (IF .INFO[.ERRN,INFO_A] EQL TUA_SC_0 THEN 0 ELSE O1777);
3541 ERRINFO[1] =
3542 (IF .INFO[.ERRN,INFO_B] EQL TUA_FE_0 THEN 0 ELSE O1777);
3543 ERRINFO[2] = .INFO[.ERRN,INFO_CORR];
3544 ERRINFO[3] =
3545 (
3546 CASE .ERRN/4 FROM 0 TO 2 OF
3547 SET
3548 [0]: (OK_ADD = 0; UPLIT(%ASCIZ 'ADD'));
3549 [1]: (OK_SUB = 0; UPLIT(%ASCIZ 'SUB'));
3550 [2]: (OK_SUBB = 0; UPLIT(%ASCIZ 'SUBB'));
3551 TES
3552 );
3553 ERRCAS(.ERRN/4+1,1,.INFO[.ERRN,INFO_CORR],.SCAD_VAL,4,ERRINFO);
3554 );
3555 EXIT_LOOP(1,.ERRN/4+1);
3556 0
3557 );
3558
3559 IFN .OK_ADD THEN NOERR(1);
3560 IFN .OK_SUB THEN NOERR(2);
3561 IFN .OK_SUBB THEN NOERR(3);
3562
3563 !*MESSAGE 1
3564 !*STIMULUS:
3565 !* LOAD SC WITH \O0, LOAD FE WITH \O1, SCAD \S3
3566 !*RESPONSE:
3567 !* OUTPUT OF SCAD SHOULD BE \O2
3568
3569 !]ERROR 1
3570 !]SCAD_ADD SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK
3571
3572 !]NO ERROR 1
3573 !]SCAD_ADD SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK
3574
3575 !]ERROR 2
3576 !]SCAD_SUB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK
3577
3578 !]NO ERROR 2
3579 !]SCAD_SUB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK
3580
3581 !]ERROR 3
3582 !]SCAD_SUBB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK
3583
3584 !]NO ERROR 3
3585 !]SCAD_SUBB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK
3586
3587 END;
3588
3589 GLOBAL ROUTINE TST18: NOVALUE =
3590
3591 !++
3592 ! FUNCTIONAL DESCRIPTION:
3593 !
3594 ! LOAD 0 INTO VMA AND SEE IF EASY BITS ARE 0
3595 ! LOAD -1 INTO VMA AND SEE IF EASY BITS (EXCEPT 1, 6) ARE 1
3596 ! EASY BITS ARE 0:2, 6, 8:35
3597 ! BITS WHICH ARE NOT "EASY" ARE ASSUMED TO BE OK HERE
3598 !
3599 !--
3600
3601 BEGIN
3602
3603 MACRO
3604 INFO_TUA = 0,0,36,0 %,
3605 INFO_COR = 1,0,36,0 %,
3606 INFO_DP = 2,0,36,0 %,
3607 INFO_N = 3,0,36,0 %,
3608 INFO_VALUE = 4,0,36,0 %;
3609
3610 LOCAL
3611 DIF,
3612 ALL_DIF,
3613 ACT,
3614 COR;
3615
3616 LABEL
3617 LOOP1,
3618 LOOP2;
3619
3620 BIND
3621 TST_U_ADR = %O'230',
3622 TST_U = PLIT
3623 (
3624 %(0230)% U_J(232) U_N(501020) V_DP_0 U_SPEC_SWEEP U,
3625 %(0231)% U_J(232) U_N(20) V_DP__1 U_SPEC_SWEEP U,
3626 %(0232)% U_DBM_VMA U_DBUS_DBM V_DP_D U_DEST_Q_AD U
3627 ),
3628 TUA_0 = TST_U_ADR + 0,
3629 TUA_1 = TST_U_ADR + 1,
3630 VMA_EASY_MASK = %O'072000000000', ! EASY BITS 0
3631 ! NOT-EASY BITS 1
3632 VMA_EASY_VALU = %O'501777777777'; ! EASY BITS 1 BUT GND 0
3633 ! NOT-EASY BITS 0
3634
3635 OWN
3636 INFO: BLOCKVECTOR[2,5] INITIAL
3637 (
3638 TUA_0, 0, 0, %O'501020', 0,
3639 TUA_1, 1, -1, %O'20', VMA_EASY_VALU
3640 ),
3641 VMA_ERROR_FIELD: VECTOR[6] INITIAL
3642 (
3643 %O'400000000000', ! USER
3644 %O'100000000000', ! FETCH
3645 %O'001000000000', ! PHYS
3646 %O'000400000000', ! PREV
3647 %O'000360000000', ! CYCLE (I/O, WRU, VECTOR, I/O BYTE)
3648 %O'000017777777' ! VMA
3649 );
3650
3651 LOAD_TST_U;
3652 ALL_DIF = 0;
3653
3654 INCR SUBTEST FROM 0 TO 1 DO
3655 ERROR_LOOP(1)
3656 (
3657 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
3658 CP(2);
3659 ACT = SERIAL(36);
3660 COR = (.ACT AND VMA_EASY_MASK) OR .INFO[.SUBTEST,INFO_VALUE];
3661 DIF = .COR XOR .ACT;
3662 ALL_DIF = .ALL_DIF OR .DIF;
3663 IF .ACT NEQ .COR
3664 THEN
3665 (
3666 ERRINFO[0] = .INFO[.SUBTEST,INFO_COR];
3667 ERRINFO[1] = .INFO[.SUBTEST,INFO_DP];
3668 ERRINFO[2] = .INFO[.SUBTEST,INFO_N];
3669 ERMCAS(1,.COR,.ACT,12,ERRINFO);
3670 INCR ERRN FROM 0 TO 5 DO
3671 IFN (.DIF AND .VMA_ERROR_FIELD[.ERRN])
3672 THEN
3673 FAILURE(.ERRN + 2);
3674 );
3675 INCR ERRN FROM 2 TO 7 DO
3676 EXIT_LOOP(1,.ERRN);
3677 0
3678 );
3679
3680 !*MESSAGE 1
3681 !*STIMULUS:
3682 !* LOAD \O1 INTO VMA (SWEEP LATCH) AND THRU DBM MUX WITH #=\O2
3683 !*RESPONSE:
3684 !* DBM OUTPUT BITS 0, 2, 8:35 SHOULD BE \O0
3685 !* DBM OUTPUT BITS 1, 6 SHOULD BE 0
3686
3687 IF .ALL_DIF EQL 0
3688 THEN
3689 NOERR(1)
3690 ELSE
3691 INCR ERRN FROM 0 TO 5 DO
3692 IF (.ALL_DIF AND .VMA_ERROR_FIELD[.ERRN]) EQL 0
3693 THEN
3694 NOERR(.ERRN + 2);
3695
3696 !]NO ERROR 1
3697 !]VMA_USER_DP VMA_FETCH_DP VMA_PHYS_DP VMA_PREV_DP VMA_CYCLE_DP VMA DBM_VMA SPEC_SWEEP NTWK
3698
3699 !]ERROR 2
3700 !]VMA_USER_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK
3701
3702 !]NO ERROR 2
3703 !]VMA_USER_DP NTWK
3704
3705 !]ERROR 3
3706 !]VMA_FETCH_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK
3707
3708 !]NO ERROR 3
3709 !]VMA_FETCH_DP NTWK
3710
3711 !]ERROR 4
3712 !]VMA_PHYS_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK
3713
3714 !]NO ERROR 4
3715 !]VMA_PHYS_DP NTWK
3716
3717 !]ERROR 5
3718 !]VMA_PREV_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK
3719
3720 !]NO ERROR 5
3721 !]VMA_PREV_DP NTWK
3722
3723 !]ERROR 6
3724 !]VMA_CYCLE_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK
3725
3726 !]NO ERROR 6
3727 !]VMA_CYCLE_DP NTWK
3728
3729 !]ERROR 7
3730 !]VMA DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK
3731
3732 !]NO ERROR 7
3733 !]VMA NTWK
3734
3735 END;
3736
3737 GLOBAL ROUTINE TST19: NOVALUE =
3738
3739 !++
3740 ! FUNCTIONAL DESCRIPTION:
3741 !
3742 ! PASS 0 THRU THE EXP HALFWORD INPUT TO DBM MUX
3743 ! PASS -1 THRU THE EXP HALFWORD INPUT TO DBM MUX
3744 !
3745 !--
3746
3747 BEGIN
3748
3749 LOCAL
3750 EXP_VAL,
3751 OK;
3752
3753 LABEL
3754 LOOP1,
3755 LOOP2;
3756
3757 BIND
3758 TST_U_ADR = %O'240',
3759 TST_U = PLIT
3760 (
3761 %(0240)% U_J(242) V_DP_0 V_SCAD_0 U_DBM_EXP V_AC_DBM U,
3762 %(0241)% U_J(242) V_DP__1 V_SCAD__1 U_DBM_EXP V_AC_DBM U,
3763 %(0242)% V_D_AC V_DP_D U_DEST_Q_AD U_NO_CLKR U_SKIP_ADLEQ0 U
3764 ),
3765 TUA_0 = TST_U_ADR + 0,
3766 TUA_1 = TST_U_ADR + 1;
3767
3768 LOAD_TST_U;
3769 OK = 1;
3770
3771 ERROR_LOOP(1)
3772 (
3773 SET_CRAM_ADR(TUA_0);
3774 IF STEP_U_NEXT(2) EQL 0
3775 THEN
3776 (
3777 ERRCAS(1,1,0,SERIAL(18),6,OK);
3778 OK = 0;
3779 );
3780 EXIT_LOOP(1,1);
3781 0
3782 );
3783
3784 !*MESSAGE 1
3785 !*STIMULUS:
3786 !* LOAD 0 FROM DP, SCAD THRU DBM MUX EXP INPUT
3787 !*RESPONSE:
3788 !* OUTPUT OF DBM MUX LEFT HALFWORD SHOULD BE 0
3789
3790 ERROR_LOOP(2)
3791 (
3792 SET_CRAM_ADR(TUA_1);
3793 CP(2);
3794 EXP_VAL = SERIAL(18);
3795 IF .EXP_VAL NEQ %O'377777'
3796 THEN
3797 (
3798 ERRCAS(1,2,%O'377777',.EXP_VAL,6,ERRINFO);
3799 OK = 0;
3800 );
3801 EXIT_LOOP(2,1);
3802 0
3803 );
3804
3805 IFN .OK THEN NOERR(1);
3806
3807 !*MESSAGE 2
3808 !*STIMULUS:
3809 !* LOAD -1 FROM DP, SCAD THRU DBM MUX EXP INPUT
3810 !*RESPONSE:
3811 !* OUTPUT OF DBM MUX LEFT HALFWORD SHOULD BE 377777
3812
3813 !]ERROR 1
3814 !]DBM_EXP DBM_SEL_EXP SCAD_A SCADA_SN NTWK
3815
3816 !]NO ERROR 1
3817 !]DBM_EXP DBM_SEL_EXP SCAD_A SCADA_SN NTWK
3818
3819 END;
3820
3821 GLOBAL ROUTINE TST20: NOVALUE =
3822
3823 !++
3824 ! FUNCTIONAL DESCRIPTION:
3825 !
3826 ! CHECK VMA FLAG BITS 0, 2, 8, 10:13 DBM MUX INPUTS STUCK HIGH/LOW
3827 ! OTHER BITS ARE ASSUMED TO BE OK HERE
3828 !
3829 !--
3830
3831 BEGIN
3832
3833 MACRO
3834 INFO_TUA = 0,0,36,0 %,
3835 INFO_DBM028 = 1,0,36,0 %,
3836 INFO_DP = 2,0,36,0 %,
3837 INFO_N = 3,0,36,0 %,
3838 INFO_VALU = 4,0,36,0 %;
3839
3840 LOCAL
3841 DIF,
3842 ALL_DIF,
3843 ACT,
3844 COR;
3845
3846 LABEL
3847 LOOP1,
3848 LOOP2;
3849
3850 BIND
3851 TST_U_ADR = %O'250',
3852 TST_U = PLIT
3853 (
3854 %(0250)% U_J(252) U_N(0) V_DP__1 U_SPEC_SWEEP U,
3855 %(0251)% U_J(252) U_N(501000) V_DP_0 U_SPEC_SWEEP U,
3856 %(0252)% U_DBM_VMA U_DBUS_DBM V_DP_D U_DEST_Q_AD U
3857 ),
3858 TUA_0 = TST_U_ADR + 0,
3859 TUA_1 = TST_U_ADR + 1,
3860 VMA_EASY_MASK = %O'27641', ! EASY BITS 0
3861 ! NOT-EASY BITS 1
3862 VMA_EASY_VALU = %O'50100'; ! EASY BITS 1 BUT GND 0
3863 ! NOT-EASY BITS 0
3864
3865 OWN
3866 VMA_ERROR_FIELD: VECTOR[4] INITIAL ! VMA FLAGS BITS 0:14
3867 (
3868 %O'40000',
3869 %O'10000',
3870 %O'00100',
3871 %O'00036'
3872 ),
3873 INFO: BLOCKVECTOR[2,5] INITIAL
3874 (
3875 TUA_0, 0, -1, 0, 0,
3876 TUA_1, 1, 0, %O'501000', VMA_EASY_VALU
3877 );
3878
3879 LOAD_TST_U;
3880 ALL_DIF = 0;
3881
3882 INCR SUBTEST FROM 0 TO 1 DO
3883 ERROR_LOOP(1)
3884 (
3885 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
3886 CP(2);
3887 ACT = SERIAL(15);
3888 COR = (.ACT AND VMA_EASY_MASK) OR .INFO[.SUBTEST,INFO_VALU];
3889 DIF = .COR XOR .ACT;
3890 ALL_DIF = .ALL_DIF OR .DIF;
3891 IF .ACT NEQ .COR
3892 THEN
3893 (
3894 ERRINFO[0] = .INFO[.SUBTEST,INFO_N];
3895 ERRINFO[1] = .INFO[.SUBTEST,INFO_DP];
3896 ERRINFO[2] = .INFO[.SUBTEST,INFO_DBM028];
3897 ERMCAS(1,.COR,.ACT,5,ERRINFO);
3898 INCR ERRN FROM 0 TO 3 DO
3899 IFN (.DIF AND .VMA_ERROR_FIELD[.ERRN])
3900 THEN
3901 FAILURE(.ERRN + 2);
3902 );
3903 INCR ERRN FROM 2 TO 5 DO
3904 EXIT_LOOP(1,.ERRN);
3905 0
3906 );
3907
3908 IF .ALL_DIF EQL 0
3909 THEN
3910 NOERR(1)
3911 ELSE
3912 INCR ERRN FROM 0 TO 3 DO
3913 IF (.ALL_DIF AND .VMA_ERROR_FIELD[.ERRN]) EQL 0
3914 THEN
3915 NOERR(.ERRN + 2);
3916
3917 !*MESSAGE 1
3918 !*STIMULUS:
3919 !* LOAD 0 INTO VMA BITS 0, 2, 8 (SWEEP LATCH)
3920 !* AND THRU DBM MUX WITH # = \O0; DP = \O1
3921 !*RESPONSE:
3922 !* DBM OUTPUT BITS 0, 2, 8 SHOULD BE \O2
3923 !* DBM OUTPUT BITS 10:13 SHOULD BE 0
3924 !*CORRECT & ACTUAL ARE VMA FLAGS BITS 0:14
3925
3926 !]NO ERROR 1
3927 !]VMA_USER_N VMA_FETCH_N VMA_PHYS_N VMA_CYCLE_N NTWK
3928
3929 !]ERROR 2
3930 !]VMA_USER_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK
3931
3932 !]NO ERROR 2
3933 !]VMA_USER_N NTWK
3934
3935 !]ERROR 3
3936 !]VMA_FETCH_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK
3937
3938 !]NO ERROR 3
3939 !]VMA_FETCH_N NTWK
3940
3941 !]ERROR 4
3942 !]VMA_PHYS_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK
3943
3944 !]NO ERROR 4
3945 !]VMA_PHYS_N NTWK
3946
3947 !]ERROR 5
3948 !]VMA_CYCLE_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK
3949
3950 !]NO ERROR 5
3951 !]VMA_CYCLE_N NTWK
3952
3953 END;
3954
3955 GLOBAL ROUTINE TST21: NOVALUE =
3956
3957 !++
3958 ! FUNCTIONAL DESCRIPTION:
3959 !
3960 ! TRY TO READ & WRITE AC0 VIA VMA
3961 ! FAILS IF FORCE RAMFILE IS SOMEHOW STUCK "OFF"
3962 ! (OR ANY OF "VMA <18:31> L" ARE STUCK HIGH)
3963 !
3964 !--
3965
3966 BEGIN
3967
3968 LOCAL
3969 LOC_0_VAL;
3970
3971 LABEL
3972 LOOP1,
3973 LOOP2;
3974
3975 BIND
3976 TST_U_ADR = %O'260',
3977 TST_U = PLIT
3978 (
3979 %(0260)% U_J(261) V_DP__1 V_AC_DP U,
3980 %(0261)% U_J(262) V_DP_0 U_MEM U_N(10012) U,
3981 %(0262)% V_DP_0 U_MEM U_N(2) U,
3982 %(0263)% U_J(264) V_DP_0 V_AC_DP U,
3983 %(0264)% U_J(265) V_DP_0 U_MEM U_N(40012) U,
3984 %(0265)% U_MEM U_N(2) U_DBM_MEM U_DBUS_DBM V_DP_D U_DEST_Q_AD U_SKIP_ADEQ0 U
3985 ),
3986 TUA_W = TST_U_ADR + 0,
3987 TUA_R = TST_U_ADR + 3;
3988
3989 LOAD_TST_U;
3990 ERROR_LOOP(1)
3991 (
3992 MEM_DEPOSIT(0,-1);
3993 SET_CRAM_ADR(TUA_W);
3994 CP(3);
3995 LOC_0_VAL = MEM_EXAMINE(0);
3996 IF .LOC_0_VAL NEQ -1
3997 THEN
3998 ERRCA(1,-1,.LOC_0_VAL,12)
3999 ELSE
4000 NOERR(1);
4001 EXIT_LOOP(1,1);
4002 0
4003 );
4004
4005 !*MESSAGE 1
4006 !*STIMULUS:
4007 !* 8080: WRITE -1 TO MEM LOC 0
4008 !* KS10: WRITE -1 TO AC0 VIA IR AC FIELD
4009 !* LOAD 0 INTO VMA, THEN WRITE 0 TO AC0 VIA VMA
4010 !* 8080: READ MEM LOC 0
4011 !*RESPONSE:
4012 !* MEM LOC 0 SHOULD BE -1
4013
4014 !]ERROR 1
4015 !]MEM_WRITE_N FORCE AC_REF VMA_ALL_N STOP MEM_EN NTWK
4016
4017 !]NO ERROR 1
4018 !]MEM_WRITE_N NTWK
4019
4020 ERROR_LOOP(2)
4021 (
4022 MEM_DEPOSIT(0,-1);
4023 SET_CRAM_ADR(TUA_R);
4024 IF STEP_U_NEXT(3) NEQ 1
4025 THEN
4026 ERRCA(2,0,SERIAL(36),12)
4027 ELSE
4028 NOERR(2);
4029 EXIT_LOOP(2,2);
4030 0
4031 );
4032
4033 !*MESSAGE 2
4034 !*STIMULUS:
4035 !* 8080: WRITE -1 TO MEM LOC 0
4036 !* KS10: WRITE 0 TO AC0 VIA IR AC FIELD
4037 !* LOAD 0 INTO THE VMA, THEN READ AC0 VIA VMA
4038 !*RESPONSE:
4039 !* AC0 SHOULD BE 0
4040
4041 !]ERROR 2
4042 !]MEM_READ_N FORCE AC_REF VMA_ALL_N STOP MEM_EN NTWK
4043
4044 !]NO ERROR 2
4045 !]MEM_READ_N NTWK
4046
4047 END;
4048
4049 GLOBAL ROUTINE TST22: NOVALUE =
4050
4051 !++
4052 ! FUNCTIONAL DESCRIPTION:
4053 !
4054 ! CAUSE ERROR AT M[0] AND ASK MMC WHERE IT WAS REALLY AT
4055 !
4056 !--
4057
4058 BEGIN
4059
4060 LOCAL
4061 MEM_ADR;
4062
4063 LABEL
4064 LOOP1;
4065
4066 BIND
4067 TST_U_ADR = %O'270',
4068 TST_U = PLIT
4069 (
4070 %(0270)% U_J(271) V_DP_0 U_MEM U_N(13012) U,
4071 %(0271)% U_J(272) V_DP_0 U_MEM U_N(2) U,
4072 %(0272)% U_J(273) V_DP_0 U_MEM U_N(43012) U,
4073 %(0273)% U_MEM U_N(2) U
4074 );
4075
4076 LOAD_TST_U;
4077 RPT_ERR_FLAG = 0;
4078 ERROR_LOOP(1)
4079 (
4080 DI(100000,376); ! SET MMC ECC FORCE BITS
4081 SET_CRAM_ADR(TST_U_ADR);
4082 CP(4);
4083 IFN (RD_301 AND %O'100')
4084 THEN
4085 ERRS(1,2,ERRINFO)
4086 ELSE
4087 (
4088 MEM_ADR = EI(100000) AND %O'17777777'; ! GET ERROR ADDRESS
4089 IFN .MEM_ADR
4090 THEN
4091 ERRCAS(1,1,0,.MEM_ADR,8,ERRINFO)
4092 ELSE
4093 NOERR(1);
4094 );
4095 MR(); ! CLEAR FORCE BITS
4096 EXIT_LOOP(1,1);
4097 0
4098 );
4099
4100 RPT_ERR_FLAG = 1;
4101
4102 !*MESSAGE 1
4103 !*STIMULUS:
4104 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
4105 !* (SETTING ALL MMC ECC FORCE BITS)
4106 !* KS10: DEPOSIT 0 TO MEM LOC 0 (WITH WRONG ECC)
4107 !* READ MEM LOC 0 (CAUSING AN ERROR)
4108 !* 8080: READ I/O REGISTER 100000 BITS <14:35>
4109 !*RESPONSE:
4110 !* SHOULD GET 0 (ADDR OF LAST ERROR)
4111
4112 !*MESSAGE 2
4113 !*STIMULUS:
4114 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
4115 !* (SETTING ALL MMC ECC FORCE BITS)
4116 !* KS10: DEPOSIT 0 TO MEM LOC 0 (WITH WRONG ECC)
4117 !* READ MEM LOC 0 (CAUSING AN ERROR)
4118 !*RESPONSE:
4119 !* REFERENCE WAS MADE TO NXM (NOT MEM LOC 0)
4120
4121 !]ERROR 1
4122 !]BUS_ALL BUS_MUX_VMA VMA_ALL_N FORCE AC_REF STOP MEM_EN BUS_REQ MEM_READ_N MEM_WRITE_N NTWK
4123
4124 !]NO ERROR 1
4125 !]MEM_READ_N MEM_WRITE_N BUS_REQ MEM_EN NTWK
4126
4127 END;
4128
4129 GLOBAL ROUTINE TST23: NOVALUE =
4130
4131 !++
4132 ! FUNCTIONAL DESCRIPTION:
4133 !
4134 ! TRY TO READ 0 & -1 FROM MEM LOC 0
4135 !
4136 !--
4137
4138 BEGIN
4139
4140 MACRO
4141 INFO_TUA = 0,0,36,0 %,
4142 INFO_TICKS = 1,0,36,0 %,
4143 INFO_COR = 2,0,36,0 %;
4144
4145 LOCAL
4146 COR,
4147 ACT,
4148 OK;
4149
4150 LABEL
4151 LOOP1,
4152 LOOP2;
4153
4154 BIND
4155 TST_U_ADR = %O'300',
4156 TST_U = PLIT
4157 (
4158 %(0300)% U_J(301) V_DP__1 V_AC_DP U,
4159 %(0301)% U_J(302) V_DP_0 U_MEM U_N(43012) U,
4160 %(0302)% U_MEM U_N(2) U_DBM_MEM U_DBUS_DBM V_DP_D U_DEST_Q_AD U_SKIP_ADEQ0 U,
4161 %(0303)% U_J(304) V_DP_0 V_AC_DP U,
4162 %(0304)% U_J(305) V_DP_0 U_MEM U_N(43012) U,
4163 %(0305)% U_J(306) U_MEM U_N(2) U_DBM_MEM U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
4164 %(0306)% U_A_AR U_LSRC_AQ U_ALU_XOR U_SKIP_ADEQ0 U
4165 ),
4166 TUA_0 = TST_U_ADR + 0,
4167 TUA_1 = TST_U_ADR + 3;
4168
4169 OWN
4170 INFO: BLOCKVECTOR[2,3] INITIAL
4171 (
4172 TUA_0, 3, 0,
4173 TUA_1, 4, -1
4174 );
4175
4176 LOAD_TST_U;
4177 OK = 1;
4178
4179 INCR SUBTEST FROM 0 TO 1 DO
4180 ERROR_LOOP(1)
4181 (
4182 COR = .INFO[.SUBTEST,INFO_COR];
4183 MEM_DEPOSIT(0,NOT .COR);
4184 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
4185 IF STEP_U_NEXT(.INFO[.SUBTEST,INFO_TICKS])
4186 THEN
4187 (
4188 ACT = SERIAL(36);
4189 ERRINFO[0] = .COR;
4190 ERRINFO[1] = NOT .COR;
4191 ERRCAS(1,1,.COR,.ACT,12,ERRINFO);
4192 OK = 0;
4193 );
4194 EXIT_LOOP(1,1);
4195 0
4196 );
4197
4198 IFN .OK THEN NOERR(1);
4199
4200 !*MESSAGE 1
4201 !*STIMULUS:
4202 !* 8080: WRITE \O0 TO MEM LOC 0
4203 !* KS10: WRITE \O1 TO AC0 VIA IR AC FIELD
4204 !* LOAD 0 INTO THE VMA, THEN READ MEM LOC 0
4205 !*RESPONSE:
4206 !* SHOULD GET \O0
4207
4208 !]ERROR 1
4209 !]BUS_R DBM_MEM DBM_SEL_MEM BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_READ_N NTWK
4210
4211 !]NO ERROR 1
4212 !]BUS_R NTWK
4213
4214 END;
4215
4216 GLOBAL ROUTINE TST24: NOVALUE =
4217
4218 !++
4219 ! FUNCTIONAL DESCRIPTION:
4220 !
4221 ! TRY TO WRITE 0 & -1 TO MEM LOC 0
4222 !
4223 !--
4224
4225 BEGIN
4226
4227 MACRO
4228 INFO_TUA = 0,0,36,0 %,
4229 INFO_COR = 1,0,36,0 %;
4230
4231 LOCAL
4232 OK,
4233 COR,
4234 ACT;
4235
4236 LABEL
4237 LOOP1,
4238 LOOP2;
4239
4240 BIND
4241 TST_U_ADR = %O'310',
4242 TST_U = PLIT
4243 (
4244 %(0310)% U_J(311) V_DP_0 U_MEM U_N(13012) U,
4245 %(0311)% V_DP__1 U_MEM U_N(2) U_DBUS_DP U,
4246 %(0312)% U_J(313) V_DP_0 U_MEM U_N(13012) U,
4247 %(0313)% V_DP_0 U_MEM U_N(2) U_DBUS_DP U
4248 ),
4249 TUA_0 = TST_U_ADR + 0,
4250 TUA_1 = TST_U_ADR + 2;
4251
4252 OWN
4253 INFO: BLOCKVECTOR[2,2] INITIAL
4254 (
4255 TUA_0, -1,
4256 TUA_1, 0
4257 );
4258
4259 LOAD_TST_U;
4260 OK = 1;
4261
4262 INCR SUBTEST FROM 0 TO 1 DO
4263 ERROR_LOOP(1)
4264 (
4265 COR = .INFO[.SUBTEST,INFO_COR];
4266 MEM_DEPOSIT(0,.COR);
4267 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
4268 CP(2);
4269 ACT = MEM_EXAMINE(0);
4270 IF .ACT NEQ .COR
4271 THEN
4272 (
4273 ERRINFO[0] = .COR;
4274 ERRCAS(1,1,.COR,.ACT,12,ERRINFO);
4275 OK = 0;
4276 );
4277 EXIT_LOOP(1,1);
4278 0
4279 );
4280
4281 IFN .OK THEN NOERR(1);
4282
4283 !*MESSAGE 1
4284 !*STIMULUS:
4285 !* 8080: WRITE 0 TO MEM LOC 0
4286 !* KS10: WRITE \O0 TO MEM LOC 0
4287 !* 8080: READ MEM LOC 0
4288 !*RESPONSE:
4289 !* SHOULD GET \O0
4290
4291 !]ERROR 1
4292 !]BUS_T BUS_MUX_DP BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_WRITE_N NTWK
4293
4294 !]NO ERROR 1
4295 !]BUS_T BUS_MUX_DP NTWK
4296
4297 END;
4298
4299 GLOBAL ROUTINE TST25: NOVALUE =
4300
4301 !++
4302 ! FUNCTIONAL DESCRIPTION:
4303 !
4304 ! WRITE TO M[2**I] TO CHECK FOR DPM ADDR BITS STUCK LOW
4305 ! HAVE THE 'PHYSICAL' BIT ON TO ALWAYS ACCESS REAL MEMORY
4306 !
4307 !--
4308
4309 BEGIN
4310
4311 LOCAL
4312 LOC,
4313 VAL,
4314 OK;
4315
4316 LABEL
4317 LOOP1;
4318
4319 BIND
4320 TST_U_ADR = %O'320',
4321 TST_U = PLIT
4322 (
4323 %(0320)% U_J(321) V_DP_N(1) U_B_T0 U_DEST_AD U,
4324 %(0321)% U_J(322) V_DP_T0 U_MEM U_N(11016) U,
4325 %(0322)% U_J(323) V_DP__1 U_MEM U_N(2) U,
4326 %(0323)% U_J(321) U_A_T0 U_B_T0 U_LSRC_AB U_ALU_ADD U_DEST_AD U
4327 );
4328
4329 LOAD_TST_U;
4330 OK = 1;
4331 SET_CRAM_ADR(TST_U_ADR);
4332 CP(1);
4333
4334 ERROR_LOOP(1)
4335 (
4336 MEM_DEPOSIT(0,0);
4337 LOC = 1;
4338 WHILE .LOC LEQ .MAX_MEM_ADR DO
4339 (
4340 MEM_DEPOSIT(.LOC,0);
4341 CP(3);
4342 VAL = MEM_EXAMINE(.LOC);
4343 IF .VAL NEQ -1
4344 THEN
4345 (
4346 ERRINFO[0] = .LOC;
4347 ERRINFO[1] = MEM_EXAMINE(0);
4348 ERRCAS(1,1,-1,.VAL,12,ERRINFO);
4349 OK = 0;
4350 MEM_DEPOSIT(0,0);
4351 );
4352 LOC = .LOC ^ 1;
4353 );
4354 EXIT_LOOP(1,1);
4355 0
4356 );
4357
4358 IFN .OK THEN NOERR(1);
4359
4360 !*MESSAGE 1
4361 !*STIMULUS:
4362 !* 8080: WRITE 0 TO MEM LOCS 0, \O0
4363 !* KS10: WRITE -1 TO PHYSICAL EXTENDED MEM LOC \O0
4364 !* 8080: READ MEM LOCS 0, \O0
4365 !*RESPONSE:
4366 !* MEM LOC 0 SHOULD BE 0 (IT IS \O1)
4367 !* MEM LOC \O0 SHOULD BE -1
4368
4369 !]ERROR 1
4370 !]AC_REF FORCE BUS_T BUS_MUX_DP BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_WRITE_N NTWK
4371
4372 !]NO ERROR 1
4373 !] NTWK
4374
4375 END;
4376
4377 GLOBAL ROUTINE TST26: NOVALUE =
4378
4379 !++
4380 ! FUNCTIONAL DESCRIPTION:
4381 !
4382 ! WRITE TO M[2**I] TO CHECK FOR -VMA (AC REF) BITS STUCK LOW
4383 ! HAVE THE 'PHYSICAL' BIT OFF TO ACCESS REAL MEMORY,
4384 ! OR AC 0 IF THE BIT IS STUCK
4385 ! NOTE THAT EXTENDED VMA BITS AREN'T CHECKED
4386 !
4387 !--
4388
4389 BEGIN
4390
4391 LOCAL
4392 LOC,
4393 VAL,
4394 OK;
4395
4396 LABEL
4397 LOOP1;
4398
4399 BIND
4400 TST_U_ADR = %O'330',
4401 TST_U = PLIT
4402 (
4403 %(0330)% U_J(331) V_DP_N(20) U_B_T0 U_DEST_AD U,
4404 %(0331)% U_J(332) V_DP_T0 U_MEM U_N(10016) U,
4405 %(0332)% U_J(333) V_DP__1 U_MEM U_N(2) U,
4406 %(0333)% U_J(331) U_A_T0 U_B_T0 U_LSRC_AB U_ALU_ADD U_DEST_AD U
4407 );
4408
4409 LOAD_TST_U;
4410 OK = 1;
4411 SET_CRAM_ADR(TST_U_ADR);
4412 CP(1);
4413
4414 ERROR_LOOP(1)
4415 (
4416 MEM_DEPOSIT(0,0);
4417 LOC = 16;
4418 WHILE (.LOC LEQ .MAX_MEM_ADR) AND (.LOC LEQ %O'777777') DO
4419 (
4420 MEM_DEPOSIT(.LOC,0);
4421 CP(3);
4422 VAL = MEM_EXAMINE(.LOC);
4423 IF .VAL NEQ -1
4424 THEN
4425 (
4426 ERRINFO[0] = .LOC;
4427 ERRINFO[1] = MEM_EXAMINE(0);
4428 ERRCAS(1,1,-1,.VAL,12,ERRINFO);
4429 OK = 0;
4430 MEM_DEPOSIT(0,0);
4431 );
4432 LOC = .LOC ^ 1;
4433 );
4434 EXIT_LOOP(1,1);
4435 0
4436 );
4437
4438 IFN .OK THEN NOERR(1);
4439
4440 !*MESSAGE 1
4441 !*STIMULUS:
4442 !* 8080: WRITE 0 TO MEM LOCS 0, \O0
4443 !* KS10: WRITE -1 TO EXTENDED MEM LOC \O0
4444 !* 8080: READ MEM LOCS 0, \O0
4445 !*RESPONSE:
4446 !* MEM LOC 0 SHOULD BE 0 (IT IS \O1)
4447 !* MEM LOC \O0 SHOULD BE -1
4448
4449 !]ERROR 1
4450 !]AC_REF FORCE BUS_T BUS_MUX_DP BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_WRITE_N NTWK
4451
4452 !]NO ERROR 1
4453 !] NTWK
4454
4455 END;
4456
4457 GLOBAL ROUTINE TST27: NOVALUE =
4458
4459 !++
4460 ! FUNCTIONAL DESCRIPTION:
4461 !
4462 ! DO MEMORY CYCLES AND TRY TO CAPTURE THE 'MEM' BITS
4463 ! LOAD THEM FROM THE MAGIC NUMBER FIELD (#)
4464 !
4465 !--
4466
4467 BEGIN
4468
4469 MACRO
4470 INFO_TUA = 0,0,36,0 %,
4471 INFO_COR = 1,0,36,0 %,
4472 INFO_NAM = 2,0,36,0 %;
4473
4474 LOCAL
4475 COR,
4476 ACT,
4477 ALL_DIF;
4478
4479 LABEL
4480 LOOP1;
4481
4482 BIND
4483 TST_U_ADR = %O'340',
4484 TST_U = PLIT
4485 (
4486 %(0340)% U_MEM U_N(2) U_DBM_VMA U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
4487 %(0341)% U_J(340) V_DP_0 U_MEM U_N(11012) U,
4488 %(0342)% U_J(340) V_DP_0 U_MEM U_N(43012) U,
4489 %(0343)% U_J(340) V_DP_0 U_MEM U_N(21012) U
4490 ),
4491 TUA_W = TST_U_ADR + 1,
4492 TUA_R = TST_U_ADR + 2,
4493 TUA_WT = TST_U_ADR + 3;
4494
4495 OWN
4496 INFO: BLOCKVECTOR[3,3] INITIAL
4497 (
4498 TUA_W, %O'04', UPLIT(%ASCIZ 'WRITE'),
4499 TUA_R, %O'21', UPLIT(%ASCIZ 'READ'),
4500 TUA_WT, %O'10', UPLIT(%ASCIZ 'WRITE TEST')
4501 );
4502
4503 LOAD_TST_U;
4504 ALL_DIF = 0;
4505
4506 INCR SUBTEST FROM 0 TO 2 DO
4507 ERROR_LOOP(1)
4508 (
4509 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
4510 CP(2);
4511 ACT = SERIAL(8) AND %O'37';
4512 COR = .INFO[.SUBTEST,INFO_COR];
4513 IF .COR NEQ .ACT
4514 THEN
4515 (
4516 ERRINFO[0] = .INFO[.SUBTEST,INFO_NAM];
4517 ERMCAS(1,.COR,.ACT,2,ERRINFO);
4518 ALL_DIF = .ALL_DIF OR (.COR XOR .ACT);
4519 INCR ERRN FROM 0 TO 4 DO
4520 IF .COR<.ERRN,1> NEQ .ACT<.ERRN,1>
4521 THEN
4522 FAILURE(.ERRN + 1);
4523 );
4524 INCR ERRN FROM 1 TO 5 DO
4525 EXIT_LOOP(1,.ERRN);
4526 0
4527 );
4528
4529 INCR ERRN FROM 0 TO 4 DO
4530 IF .ALL_DIF<.ERRN,1> EQL 0 THEN NOERR(.ERRN + 1);
4531
4532 !*MESSAGE 1
4533 !*STIMULUS:
4534 !* \S0 TO MEM LOC 0 CONTROLLED BY #
4535 !*RESPONSE:
4536 !* READ VMA DURING MEMORY CYCLE
4537 !* CORRECT & ACTUAL ARE VMA<3:7>
4538
4539 !]ERROR 1
4540 !]DBM_VMA_MEM DBM_SEL_VMA MEM_CAC_INH_N NTWK
4541
4542 !]NO ERROR 1
4543 !]MEM_CAC_INH_N NTWK
4544
4545 !]ERROR 2
4546 !]DBM_VMA_MEM DBM_SEL_VMA NTWK
4547
4548 !]NO ERROR 2
4549 !] NTWK
4550
4551 !]ERROR 3
4552 !]DBM_VMA_MEM DBM_SEL_VMA MEM_WRITE_N NTWK
4553
4554 !]NO ERROR 3
4555 !]MEM_WRITE_N NTWK
4556
4557 !]ERROR 4
4558 !]DBM_VMA_MEM DBM_SEL_VMA MEM_WR_TEST_N NTWK
4559
4560 !]NO ERROR 4
4561 !]MEM_WR_TEST_N NTWK
4562
4563 !]ERROR 5
4564 !]DBM_VMA_MEM DBM_SEL_VMA MEM_READ_N NTWK
4565
4566 !]NO ERROR 5
4567 !]MEM_READ_N NTWK
4568
4569 END;
4570
4571 GLOBAL ROUTINE TST28: NOVALUE =
4572
4573 !++
4574 ! FUNCTIONAL DESCRIPTION:
4575 !
4576 ! DO MEMORY CYCLES AND TRY TO CAPTURE THE 'MEM' BITS
4577 ! LOAD THEM FROM THE DATA PATH
4578 !
4579 !--
4580
4581 BEGIN
4582
4583 MACRO
4584 INFO_TUA = 0,0,36,0 %,
4585 INFO_COR = 1,0,36,0 %,
4586 INFO_NAM = 2,0,36,0 %;
4587
4588 LOCAL
4589 COR,
4590 ACT,
4591 ALL_DIF;
4592
4593 LABEL
4594 LOOP1;
4595
4596 BIND
4597 TST_U_ADR = %O'350',
4598 TST_U = PLIT
4599 (
4600 %(0350)% U_J(351) U_A_BRX U_B_T0 U_LSRC_0B U_RSRC_0A U_ALU_OR U_MEM U_N(32) U,
4601 %(0351)% U_MEM U_N(2) U_DBM_VMA U_DBUS_DBM V_DP_D U_DEST_Q_AD U,
4602 %(0352)% U_J(350) U_DBM_N U_DBUS_DBM V_DP_D U_B_T0 U_DEST_AD U_N(11000) U,
4603 %(0353)% U_J(350) U_DBM_N U_DBUS_DBM V_DP_D U_B_T0 U_DEST_AD U_N(43000) U,
4604 %(0354)% U_J(350) U_DBM_N U_DBUS_DBM V_DP_D U_B_T0 U_DEST_AD U_N(21000) U
4605 ),
4606 TUA_W = TST_U_ADR + 2,
4607 TUA_R = TST_U_ADR + 3,
4608 TUA_WT = TST_U_ADR + 4;
4609
4610 OWN
4611 INFO: BLOCKVECTOR[3,3] INITIAL
4612 (
4613 TUA_W, %O'04', UPLIT(%ASCIZ 'WRITE'),
4614 TUA_R, %O'21', UPLIT(%ASCIZ 'READ'),
4615 TUA_WT, %O'10', UPLIT(%ASCIZ 'WRITE TEST')
4616 );
4617
4618 LOAD_TST_U;
4619 ALL_DIF = 0;
4620
4621 INCR SUBTEST FROM 0 TO 2 DO
4622 ERROR_LOOP(1)
4623 (
4624 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
4625 CP(3);
4626 ACT = SERIAL(8) AND %O'37';
4627 COR = .INFO[.SUBTEST,INFO_COR];
4628 IF .COR NEQ .ACT
4629 THEN
4630 (
4631 ERRINFO[0] = .INFO[.SUBTEST,INFO_NAM];
4632 ERMCAS(1,.COR,.ACT,2,ERRINFO);
4633 ALL_DIF = .ALL_DIF OR (.COR XOR .ACT);
4634 INCR ERRN FROM 0 TO 4 DO
4635 IF .COR<.ERRN,1> NEQ .ACT<.ERRN,1>
4636 THEN
4637 FAILURE(.ERRN + 1);
4638 );
4639 INCR ERRN FROM 1 TO 5 DO
4640 EXIT_LOOP(1,.ERRN);
4641 0
4642 );
4643
4644 INCR ERRN FROM 0 TO 4 DO
4645 IF .ALL_DIF<.ERRN,1> EQL 0 THEN NOERR(.ERRN + 1);
4646
4647 !*MESSAGE 1
4648 !*STIMULUS:
4649 !* \S0 TO MEM LOC 0 CONTROLLED BY DP
4650 !*RESPONSE:
4651 !* READ VMA DURING MEMORY CYCLE
4652 !* CORRECT & ACTUAL ARE VMA<3:7>
4653
4654 !]ERROR 1
4655 !]DBM_VMA_MEM DBM_SEL_VMA MEM_CAC_INH_DP NTWK
4656
4657 !]NO ERROR 1
4658 !]MEM_CAC_INH_DP NTWK
4659
4660 !]ERROR 2
4661 !]DBM_VMA_MEM DBM_SEL_VMA NTWK
4662
4663 !]NO ERROR 2
4664 !] NTWK
4665
4666 !]ERROR 3
4667 !]DBM_VMA_MEM DBM_SEL_VMA MEM_WRITE_DP NTWK
4668
4669 !]NO ERROR 3
4670 !]MEM_WRITE_DP NTWK
4671
4672 !]ERROR 4
4673 !]DBM_VMA_MEM DBM_SEL_VMA MEM_WR_TEST_DP NTWK
4674
4675 !]NO ERROR 4
4676 !]MEM_WR_TEST_DP NTWK
4677
4678 !]ERROR 5
4679 !]DBM_VMA_MEM DBM_SEL_VMA MEM_READ_DP NTWK
4680
4681 !]NO ERROR 5
4682 !]MEM_READ_DP NTWK
4683
4684 END;
4685
4686 GLOBAL ROUTINE TST29: NOVALUE =
4687
4688 !++
4689 ! FUNCTIONAL DESCRIPTION:
4690 !
4691 ! START MEMORY CYCLES AND TRY TO CAPTURE THE 'MEM' BITS
4692 ! LOAD THEM FROM THE DROM
4693 ! DROM[124] = 0300,1567,0100
4694 ! DROM[277] = 0017,1561,1700
4695 !
4696 !--
4697
4698 BEGIN
4699
4700 MACRO
4701 INFO_TUA = 0,0,36,0 %,
4702 INFO_COR = 1,0,36,0 %,
4703 INFO_OPCODE = 2,0,36,0 %;
4704
4705 LOCAL
4706 COR,
4707 ACT,
4708 ALL_DIF;
4709
4710 LABEL
4711 LOOP1;
4712
4713 BIND
4714 TST_U_ADR = %O'360',
4715 TST_U = PLIT
4716 (
4717 %(0360)% U_J(362) U_N(277000) U_DBM_N U_DBUS_DBM U_SPEC_LOADIR U,
4718 %(0361)% U_J(362) U_N(124000) U_DBM_N U_DBUS_DBM U_SPEC_LOADIR U,
4719 %(0362)% U_J(363) U_N(42) U_MEM V_DP_0 U,
4720 %(0363)% U_SPEC_MEMCLR U_DBM_VMA U_DBUS_DBM V_DP_D U_DEST_Q_AD U
4721 ),
4722 TUA_0 = TST_U_ADR + 0,
4723 TUA_1 = TST_U_ADR + 1;
4724
4725 OWN
4726 INFO: BLOCKVECTOR[2,3] INITIAL
4727 (
4728 TUA_0, %O'30', %O'277',
4729 TUA_1, %O'00', %O'124'
4730 );
4731
4732 LOAD_TST_U;
4733 ALL_DIF = 0;
4734
4735 INCR SUBTEST FROM 0 TO 1 DO
4736 ERROR_LOOP(1)
4737 (
4738 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
4739 CP(3);
4740 ACT = SERIAL(8) AND %O'37';
4741 COR = .INFO[.SUBTEST,INFO_COR];
4742 IF .COR NEQ .ACT
4743 THEN
4744 (
4745 ERRINFO[0] = .INFO[.SUBTEST,INFO_OPCODE];
4746 ERMCAS(1,.COR,.ACT,2,ERRINFO);
4747 ALL_DIF = .ALL_DIF OR (.COR XOR .ACT);
4748 INCR ERRN FROM 0 TO 4 DO
4749 IF .COR<.ERRN,1> NEQ .ACT<.ERRN,1>
4750 THEN
4751 FAILURE(.ERRN + 1);
4752 );
4753 INCR ERRN FROM 1 TO 5 DO
4754 EXIT_LOOP(1,.ERRN);
4755 0
4756 );
4757
4758 INCR ERRN FROM 0 TO 4 DO
4759 IF .ALL_DIF<.ERRN,1> EQL 0 THEN NOERR(.ERRN + 1);
4760
4761 !*MESSAGE 1
4762 !*STIMULUS:
4763 !* LOAD OPCODE \O0 INTO THE IR
4764 !* START A MEMORY CYCLE CONTROLLED BY DROM
4765 !* ABORT THE MEMORY CYCLE
4766 !*RESPONSE:
4767 !* READ VMA DURING MEMORY CYCLE
4768 !* CORRECT & ACTUAL ARE VMA<3:7>
4769
4770 !]ERROR 1
4771 !]DBM_VMA_MEM DBM_SEL_VMA MEM_CAC_INH_DRO NTWK
4772
4773 !]NO ERROR 1
4774 !]MEM_CAC_INH_DRO NTWK
4775
4776 !]ERROR 2
4777 !]DBM_VMA_MEM DBM_SEL_VMA NTWK
4778
4779 !]NO ERROR 2
4780 !] NTWK
4781
4782 !]ERROR 3
4783 !]DBM_VMA_MEM DBM_SEL_VMA MEM_WRITE_DRO NTWK
4784
4785 !]NO ERROR 3
4786 !]MEM_WRITE_DRO NTWK
4787
4788 !]ERROR 4
4789 !]DBM_VMA_MEM DBM_SEL_VMA MEM_WR_TEST_DRO NTWK
4790
4791 !]NO ERROR 4
4792 !]MEM_WR_TEST_DRO NTWK
4793
4794 !]ERROR 5
4795 !]DBM_VMA_MEM DBM_SEL_VMA MEM_READ_DRO NTWK
4796
4797 !]NO ERROR 5
4798 !]MEM_READ_DRO NTWK
4799
4800 END;
4801
4802 GLOBAL ROUTINE TST30: NOVALUE =
4803
4804 !++
4805 ! FUNCTIONAL DESCRIPTION:
4806 !
4807 ! CHECK STUCK BITS ON E612 WHICH GENERATES DPM5 MEM EN L
4808 ! DROM[124] = 0300,1567,0100
4809 ! DROM[277] = 0017,1561,1700
4810 !
4811 !--
4812
4813 BEGIN
4814
4815 MACRO
4816 INFO_INI_ADR = 0,0,36,0 %,
4817 INFO_TST_ADR = 1,0,36,0 %,
4818 INFO_N = 2,0,36,0 %,
4819 INFO_MEM = 3,0,36,0 %,
4820 INFO_COND = 4,0,36,0 %,
4821 INFO_CORR = 5,0,36,0 %;
4822
4823 LABEL
4824 LOOP1;
4825
4826 BIND
4827 TST_U_ADR = %O'370',
4828 TST_U = PLIT
4829 (
4830 %(0370)% U_N(277000) U_DBM_N U_DBUS_DBM U_SPEC_LOADIR U,
4831 %(0371)% U_N(124000) U_DBM_N U_DBUS_DBM U_SPEC_LOADIR U,
4832 %(0372)% U_J(373) V_DP_0 U_MEM U_N(13011) U,
4833 %(0373)% V_DP_0 U_MEM U_N(1) U,
4834 %(0374)% U_J(375) V_DP_0 U_N(13013) U,
4835 %(0375)% V_DP_0 U_N(3) U,
4836 %(0376)% U_J(377) V_DP_0 U_MEM U_N(13010) U,
4837 %(0377)% V_DP_0 U_MEM U_N(0) U,
4838 %(0400)% U_J(401) V_DP_0 U_MEM U_N(13012) U,
4839 %(0401)% V_DP_0 U_MEM U_N(2) U
4840 ),
4841 TUA = TST_U_ADR;
4842
4843 LOCAL
4844 OK,
4845 VAL;
4846
4847 OWN
4848 INFO: BLOCKVECTOR[5,6] INITIAL
4849 (
4850 TUA+0, TUA+2, %O'13011', 1, 1, 0,
4851 0, TUA+4, %O'13013', 0, 1, -1,
4852 0, TUA+6, %O'13010', 1, 1, -1,
4853 TUA+1, TUA+4, %O'13011', 1, 0, -1,
4854 0, TUA+8, %O'13012', 1, 0, 0
4855 );
4856
4857 LOAD_TST_U;
4858 OK = 1;
4859
4860 INCR ERRN FROM 0 TO 4 DO
4861 ERROR_LOOP(1)
4862 (
4863 IFN .INFO[.ERRN,INFO_INI_ADR]
4864 THEN
4865 (
4866 SET_CRAM_ADR(.INFO[.ERRN,INFO_INI_ADR]);
4867 CP(2); ! EXTRA CLOCK PULSE NEEDED
4868 );
4869 MEM_DEPOSIT(0,-1);
4870 SET_CRAM_ADR(.INFO[.ERRN,INFO_TST_ADR]);
4871 CP(2);
4872 VAL = MEM_EXAMINE(0);
4873 IF .VAL NEQ .INFO[.ERRN,INFO_CORR]
4874 THEN
4875 (
4876 ERRINFO[0] = .INFO[.ERRN,INFO_N];
4877 ERRINFO[1] = .INFO[.ERRN,INFO_MEM];
4878 ERRINFO[2] = .INFO[.ERRN,INFO_COND];
4879 ERRINFO[3] = .INFO[.ERRN,INFO_CORR];
4880 ERRCAS(1,1,.INFO[.ERRN,INFO_CORR],.VAL,12,ERRINFO);
4881 OK = 0;
4882 );
4883 EXIT_LOOP(1,1);
4884 0
4885 );
4886
4887 IFN .OK THEN NOERR(1);
4888
4889 !*MESSAGE 1
4890 !*STIMULUS:
4891 !* 8080: WRITE -1 TO MEM LOC 0
4892 !* KS10: CONDITIONALLY WRITE 0 TO MEM LOC 0
4893 !* TO START CYCLE, #=\O0, MEM=\O1, DROM COND FUNC=\O2
4894 !* 8080: READ MEM LOC 0
4895 !*RESPONSE:
4896 !* MEM LOC 0 SHOULD BE \O3
4897
4898 !]ERROR 1
4899 !]N_ALL BUS_ALL BUS_MUX_VMA BUS_MUX_DP VMA_ALL_N MEM_WRITE_N MEM_CAC_INH_N FORCE AC_REF MEM_EN NTWK
4900
4901 !]NO ERROR 1
4902 !]MEM_EN NTWK
4903
4904 END;
4905
4906 GLOBAL ROUTINE TST31: NOVALUE =
4907
4908 !++
4909 ! FUNCTIONAL DESCRIPTION:
4910 !
4911 ! TEST BUS REQUEST INPUT TO DPM MUX SEL 2 FOR STUCK HIGH/LOW
4912 !
4913 !--
4914
4915 BEGIN
4916
4917 LOCAL
4918 VAL,
4919 LOC,
4920 OK;
4921
4922 LABEL
4923 LOOP1;
4924
4925 BIND
4926 TST_U_ADR = %O'410',
4927 TST_U = PLIT
4928 (
4929 %(0410)% U_J(412) V_DP_N(1) U_B_T0 U_DEST_AD U,
4930 %(0411)% U_J(412) U_A_T0 U_B_T0 U_LSRC_AB U_ALU_ADD U_DEST_AD U,
4931 %(0412)% U_J(413) V_DP_0 U_MEM U_N(13012) U,
4932 %(0413)% U_J(412) V_DP_T0 U_MEM U_N(2) U
4933 ),
4934 TUA_NXT = TST_U_ADR + 1;
4935
4936 LOAD_TST_U;
4937 OK = 1;
4938 SET_CRAM_ADR(TST_U_ADR);
4939 CP(1);
4940 LOC = 1;
4941
4942 WHILE .LOC LEQ .MAX_MEM_ADR DO
4943 ERROR_LOOP(1)
4944 (
4945 ERRINFO[0] = .LOC;
4946 MEM_DEPOSIT(0,-1);
4947 MEM_DEPOSIT(.LOC,-1);
4948 CP(2);
4949
4950 VAL = MEM_EXAMINE(0);
4951 IF .VAL NEQ .LOC
4952 THEN
4953 (
4954 ERRCAS(1,1,.LOC,.VAL,12,ERRINFO);
4955 OK = 0;
4956 );
4957 EXIT_LOOP(1,1);
4958
4959 VAL = MEM_EXAMINE(.LOC);
4960 IF .VAL NEQ -1
4961 THEN
4962 (
4963 ERRCAS(1,2,-1,.VAL,12,ERRINFO);
4964 OK = 0;
4965 );
4966 EXIT_LOOP(1,2);
4967
4968 LOC = .LOC ^ 1;
4969 SET_CRAM_ADR(TUA_NXT);
4970 CP(1);
4971 0
4972 );
4973
4974 IFN .OK THEN NOERR(1);
4975
4976 !*MESSAGE 1
4977 !*STIMULUS:
4978 !* 8080: WRITE -1 TO MEM LOCS 0, \O0
4979 !* KS10: WRITE \O0 TO MEM LOC 0
4980 !* 8080: READ MEM LOC 0
4981 !*RESPONSE:
4982 !* MEM LOC 0 SHOULD BE \O0
4983
4984 !*MESSAGE 2
4985 !*STIMULUS:
4986 !* 8080: WRITE -1 TO MEM LOCS 0, \O0
4987 !* KS10: WRITE 1 TO MEM LOC 0
4988 !* 8080: READ MEM LOC \O0
4989 !*RESPONSE:
4990 !* MEM LOC \O0 SHOULD BE -1
4991
4992 !]ERROR 1
4993 !]BUS_REQ_A BUS_ALL BUS_MUX_VMA BUS_MUX_DP VMA_ALL_N MEM_WRITE_N MEM_CAC_INH_N FORCE AC_REF MEM_EN NTWK
4994
4995 !]NO ERROR 1
4996 !]BUS_REQ_A NTWK
4997
4998 END;
4999
5000 GLOBAL ROUTINE TST32: NOVALUE =
5001
5002 !++
5003 ! FUNCTIONAL DESCRIPTION:
5004 !
5005 ! TEST PAGE TABLE DATA INPUTS/OUTPUTS AND DPM MUX ADDRESS INPUTS
5006 ! CAUSE ECC ERROR AT VMA 377777 AND THEN 777777
5007 ! MAPPED TO PMA 777, 1777, 2777, 4777, ..., MAX_MEM_ADR
5008 ! THIS ALSO CHECKS PAGE FAIL LOGIC (WRITABLE AND WRITE-TEST ON)
5009 !
5010 !--
5011
5012 BEGIN
5013
5014 LOCAL
5015 OK,
5016 VMA,
5017 CURR_PAGE,
5018 NEXT_PAGE,
5019 COR_MEM_ADR,
5020 ACT_MEM_ADR,
5021 CRAM_ADR;
5022
5023 LABEL
5024 LOOP1;
5025
5026 BIND
5027 TST_U_ADR = %O'420',
5028 TST_U = PLIT
5029 (
5030 %(0420)% U_J(422) V_DP_N(377777) U_B_T0 U_DEST_AD U,
5031 %(0421)% U_J(422) V_DP_N(777777) U_B_T0 U_DEST_AD U,
5032 %(0422)% U_J(423) V_DP_T0 U_MEM U_N(3010) U_SPEC_LDPAGE U,
5033 %(0423)% U_J(0) V_DP_N(440000) U, ! J, #<6:17> CHANGE
5034 %(0424)% U_J(425) V_DP_T0 U_MEM U_N(32012) U,
5035 %(0425)% U_J(426) V_DP_0 U_MEM U_N(2) U,
5036 %(0426)% U_J(427) V_DP_T0 U_MEM U_N(42012) U,
5037 %(0427)% U_J(0) U_MEM U_N(2) U ! J CHANGES
5038 ),
5039 TUA_PAG = TST_U_ADR + 3, ! WHERE TO DIDDLE PAGE MAP
5040 TUA_PE1 = TST_U_ADR + 3, ! WHERE TO ENABLE PAGING
5041 TUA_CONT = TST_U_ADR + 4, ! WHERE TO CONTINUE AFTER THAT
5042 TUA_PE0 = TST_U_ADR + 7; ! WHERE TO DISABLE PAGING
5043
5044 LOAD_TST_U;
5045 SET_CRAM_ADR(TUA_PE1);
5046 MOD_FLD(0,PE1_ADR);
5047 SET_CRAM_ADR(TUA_PE0);
5048 MOD_FLD(0,PE0_ADR);
5049
5050 RPT_ERR_FLAG = 0;
5051 OK = 1;
5052 CURR_PAGE = 0; ! START AT PAGE 0
5053 NEXT_PAGE = %O'1000'; ! NEXT PAGE WILL BE 1
5054 WHILE .CURR_PAGE LEQ .MAX_MEM_ADR DO
5055 (
5056 VMA = %O'377777'; ! DO VMA<18> = 0 SIDE FIRST
5057 ERRINFO[0] = COR_MEM_ADR = .CURR_PAGE OR %O'777';
5058 ERRINFO[1] = %O'440000' OR (.CURR_PAGE^(-9));
5059 SET_CRAM_ADR(TUA_PAG); ! U-WORD TO DIDDLE TO
5060 MOD_FLD(3,.CURR_PAGE^(-9)); ! DO THIS PHYSICAL PAGE
5061 INCR PAIR_SIDE FROM 0 TO 1 DO
5062 (
5063 ERRINFO[2] = .VMA;
5064 ERRINFO[3] = .VMA ^ (-9); ! PAGE NUMBER
5065 ERROR_LOOP(1)
5066 (
5067 DI(100000,376); ! SET MMC FORCE BITS
5068 SET_CRAM_ADR(TST_U_ADR+.PAIR_SIDE); ! START FOR THIS SIDE
5069 CP(5); ! SET UP & ENABLE PAGING
5070 SET_CRAM_ADR(TUA_CONT); ! COME BACK TO WORK...
5071 CP(6); ! AND DISABLE PAGING
5072 CRAM_ADR = STEP_U_NEXT(9); ! DO IT AND CHECK...
5073 IF .CRAM_ADR EQL O7777 ! IF -1 WE HAD PAGE FAIL
5074 THEN
5075 (
5076 ERRINFO[4] = PF_TRAP();
5077 ERRINFO[5] = PF_NAME(.ERRINFO[4]);
5078 ERRS(1,1,ERRINFO);
5079 OK = 0;
5080 )
5081 ELSE
5082 IFN (RD_301 AND %O'100') ! IF BIT SET WE HIT NXM
5083 THEN
5084 (
5085 ERRS(1,2,ERRINFO);
5086 OK = 0;
5087 MR(); ! CLEAR MMC ERR HOLD BIT
5088 )
5089 ELSE
5090 (
5091 ACT_MEM_ADR = EI(100000) AND %O'17777777'; ! ERR ADDR
5092 MR(); ! CLEAR MMC ERR HOLD BIT
5093 IF .ACT_MEM_ADR NEQ .COR_MEM_ADR
5094 THEN
5095 (
5096 ERRCAS(1,3,.COR_MEM_ADR,.ACT_MEM_ADR,8,ERRINFO);
5097 OK = 0;
5098 );
5099 );
5100 EXIT_LOOP(1,1);
5101 0
5102 );
5103 VMA = %O'777777'; ! DO OTHER SIDE OF RAMS
5104 );
5105 CURR_PAGE = .NEXT_PAGE;
5106 NEXT_PAGE = .NEXT_PAGE ^ 1;
5107 );
5108
5109 IFN .OK THEN NOERR(1);
5110
5111 RPT_ERR_FLAG = 1;
5112
5113 !*MESSAGE 1
5114 !*STIMULUS:
5115 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
5116 !* (SETTING ALL MMC ECC FORCE BITS)
5117 !* KS10: LOAD \O1 INTO PAGE TABLE LOC \O3
5118 !* DEPOSIT 0 TO VIRTUAL MEM LOC \O2 (WITH WRONG ECC)
5119 !* READ VIRTUAL MEM LOC \O2 (CAUSING AN ERROR)
5120 !*RESPONSE:
5121 !* PAGE FAIL U-TRAP TO CRAM ADDR 7777 (SHOULDN'T HAPPEN)
5122 !* PAGE FAIL CODE \O4 (\S5)
5123
5124 !*MESSAGE 2
5125 !*STIMULUS:
5126 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
5127 !* (SETTING ALL MMC ECC FORCE BITS)
5128 !* KS10: LOAD \O1 INTO PAGE TABLE LOC \O3
5129 !* DEPOSIT 0 TO VIRTUAL MEM LOC \O2 (WITH WRONG ECC)
5130 !* READ VIRTUAL MEM LOC \O2 (CAUSING AN ERROR)
5131 !*RESPONSE:
5132 !* REFERENCE WAS MADE TO NXM (NOT MEM LOC 0)
5133
5134 !*MESSAGE 3
5135 !*STIMULUS:
5136 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
5137 !* (SETTING ALL MMC ECC FORCE BITS)
5138 !* KS10: LOAD \O1 INTO PAGE TABLE LOC \O3
5139 !* DEPOSIT 0 TO VIRTUAL MEM LOC \O2 (WITH WRONG ECC)
5140 !* READ VIRTUAL MEM LOC \O2 (CAUSING AN ERROR)
5141 !* 8080: READ I/O REGISTER 100000 BITS <14:35>
5142 !*RESPONSE:
5143 !* SHOULD GET \O0 (PHYSICAL ADDR OF LAST ERROR)
5144
5145 !]ERROR 1
5146 !]PT_IO PT_VAL_WRT PT_USR PT_MESS N_ALL NTWK
5147
5148 !]NO ERROR 1
5149 !]PT_IO NTWK
5150
5151 END;
5152
5153 GLOBAL ROUTINE TST33: NOVALUE =
5154
5155 !++
5156 ! FUNCTIONAL DESCRIPTION:
5157 !
5158 ! TEST PAGE TABLE ADDRESS LINES
5159 ! CAUSE ECC ERROR ON PAGES 0,1,2,4,10,20,40,100,200
5160 ! MAPPED TO PHYSICAL PAGES 0,1,2,3,4,5,6,7,10
5161 ! FOR EACH SIDE OF THE RAM PAIRS (+0,+400)
5162 !
5163 !--
5164
5165 BEGIN
5166
5167 LOCAL
5168 PTE,
5169 VMA,
5170 COR_PMA,
5171 ACT_PMA,
5172 OK;
5173
5174 OWN
5175 INFO: VECTOR[18] INITIAL ! VIRTUAL PAGE NUMBERS TO TEST
5176 (
5177 %O'000', %O'400',
5178 %O'001', %O'401',
5179 %O'002', %O'402',
5180 %O'004', %O'404',
5181 %O'010', %O'410',
5182 %O'020', %O'420',
5183 %O'040', %O'440',
5184 %O'100', %O'500',
5185 %O'200', %O'600'
5186 );
5187
5188 LABEL
5189 LOOP1;
5190
5191 BIND
5192 TST_U_ADR = %O'440',
5193 TST_U = PLIT
5194 (
5195 %(0440)% U_J(0) V_DP_N(0) U_B_T0 U_DEST_AD U, ! J, #<0:17> CHANGE
5196 %(0441)% U_J(442) V_DP_T0 U_MEM U_N(3010) U_SPEC_LDPAGE U,
5197 %(0442)% V_DP_N(440000) U, ! #<6:17> CHANGES
5198 %(0443)% U_J(444) V_DP_T0 U_MEM U_N(12012) U,
5199 %(0444)% U_J(445) V_DP_0 U_MEM U_N(2) U,
5200 %(0445)% U_J(446) V_DP_T0 U_MEM U_N(42012) U,
5201 %(0446)% U_MEM U_N(2) U
5202 ),
5203 TUA_VMA = TST_U_ADR + 0, ! WHERE TO DIDDLE VMA TO USE
5204 TUA_PAG = TST_U_ADR + 2, ! WHERE TO DIDDLE PAGE MAP
5205 TUA_TST = TST_U_ADR + 3; ! WHERE TO START TEST ITSELF
5206
5207 LOAD_TST_U;
5208 RPT_ERR_FLAG = 0;
5209 OK = 1;
5210
5211 SET_CRAM_ADR(TUA_VMA); ! FIX J FIELD FOR LOADING
5212 MOD_FLD(0,TUA_VMA+1); ! THE PAGE TABLE
5213
5214 INCR ERRN FROM 0 TO 17 DO ! LOAD THE PAGE TABLE
5215 (
5216 VMA = (.INFO[.ERRN] ^ 9) + %O'777';
5217 PTE = %O'440000' OR .ERRN;
5218 SET_CRAM_ADR(TUA_PAG);
5219 MOD_FLD(3,.PTE<N_FLD3>); ! DIDDLE #<6:17>
5220 SET_CRAM_ADR(TUA_VMA);
5221 MOD_FLD(3,.VMA<N_FLD3>); ! DIDDLE #<6:17>
5222 MOD_FLD(4,.VMA<N_FLD4>); ! DIDDLE #<0:5>; ZAP OTHER BITS
5223 CP(4); ! STUFF THE ENTRY IN THE PAGE TABLE
5224 ! EXTRA CLOCK PULSE NEEDED (REALLY!!!)
5225 );
5226
5227 PAGING_ON;
5228
5229 SET_CRAM_ADR(TUA_VMA); ! FIX J FIELD FOR
5230 MOD_FLD(0,TUA_TST); ! THE TESTS
5231
5232 INCR ERRN FROM 0 TO 17 DO ! DO THE TESTS
5233 (
5234 ERRINFO[0] = COR_PMA = (.ERRN ^ 9) + %O'777';
5235 ERRINFO[1] = VMA = (.INFO[.ERRN] ^ 9) + %O'777';
5236 ERRINFO[2] = PTE = %O'440000' OR .ERRN;
5237 ERRINFO[3] = .INFO[.ERRN];
5238 SET_CRAM_ADR(TUA_VMA);
5239 MOD_FLD(3,.VMA<N_FLD3>); ! DIDDLE #<6:17>
5240 MOD_FLD(4,.VMA<N_FLD4>); ! DIDDLE #<0:5>; ZAP OTHER BITS
5241 ERROR_LOOP(1)
5242 (
5243 DI(100000,376); ! SET MMC FORCE BITS
5244 SET_CRAM_ADR(TUA_VMA);
5245 ! EXTRA CLOCK PULSE NEEDED...
5246 IF STEP_U_NEXT(6) EQL O7777 ! IF -1 WE HAD PAGE FAIL
5247 THEN
5248 (
5249 ERRINFO[4] = PF_TRAP();
5250 ERRINFO[5] = PF_NAME(.ERRINFO[4]);
5251 ERRS(1,1,ERRINFO);
5252 PAGING_ON;
5253 )
5254 ELSE
5255 IFN (RD_301 AND %O'100') ! IF BIT SET WE HIT NXM
5256 THEN
5257 (
5258 ERRS(1,2,ERRINFO);
5259 MR(); ! CLEAR MMC ERR HOLD BIT
5260 )
5261 ELSE
5262 (
5263 ACT_PMA = EI(100000) AND %O'17777777'; ! ERR ADDR
5264 MR(); ! CLEAR MMC ERR HOLD BIT
5265 IF .ACT_PMA NEQ .COR_PMA
5266 THEN
5267 (
5268 ERRCAS(1,3,.COR_PMA,.ACT_PMA,8,ERRINFO);
5269 OK = 0;
5270 );
5271 );
5272 EXIT_LOOP(1,1);
5273 0
5274 );
5275 );
5276
5277 IFN .OK THEN NOERR(1);
5278
5279 PAGING_OFF;
5280 RPT_ERR_FLAG = 1;
5281
5282 !*MESSAGE 1
5283 !*STIMULUS:
5284 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
5285 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
5286 !* (SETTING ALL MMC ECC FORCE BITS)
5287 !* KS10: DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC)
5288 !* READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR)
5289 !*RESPONSE:
5290 !* PAGE FAIL U-TRAP TO CRAM ADDR 7777 (SHOULDN'T HAPPEN)
5291 !* PAGE FAIL CODE \O4 (\S5)
5292
5293 !*MESSAGE 2
5294 !*STIMULUS:
5295 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
5296 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
5297 !* (SETTING ALL MMC ECC FORCE BITS)
5298 !* KS10: DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC)
5299 !* READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR)
5300 !*RESPONSE:
5301 !* REFERENCE WAS MADE TO NXM (NOT MEM LOC 0)
5302
5303 !*MESSAGE 3
5304 !*STIMULUS:
5305 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
5306 !* 8080: DEPOSIT 376 TO I/O REGISTER 100000
5307 !* (SETTING ALL MMC ECC FORCE BITS)
5308 !* KS10: DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC)
5309 !* READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR)
5310 !* 8080: READ I/O REGISTER 100000 BITS <14:35>
5311 !*RESPONSE:
5312 !* SHOULD GET \O0 (PHYSICAL ADDR OF LAST ERROR)
5313
5314 !]ERROR 1
5315 !]PT_ADR PT_IO PT_VAL_WRT PT_USR PT_MESS N_ALL NTWK
5316
5317 !]NO ERROR 1
5318 !]PT_ADR SPEC_PAGE NTWK
5319
5320 END;
5321
5322 GLOBAL ROUTINE TST34: NOVALUE =
5323
5324 !++
5325 ! FUNCTIONAL DESCRIPTION:
5326 !
5327 ! TEST PAGE TABLE VALID, WRITABLE PINS
5328 ! FOR EACH SIDE OF THE RAM PAIRS (0,400)
5329 ! THIS ALSO CHECKS PAGE FAIL LOGIC (WRITABLE OFF, WRITE-TEST ON)
5330 !
5331 !--
5332
5333 BEGIN
5334
5335 MACRO
5336 PF_INFO_CAUSE = 0,0,36,0 %, ! CORRECT PAGE FAIL CAUSE
5337 PF_INFO_PTE = 1,0,36,0 %; ! PAGE TABLE ENTRY FOR TEST
5338
5339 LOCAL
5340 PTE,
5341 VMA,
5342 COR_PF_CAUSE,
5343 ACT_PF_CAUSE,
5344 OK;
5345
5346 OWN
5347 VMA_INFO: VECTOR[2] INITIAL
5348 (%O'000777', %O'400777'), ! LAST LOC FIRST PAGE EACH SIDE
5349 PF_INFO: BLOCKVECTOR[2,2] INITIAL
5350 (
5351 %O'12', %O'040000', ! INVALID, WRITABLE
5352 %O'10', %O'400000' ! VALID, UNWRITABLE
5353 );
5354
5355 LABEL
5356 LOOP1;
5357
5358 BIND
5359 TST_U_ADR = %O'460',
5360 TST_U = PLIT
5361 (
5362 %(0460)% U_J(0) V_DP_N(0777) U_B_T0 U_DEST_AD U, ! J, #<0:6> CHANGE
5363 %(0461)% U_J(462) V_DP_T0 U_MEM U_N(3010) U_SPEC_LDPAGE U,
5364 %(0462)% V_DP_N(0) U, ! #<0:17> CHANGES
5365 %(0463)% U_J(464) V_DP_T0 U_MEM U_N(32012) U,
5366 %(0464)% V_DP_0 U_MEM U_N(2) U
5367 ),
5368 TUA_VMA = TST_U_ADR + 0, ! WHERE TO DIDDLE VMA TO USE
5369 TUA_PAG = TST_U_ADR + 2, ! WHERE TO DIDDLE PAGE MAP
5370 TUA_TST = TST_U_ADR + 3; ! WHERE TO START TEST ITSELF
5371
5372 LOAD_TST_U;
5373 RPT_ERR_FLAG = 0;
5374 OK = 1;
5375
5376 INCR SUBTEST FROM 0 TO 1 DO ! INVALIDS THEN UNWRITABLES
5377 (
5378 SET_CRAM_ADR(TUA_VMA); ! FIX J FIELD FOR LOADING
5379 MOD_FLD(0,TUA_VMA+1); ! THE PAGE TABLE
5380 ERRINFO[2] = PTE = .PF_INFO[.SUBTEST,PF_INFO_PTE];
5381 ERRINFO[6] = COR_PF_CAUSE = .PF_INFO[.SUBTEST,PF_INFO_CAUSE];
5382 ERRINFO[7] = PF_NAME(.ERRINFO[6]);
5383
5384 INCR SIDE FROM 0 TO 1 DO ! SET UP BOTH SIDES (SWEEP?)
5385 (
5386 VMA = .VMA_INFO[.SIDE];
5387 SET_CRAM_ADR(TUA_PAG);
5388 MOD_FLD(3,.PTE<N_FLD3>); ! DIDDLE #<6:17>
5389 MOD_FLD(4,.PTE<N_FLD4>); ! DIDDLE #<0:5>; ZAP OTHER BITS
5390 SET_CRAM_ADR(TUA_VMA);
5391 MOD_FLD(4,.VMA<N_FLD4>); ! DIDDLE #<0:5>; ZAP OTHER BITS
5392 CP(4); ! STUFF THE ENTRY IN THE PAGE TABLE
5393 ! EXTRA CLOCK PULSE NEEDED
5394 );
5395
5396 SET_CRAM_ADR(TUA_VMA); ! FIX J FIELD FOR
5397 MOD_FLD(0,TUA_TST); ! THE TESTS
5398
5399 INCR SIDE FROM 0 TO 1 DO ! BOTH SIDES
5400 (
5401 ERRINFO[1] = VMA = .VMA_INFO[.SIDE];
5402 ERRINFO[3] = .VMA ^ (-9);
5403 SET_CRAM_ADR(TUA_VMA);
5404 MOD_FLD(4,.VMA<N_FLD4>); ! DIDDLE #<0:5>; ZAP OTHER BITS
5405 ERROR_LOOP(1)
5406 (
5407 PAGING_ON;
5408 SET_CRAM_ADR(TUA_VMA);
5409 IF STEP_U_NEXT(4) EQL O7777 ! EXTRA CLOCK PULSE?
5410 THEN
5411 (
5412 ERRINFO[4] = ACT_PF_CAUSE = PF_TRAP();
5413 ERRINFO[5] = PF_NAME(.ERRINFO[4]);
5414 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
5415 THEN
5416 (
5417 ERRCAS(1,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
5418 OK = 0;
5419 );
5420 )
5421 ELSE
5422 (
5423 ERRS(1,2,ERRINFO);
5424 OK = 0;
5425 );
5426 EXIT_LOOP(1,1);
5427 0
5428 );
5429 );
5430
5431 PAGING_OFF;
5432 );
5433
5434 IFN .OK THEN NOERR(1);
5435
5436 RPT_ERR_FLAG = 1;
5437
5438 !*MESSAGE 1
5439 !*STIMULUS:
5440 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
5441 !* WRITE/WRITE TEST TO VIRTUAL ADDR \O1 (CAUSING AN ERROR)
5442 !*RESPONSE:
5443 !* PAGE FAIL U-TRAP TO CRAM ADDR 7777
5444 !* CORRECT: PAGE FAIL CODE \O6 (\S7)
5445 !* ACTUAL: PAGE FAIL CODE \O4 (\S5)
5446
5447 !*MESSAGE 2
5448 !*STIMULUS:
5449 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
5450 !* WRITE/WRITE TEST TO VIRTUAL ADDR \O1 (CAUSING AN ERROR)
5451 !*RESPONSE:
5452 !* SHOULD GET PAGE FAIL U-TRAP TO CRAM ADDR 7777 (DIDN'T)
5453 !* CORRECT: PAGE FAIL CODE \O6 (\S7)
5454
5455 !]ERROR 1
5456 !]PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL NTWK
5457
5458 !]NO ERROR 1
5459 !]PT_VAL_WRT NTWK
5460
5461 END;
5462
5463 GLOBAL ROUTINE TST35: NOVALUE =
5464
5465 !++
5466 ! FUNCTIONAL DESCRIPTION:
5467 !
5468 ! TEST VMA USER, VMA PREV
5469 ! THIS LOADS LOTS OF U-CODE (SOMEDAY IT MAY DO MODIFY-FIELDS)
5470 !
5471 !--
5472
5473 BEGIN
5474
5475 MACRO
5476 INFO_COR_PREV = 0,0,36,0 %, ! CORRECT VMA PREVIOUS
5477 INFO_COR_USER = 1,0,36,0 %, ! CORRECT VMA USER
5478 INFO_EXECUTE = 2,0,36,0 %, ! CSL EXECUTE
5479 INFO_USER = 3,0,36,0 %, ! DPE USER
5480 INFO_PCU = 4,0,36,0 %, ! DPE PCU
5481 INFO_SPEC = 5,0,36,0 %, ! U-CODE SPEC FIELD
5482 INFO_N = 6,0,36,0 %; ! #
5483
5484 LOCAL
5485 CSL_EXECUTE,
5486 VMA,
5487 ACT_PREV,
5488 ACT_USER,
5489 COR_PREV,
5490 COR_USER,
5491 OK;
5492
5493 OWN
5494 INFO: BLOCKVECTOR[11,7] INITIAL
5495 (
5496 1, 1, 1, 0, 1, %O'00', %O'203110',
5497 1, 0, 1, 0, 0, %O'16', %O'203010',
5498 0, 0, 1, 0, 1, %O'00', %O'203010',
5499 0, 1, 1, 0, 0, %O'00', %O'603010',
5500 0, 0, 1, 0, 0, %O'00', %O'303010',
5501 0, 0, 1, 1, 0, %O'00', %O'203010',
5502 0, 1, 1, 1, 0, %O'00', %O'303010',
5503 0, 1, 0, 1, 0, %O'00', %O'003010',
5504 0, 0, 0, 0, 0, %O'00', %O'003010',
5505 0, 0, 1, 1, 0, %O'00', %O'003010',
5506 0, 0, 0, 1, 0, %O'00', %O'203010'
5507 );
5508
5509 LABEL
5510 LOOP1;
5511
5512 BIND
5513 TST_U_ADR = %O'470',
5514 TST_U = PLIT
5515 (
5516 %(0470)% V_D_N(400) V_DP_D U_SPEC_LDPXCT U, ! A PXCT BIT ON
5517 %(0471)% U_J(521) V_DP_0 U_SPEC_PXCT_OFF U, ! PXCT BITS OFF
5518 %(0472)% U_DBM_VMA U_DBUS_DBM V_DP_D U_DEST_Q_AD U, ! SAVE FLAGS
5519 %(0473)% U_J(474) V_D_N(004404) V_DP_D U_SPEC_FLAGS U,
5520 %(0474)% U_J(472) U_N(203110) U_MEM U,
5521 %(0475)% U_J(476) V_D_N(000004) V_DP_D U_SPEC_FLAGS U,
5522 %(0476)% U_J(472) U_N(203010) U_MEM U_SPEC_PREV U,
5523 %(0477)% U_J(500) V_D_N(004404) V_DP_D U_SPEC_FLAGS U,
5524 %(0500)% U_J(472) U_N(203010) U_MEM U,
5525 %(0501)% U_J(502) V_D_N(000004) V_DP_D U_SPEC_FLAGS U,
5526 %(0502)% U_J(472) U_N(603010) U_MEM U,
5527 %(0503)% U_J(504) V_D_N(000004) V_DP_D U_SPEC_FLAGS U,
5528 %(0504)% U_J(472) U_N(303010) U_MEM U,
5529 %(0505)% U_J(506) V_D_N(010004) V_DP_D U_SPEC_FLAGS U,
5530 %(0506)% U_J(472) U_N(203010) U_MEM U,
5531 %(0507)% U_J(510) V_D_N(010004) V_DP_D U_SPEC_FLAGS U,
5532 %(0510)% U_J(472) U_N(303010) U_MEM U,
5533 %(0511)% U_J(512) V_D_N(010004) V_DP_D U_SPEC_FLAGS U,
5534 %(0512)% U_J(472) U_N(003010) U_MEM U,
5535 %(0513)% U_J(514) V_D_N(000004) V_DP_D U_SPEC_FLAGS U,
5536 %(0514)% U_J(472) U_N(003010) U_MEM U,
5537 %(0515)% U_J(516) V_D_N(010004) V_DP_D U_SPEC_FLAGS U,
5538 %(0516)% U_J(472) U_N(003010) U_MEM U,
5539 %(0517)% U_J(520) V_D_N(010004) V_DP_D U_SPEC_FLAGS U,
5540 %(0520)% U_J(472) U_N(203010) U_MEM U,
5541 %(0521)% V_D_N(4) V_DP_D U_SPEC_FLAGS U
5542 ),
5543 TUA_INIT = TST_U_ADR + 0,
5544 TUA_FINI = TST_U_ADR + 1,
5545 TUA_BASE = TST_U_ADR + 3;
5546
5547 LOAD_TST_U;
5548 SET_CRAM_ADR(TUA_INIT);
5549 CP(2); ! EXTRA CLOCK PULSE NEEDED?
5550 OK = 1;
5551
5552 INCR SUBTEST FROM 0 TO 10 DO
5553 ERROR_LOOP(1)
5554 (
5555 ERRINFO[0] = CSL_EXECUTE = .INFO[.SUBTEST,INFO_EXECUTE];
5556 ERRINFO[1] = COR_PREV = .INFO[.SUBTEST,INFO_COR_PREV];
5557 ERRINFO[2] = COR_USER = .INFO[.SUBTEST,INFO_COR_USER];
5558 ERRINFO[5] = .INFO[.SUBTEST,INFO_USER];
5559 ERRINFO[6] = .INFO[.SUBTEST,INFO_PCU];
5560 ERRINFO[7] = .INFO[.SUBTEST,INFO_N];
5561 ERRINFO[8] = .INFO[.SUBTEST,INFO_SPEC];
5562 WRT212(.CSL_EXECUTE * 2);
5563 SET_CRAM_ADR(TUA_BASE + (.SUBTEST * 2));
5564 CP(3);
5565 VMA = SERIAL(10);
5566 ERRINFO[3] = ACT_PREV = .VMA<0,1>;
5567 ERRINFO[4] = ACT_USER = .VMA<9,1>;
5568 IF (.ACT_PREV NEQ .COR_PREV) OR (.ACT_USER NEQ .COR_USER)
5569 THEN
5570 (
5571 ERRS(1,1,ERRINFO);
5572 OK = 0;
5573 );
5574 MR(); ! DON'T GO AWAY IN USER MODE
5575 EXIT_LOOP(1,1);
5576 0
5577 );
5578
5579 IFN .OK THEN NOERR(1);
5580
5581 SET_CRAM_ADR(TUA_FINI); ! TURN PXCT & FLAGS BACK OFF
5582 CP(3); ! EXTRA CLOCK PULSE NEEDED?
5583 WRT212(0); ! TURN CSL EXECUTE BACK OFF
5584
5585 !*MESSAGE 1
5586 !*STIMULUS:
5587 !* CSL EXECUTE = \O0
5588 !* DPE USER = \O5, DPE PCU = \O6
5589 !* # = \O7, SPEC FIELD = \O8, LOAD VMA FLAGS
5590 !*RESPONSE:
5591 !* CORRECT: PREV = \O1, USER = \O2
5592 !* ACTUAL: PREV = \O3, USER = \O4
5593
5594 !]ERROR 1
5595 !]VMA_USER_PREV SPEC_PREV SPEC_PXCT MEM_EN N_ALL VMA_EN DBM_VMA_MEM DBM_SEL_VMA NTWK
5596
5597 !]NO ERROR 1
5598 !]VMA_USER_DP VMA_USER_N VMA_PREV_DP VMA_PREV_N SPEC_PXCT_OFF SPEC_PREV NTWK
5599
5600 END;
5601
5602 GLOBAL ROUTINE TST36: NOVALUE =
5603
5604 !++
5605 ! FUNCTIONAL DESCRIPTION:
5606 !
5607 ! TEST PAGE TABLE USER PINS & EXEC/USER MISMATCH PAGE FAIL
5608 ! FOR EACH SIDE OF THE RAM PAIRS (0,400)
5609 !
5610 !--
5611
5612 BEGIN
5613
5614 LOCAL
5615 VMA,
5616 COR_PF_CAUSE,
5617 ACT_PF_CAUSE,
5618 OK;
5619
5620 LABEL
5621 LOOP1;
5622
5623 BIND
5624 TST_U_ADR = %O'540',
5625 TST_U = PLIT
5626 (
5627 %(0540)% V_DP_N(000777) U_B_T0 U_DEST_AD U,
5628 %(0541)% V_DP_N(400777) U_B_T0 U_DEST_AD U,
5629 %(0542)% U_J(544) V_DP_T0 U_MEM U_N(203010) U_SPEC_LDPAGE U,
5630 %(0543)% U_J(544) V_DP_T0 U_MEM U_N(403010) U_SPEC_LDPAGE U,
5631 %(0544)% V_DP_N(400000) U,
5632 %(0545)% U_J(547) V_DP_T0 U_MEM U_N(232012) U,
5633 %(0546)% U_J(547) V_DP_T0 U_MEM U_N(432012) U,
5634 %(0547)% V_DP_0 U_MEM U_N(2) U
5635 ),
5636 TUA_LDVMA = TST_U_ADR + 0, ! LOAD VMA TO USE INTO T0
5637 TUA_LDPAG = TST_U_ADR + 2, ! LOAD PAGE TABLE ENTRY
5638 TUA_WRITE = TST_U_ADR + 5; ! WRITE, TO SEE HOW IT FAILS
5639
5640 LOAD_TST_U;
5641 OK = 1;
5642
5643 INCR SIDE FROM 0 TO 1 DO
5644 (
5645 ERRINFO[0] = VMA = (.SIDE ^ 17) OR %O'777';
5646 ERRINFO[1] = .VMA<9,9>;
5647 SET_CRAM_ADR(TUA_LDVMA + .SIDE);
5648 CP(2); ! EXTRA CLOCK PULSE NEEDED
5649 INCR PAGE_USER FROM 0 TO 1 DO
5650 (
5651 ERRINFO[2] = .PAGE_USER;
5652 SET_CRAM_ADR(TUA_LDPAG + .PAGE_USER);
5653 CP(3); ! EXTRA CLOCK PULSE NEEDED
5654 INCR WRITE_USER FROM 0 TO 1 DO
5655 (
5656 ERRINFO[3] = .WRITE_USER;
5657 ERRINFO[4] = COR_PF_CAUSE =
5658 (
5659 IF .PAGE_USER EQL .WRITE_USER
5660 THEN
5661 %O'10'
5662 ELSE
5663 %O'13'
5664 );
5665 ERRINFO[5] = PF_NAME(.COR_PF_CAUSE);
5666 ERROR_LOOP(1)
5667 (
5668 PAGING_ON;
5669 SET_CRAM_ADR(TUA_WRITE + .WRITE_USER);
5670 IF STEP_U_NEXT(3) EQL O7777 ! EXTRA CLOCK PULSE
5671 THEN
5672 (
5673 ERRINFO[6] = ACT_PF_CAUSE = PF_TRAP();
5674 ERRINFO[7] = PF_NAME(.ACT_PF_CAUSE);
5675 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
5676 THEN
5677 (
5678 ERRCAS(1,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
5679 OK = 0;
5680 );
5681 )
5682 ELSE
5683 (
5684 ERRS(1,2,ERRINFO);
5685 OK = 0;
5686 );
5687 PAGING_OFF;
5688 EXIT_LOOP(1,1);
5689 0
5690 );
5691 );
5692 );
5693 );
5694
5695 IFN .OK THEN NOERR(1);
5696
5697 !*MESSAGE 1
5698 !*STIMULUS:
5699 !* KS10: LOAD 400000 INTO PAGE TABLE LOC \O1, USER = \O2
5700 !* WRITE/WRITE TEST TO VIRTUAL ADDR \O0, USER = \O3
5701 !*RESPONSE:
5702 !* PAGE FAIL U-TRAP TO CRAM ADDR 7777
5703 !* CORRECT: PAGE FAIL CODE \O4 (\S5)
5704 !* ACTUAL: PAGE FAIL CODE \O6 (\S7)
5705
5706 !*MESSAGE 2
5707 !*STIMULUS:
5708 !* KS10: LOAD 400000 INTO PAGE TABLE LOC \O1, USER = \O2
5709 !* WRITE/WRITE TEST TO VIRTUAL ADDR \O0, USER = \O3
5710 !*RESPONSE:
5711 !* PAGE FAIL U-TRAP TO CRAM ADDR 7777 (DIDN'T)
5712 !* CORRECT: PAGE FAIL CODE \O4 (\S5)
5713
5714 !]ERROR 1
5715 !]PT_USR PT_IO PT_VAL_WRT PT_USR PT_MESS N_ALL PF_CODE NTWK
5716
5717 !]NO ERROR 1
5718 !]PT_USR NTWK
5719
5720 END;
5721
5722 GLOBAL ROUTINE TST37: NOVALUE =
5723
5724 !++
5725 ! FUNCTIONAL DESCRIPTION:
5726 !
5727 ! CHECK PAGE FAIL LOGIC (WRITABLE ON, WRITE-TEST OFF)
5728 !
5729 !--
5730
5731 BEGIN
5732
5733 LOCAL
5734 VMA,
5735 COR_PF_CAUSE,
5736 ACT_PF_CAUSE,
5737 CRAM_ADR,
5738 MEM_VAL;
5739
5740 LABEL
5741 LOOP1;
5742
5743 BIND
5744 TST_U_ADR = %O'550',
5745 TST_U = PLIT
5746 (
5747 %(0550)% U_J(551) V_DP_N(000777) U_B_T0 U_DEST_AD U,
5748 %(0551)% U_J(552) V_DP_T0 U_MEM U_N(203010) U_SPEC_LDPAGE U,
5749 %(0552)% V_DP_N(440000) U,
5750 %(0553)% U_J(554) V_DP_T0 U_MEM U_N(212012) U,
5751 %(0554)% V_DP_0 U_MEM U_N(2) U
5752 ),
5753 TUA_LDPAG = TST_U_ADR + 0, ! LOAD PAGE TABLE ENTRY
5754 TUA_WRITE = TST_U_ADR + 3; ! WRITE, TO SEE IF IT FAILS
5755
5756 LOAD_TST_U;
5757 ERRINFO[1] = COR_PF_CAUSE = %O'11'; ! 74148: EN = L --> Q1,Q2,Q4 = H
5758 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
5759 ERROR_LOOP(1)
5760 (
5761 DM(777,'-1'); ! SET LOCATION (%STRING HACK!)
5762 SET_CRAM_ADR(TUA_LDPAG); ! LOAD THE PAGE TABLE
5763 CP(4); ! EXTRA CLOCK PULSE
5764 PAGING_ON;
5765 SET_CRAM_ADR(TUA_WRITE); ! WRITE THE LOCATION (THE TEST)
5766 CRAM_ADR = STEP_U_NEXT(3); ! AND REMEMBER WHAT HAPPENED
5767 ERRINFO[0] = MEM_VAL = EM(777); ! SEE IF IT GOT WRITTEN
5768 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
5769 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
5770 IF .CRAM_ADR EQL O7777
5771 THEN
5772 ERRS(1,1,ERRINFO)
5773 ELSE
5774 IFN .MEM_VAL
5775 THEN
5776 ERRS(1,2,ERRINFO) ! DIDN'T WRITE
5777 ELSE
5778 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
5779 THEN
5780 ERRS(1,3,ERRINFO) ! WRONG DEFAULT PF CAUSE
5781 ELSE
5782 NOERR(1); ! SUCCESS
5783 PAGING_OFF;
5784 EXIT_LOOP(1,1);
5785 0
5786 );
5787
5788 !*MESSAGE 1
5789 !*STIMULUS:
5790 !* 8080: WRITE -1 TO MEM LOC 777
5791 !* KS10: LOAD 440000 INTO PAGE TABLE LOC 0
5792 !* WRITE 0 TO MEM LOC 777 WITH WRITE-TEST OFF
5793 !*RESPONSE:
5794 !* MEM LOC 777 SHOULD BE 0 (BUT IT IS \O0)
5795 !* SHOULD NOT GET PAGE FAIL TRAP (BUT IT DID)
5796 !* CORRECT: PAGE FAIL \O1 (\S2)
5797 !* ACTUAL: PAGE FAIL \O3 (\S4)
5798
5799 !*MESSAGE 2
5800 !*STIMULUS:
5801 !* 8080: WRITE -1 TO MEM LOC 777
5802 !* KS10: LOAD 440000 INTO PAGE TABLE LOC 0
5803 !* WRITE 0 TO MEM LOC 777 WITH WRITE-TEST OFF
5804 !*RESPONSE:
5805 !* MEM LOC 777 SHOULD BE 0 (BUT IT IS \O0)
5806 !* CORRECT: PAGE FAIL \O1 (\S2)
5807 !* ACTUAL: PAGE FAIL \O3 (\S4)
5808
5809 !*MESSAGE 3
5810 !*STIMULUS:
5811 !* 8080: WRITE -1 TO MEM LOC 777
5812 !* KS10: LOAD 440000 INTO PAGE TABLE LOC 0
5813 !* WRITE 0 TO MEM LOC 777 WITH WRITE-TEST OFF
5814 !*RESPONSE:
5815 !* MEM LOC 777 SHOULD BE 0 (IT IS)
5816 !* CORRECT: PAGE FAIL \O1 (\S2)
5817 !* ACTUAL: PAGE FAIL \O3 (\S4)
5818
5819 !]ERROR 1
5820 !]PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL NTWK
5821
5822 !]NO ERROR 1
5823 !]PF_WT NTWK
5824
5825 END;
5826
5827 GLOBAL ROUTINE TST38: NOVALUE =
5828
5829 !++
5830 ! FUNCTIONAL DESCRIPTION:
5831 !
5832 ! CHECK PAGE FAIL LOGIC (NXM ERROR)
5833 ! CAUSE AN NXM ERROR AND SEE IF WE GET THE
5834 ! PF TRAP AND CORRECT DISPATCH
5835 ! INSURE THAT THE ERROR PERSISTS WITHOUT SPEC/MEM CLR
5836 ! INSURE THAT THE ERROR IS CLEARED BY SPEC/MEM CLR
5837 !
5838 !--
5839
5840 BEGIN
5841
5842 LOCAL
5843 COR_PF_CAUSE,
5844 ACT_PF_CAUSE,
5845 CRAM_ADR,
5846 MEM_VAL,
5847 OK;
5848
5849 LABEL
5850 LOOP1;
5851
5852 BIND
5853 TST_U_ADR = %O'560',
5854 TST_U = PLIT
5855 (
5856 %(0560)% U_J(561) V_DP__1 U_MEM U_N(403010) U_SPEC_LDPAGE U,
5857 %(0561)% V_DP_N(443777) U,
5858 %(0562)% U_J(563) V_DP__1 U_MEM U_N(430012) U,
5859 %(0563)% V_DP_0 U_MEM U_N(2) U
5860 ),
5861 TUA_LDPAG = TST_U_ADR + 0, ! LOAD PAGE TABLE ENTRY
5862 TUA_WRITE = TST_U_ADR + 2; ! WRITE, TO SEE HOW IT FAILS
5863
5864 IF .MAX_MEM_ADR GTR %O'3777777' ! BE SURE WE HAVE AN NXM LOC
5865 THEN
5866 RETURN; ! NO, SO FORGET THIS TEST
5867 ! WITHOUT ANY ERROR ANALYSIS
5868 LOAD_TST_U;
5869 OK = 1;
5870 RPT_ERR_FLAG = 0;
5871
5872 SET_CRAM_ADR(TUA_LDPAG); ! LOAD THE PAGE TABLE
5873 CP(3); ! EXTRA CLOCK PULSE
5874 ERROR_LOOP(1)
5875 (
5876 PAGING_ON;
5877
5878 SET_CRAM_ADR(TUA_WRITE); ! DO THE TEST
5879 CRAM_ADR = STEP_U_NEXT(3); ! AND REMEMBER WHAT HAPPENED
5880 ERRINFO[1] = COR_PF_CAUSE = %O'05'; ! NXM "PAGE FAIL" DISPATCH
5881 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
5882 ERRINFO[3] = ACT_PF_CAUSE = PF_DISPATCH();
5883 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
5884 IF .CRAM_ADR NEQ O7777
5885 THEN
5886 ERRS(1,2,ERRINFO) ! NO "PAGE FAIL" TRAP HAPPENED
5887 ELSE
5888 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
5889 THEN
5890 (
5891 ! NOT NXM "PAGE FAIL" DISPATCH
5892 ERRCAS(1,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
5893 OK = 0;
5894 );
5895
5896 SET_CRAM_ADR(O7777); ! THIS U-CODE DOES NOTHING
5897 CP(3); ! LET CLOCKS GO A WHILE
5898 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
5899 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
5900 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
5901 THEN
5902 (
5903 ! NXM FLAG DIDN'T STAY SET
5904 ERRCAS(1,3,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
5905 OK = 0;
5906 );
5907
5908 ERRINFO[1] = COR_PF_CAUSE = %O'11'; ! NO PAGE FAIL
5909 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
5910 ERRINFO[3] = ACT_PF_CAUSE = PF_DISPATCH();
5911 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
5912 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
5913 THEN
5914 (
5915 ERRCAS(1,4,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
5916 ! DIDN'T CLEAR NXM FLAG
5917 OK = 0;
5918 );
5919
5920 SET_CRAM_ADR(TIU_ADR); ! MAKE IT GO AWAY
5921 CP(TIU_CNT);
5922 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
5923 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
5924 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
5925 THEN
5926 (
5927 ! NXM FLAG DIDN'T STAY CLEAR
5928 ERRCAS(1,5,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
5929 OK = 0;
5930 );
5931
5932 PAGING_OFF;
5933 EXIT_LOOP(1,1);
5934 0
5935 );
5936
5937 IFN .OK THEN NOERR(1);
5938
5939 RPT_ERR_FLAG = 1;
5940
5941 !*MESSAGE 1
5942 !*STIMULUS:
5943 !* KS10: LOAD 443777 INTO PAGE TABLE LOC 777
5944 !* WRITE 0 TO VIRTUAL MEM LOC 777777
5945 !*RESPONSE:
5946 !* SHOULD GET PAGE FAIL TRAP
5947 !* CORRECT: PAGE FAIL \O1 (\S2)
5948 !* ACTUAL: PAGE FAIL \O3 (\S4)
5949
5950 !*MESSAGE 2
5951 !*STIMULUS:
5952 !* KS10: LOAD 443777 INTO PAGE TABLE LOC 777
5953 !* WRITE 0 TO VIRTUAL MEM LOC 777777
5954 !*RESPONSE:
5955 !* SHOULD GET PAGE FAIL TRAP (DIDN'T)
5956 !* CORRECT: PAGE FAIL \O1 (\S2)
5957 !* ACTUAL: PAGE FAIL \O3 (\S4)
5958
5959 !*MESSAGE 3
5960 !*STIMULUS:
5961 !* KS10: CAUSE NXM ERROR, DO NOTHING, SEE IF IT STAYS
5962 !*RESPONSE:
5963 !* PAGE FAIL CONDITION SHOULD STAY (DIDN'T)
5964 !* CORRECT: PAGE FAIL \O1 (\S2)
5965 !* ACTUAL: PAGE FAIL \O3 (\S4)
5966
5967 !*MESSAGE 4
5968 !*STIMULUS:
5969 !* KS10: CAUSE NXM ERROR AND THEN DO SPEC/MEM CLR
5970 !*RESPONSE:
5971 !* SHOULD CLEAR PAGE FAIL TRAP CONDITION (DIDN'T)
5972 !* CORRECT: PAGE FAIL \O1 (\S2)
5973 !* ACTUAL: PAGE FAIL \O3 (\S4)
5974
5975 !*MESSAGE 5
5976 !*STIMULUS:
5977 !* KS10: CAUSE NXM ERROR, CLEAR IT (SPEC/MEM CLR),
5978 !* DO NOTHING, SEE IF IT STAYS AWAY
5979 !*RESPONSE:
5980 !* PAGE FAIL CONDITION SHOULD STAY AWAY (DIDN'T)
5981 !* CORRECT: PAGE FAIL \O1 (\S2)
5982 !* ACTUAL: PAGE FAIL \O3 (\S4)
5983
5984 !]ERROR 1
5985 !]PT_VAL_WRT PT_IO PF_NXM SPEC_MEMCLR_NXM PF_CODE PT_USR PT_MESS N_ALL NTWK
5986
5987 !]NO ERROR 1
5988 !]PF_NXM SPEC_MEMCLR_NXM NTWK
5989
5990 END;
5991
5992 GLOBAL ROUTINE TST39: NOVALUE =
5993
5994 !++
5995 ! FUNCTIONAL DESCRIPTION:
5996 !
5997 ! CHECK PAGE FAIL LOGIC (BAD DATA ERROR)
5998 ! CAUSE A BAD DATA ERROR AND SEE IF WE GET THE
5999 ! PF TRAP AND CORRECT DISPATCH
6000 ! INSURE THAT THE ERROR PERSISTS WITHOUT SPEC/MEM CLR
6001 ! INSURE THAT THE ERROR IS CLEARED BY SPEC/MEM CLR
6002 !
6003 !--
6004
6005 BEGIN
6006
6007 LOCAL
6008 COR_PF_CAUSE,
6009 ACT_PF_CAUSE,
6010 CRAM_ADR,
6011 OK;
6012
6013 LABEL
6014 LOOP1;
6015
6016 BIND
6017 TST_U_ADR = %O'570',
6018 TST_U = PLIT
6019 (
6020 %(0570)% U_J(571) V_DP_N(777) U_B_T0 U_DEST_AD U,
6021 %(0571)% U_J(572) V_DP_T0 U_MEM U_N(403010) U_SPEC_LDPAGE U,
6022 %(0572)% V_DP_N(460000) U,
6023 %(0573)% U_J(574) V_DP_T0 U_MEM U_N(442012) U,
6024 %(0574)% V_DP_0 U_MEM U_N(2) U
6025 ),
6026 TUA_LDPAG = TST_U_ADR + 0, ! LOAD PAGE TABLE ENTRY
6027 TUA_READ = TST_U_ADR + 3; ! READ, TO SEE HOW IT FAILS
6028
6029 LOAD_TST_U;
6030 OK = 1;
6031 RPT_ERR_FLAG = 0;
6032
6033 SET_CRAM_ADR(TUA_LDPAG); ! LOAD THE PAGE TABLE
6034 CP(4); ! EXTRA CLOCK PULSE
6035 ERROR_LOOP(1)
6036 (
6037 DI(100000,176); ! SET MMC ECC FORCE BITS --
6038 ! EVEN NUMBER OF BITS ON GETS AN
6039 ! UNCORRECTABLE DOUBLE-BIT ERROR
6040 DM(777,0); ! MAKE ECC BAD AT A LOCATION
6041 PAGING_ON;
6042
6043 SET_CRAM_ADR(TUA_READ); ! DO THE TEST
6044 CRAM_ADR = STEP_U_NEXT(3); ! AND REMEMBER WHAT HAPPENED
6045 ERRINFO[1] = COR_PF_CAUSE = %O'03'; ! BAD DATA "PAGE FAIL" DISPATCH
6046 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
6047 ERRINFO[3] = ACT_PF_CAUSE = PF_DISPATCH();
6048 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6049 IF .CRAM_ADR NEQ O7777
6050 THEN
6051 (
6052 ERRS(1,2,ERRINFO); ! NO "PAGE FAIL" TRAP HAPPENED
6053 OK = 0;
6054 )
6055 ELSE
6056 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6057 THEN
6058 (
6059 ! NOT BAD DATA "PAGE FAIL" DISPATCH
6060 ERRCAS(1,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6061 OK = 0;
6062 );
6063
6064 SET_CRAM_ADR(O7777); ! THIS U-CODE DOES NOTHING
6065 CP(3); ! BUT LET THE CLOCKS GO A WHILE
6066 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
6067 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6068 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6069 THEN
6070 (
6071 ! BAD DATA FLAG DIDN'T STAY SET
6072 ERRCAS(1,3,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6073 OK = 0;
6074 );
6075
6076 ERRINFO[1] = COR_PF_CAUSE = %O'11'; ! NO PAGE FAIL
6077 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
6078 ERRINFO[3] = ACT_PF_CAUSE = PF_DISPATCH();
6079 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6080 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6081 THEN
6082 (
6083 ! DIDN'T CLEAR BAD DATA FLAG
6084 ERRCAS(1,4,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6085 OK = 0;
6086 );
6087
6088 SET_CRAM_ADR(TIU_ADR); ! MAKE IT GO AWAY
6089 CP(TIU_CNT);
6090 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
6091 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6092 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6093 THEN
6094 (
6095 ! BAD DATA FLAG DIDN'T STAY CLEAR
6096 ERRCAS(1,5,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6097 OK = 0;
6098 );
6099
6100 PAGING_OFF;
6101 EXIT_LOOP(1,1);
6102 0
6103 );
6104
6105 IFN .OK THEN NOERR(1);
6106
6107 DM(777,0); ! MAKE ECC GOOD AGAIN
6108 RPT_ERR_FLAG = 1;
6109
6110 !*MESSAGE 1
6111 !*STIMULUS:
6112 !* 8080: DEPOSIT 176 TO I/O REGISTER 100000
6113 !* (SETTING EVEN NUMBER OF MMC ECC FORCE BITS)
6114 !* DEPOSIT 0 TO PHYSICAL MEM LOC 777 (WITH WRONG ECC)
6115 !* KS10: LOAD 460000 INTO PAGE TABLE LOC 0
6116 !* READ VIRTUAL MEM LOC 777 (CAUSING DOUBLE-BIT ERROR)
6117 !*RESPONSE:
6118 !* SHOULD GET PAGE FAIL TRAP
6119 !* CORRECT: PAGE FAIL \O1 (\S2)
6120 !* ACTUAL: PAGE FAIL \O3 (\S4)
6121
6122 !*MESSAGE 2
6123 !*STIMULUS:
6124 !* 8080: DEPOSIT 176 TO I/O REGISTER 100000
6125 !* (SETTING EVEN NUMBER OF MMC ECC FORCE BITS)
6126 !* DEPOSIT 0 TO PHYSICAL MEM LOC 777 (WITH WRONG ECC)
6127 !* KS10: LOAD 460000 INTO PAGE TABLE LOC 0
6128 !* READ VIRTUAL MEM LOC 777 (CAUSING DOUBLE-BIT ERROR)
6129 !*RESPONSE:
6130 !* SHOULD GET PAGE FAIL TRAP (DIDN'T)
6131 !* CORRECT: PAGE FAIL \O1 (\S2)
6132 !* ACTUAL: PAGE FAIL \O3 (\S4)
6133
6134 !*MESSAGE 3
6135 !*STIMULUS:
6136 !* KS10: CAUSE BAD DATA ERROR, DO NOTHING, SEE IF IT STAYS
6137 !*RESPONSE:
6138 !* PAGE FAIL CONDITION SHOULD STAY (DIDN'T)
6139 !* CORRECT: PAGE FAIL \O1 (\S2)
6140 !* ACTUAL: PAGE FAIL \O3 (\S4)
6141
6142 !*MESSAGE 4
6143 !*STIMULUS:
6144 !* KS10: CAUSE BAD DATA ERROR AND THEN DO SPEC/MEM CLR
6145 !*RESPONSE:
6146 !* SHOULD CLEAR PAGE FAIL TRAP CONDITION (DIDN'T)
6147 !* CORRECT: PAGE FAIL \O1 (\S2)
6148 !* ACTUAL: PAGE FAIL \O3 (\S4)
6149
6150 !*MESSAGE 5
6151 !*STIMULUS:
6152 !* KS10: CAUSE BAD DATA ERROR, CLEAR IT (SPEC/MEM CLR),
6153 !* DO NOTHING, SEE IF IT STAYS AWAY
6154 !*RESPONSE:
6155 !* PAGE FAIL CONDITION SHOULD STAY AWAY (DIDN'T)
6156 !* CORRECT: PAGE FAIL \O1 (\S2)
6157 !* ACTUAL: PAGE FAIL \O3 (\S4)
6158
6159 !]ERROR 1
6160 !]PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL PF_BAD SPEC_MEMCLR_BAD NTWK
6161
6162 !]NO ERROR 1
6163 !]PF_BAD SPEC_MEMCLR_BAD NTWK
6164
6165 END;
6166
6167 GLOBAL ROUTINE TST40: NOVALUE =
6168
6169 !++
6170 ! FUNCTIONAL DESCRIPTION:
6171 !
6172 ! CHECK DPM PAGING OK ENABLING CONDITIONS GATE
6173 !
6174 !--
6175
6176 BEGIN
6177
6178 LOCAL
6179 COR_PF_CAUSE,
6180 ACT_PF_CAUSE,
6181 CRAM_ADR,
6182 OK;
6183
6184 LABEL
6185 LOOP1,
6186 LOOP2,
6187 LOOP3,
6188 LOOP4;
6189
6190 BIND
6191 TST_U_ADR = %O'600',
6192 TST_U = PLIT
6193 (
6194 %(0600)% U_J(601) V_DP_0 U_MEM U_N(403010) U_SPEC_LDPAGE U,
6195 %(0601)% U_J(602) V_DP_0 U,
6196 %(0602)% U_J(604) V_DP_N(777) U_B_T0 U_DEST_AD U,
6197 %(0603)% U_J(604) V_DP_0 U_B_T0 U_DEST_AD U,
6198 %(0604)% U_J(607) V_DP_T0 U_MEM U_N(430012) U,
6199 %(0605)% U_J(606) V_DP_0 U_B_T0 U_DEST_AD U,
6200 %(0606)% U_J(607) V_DP_T0 U_MEM U_N(431012) U,
6201 %(0607)% V_DP_0 U_MEM U_N(2) U
6202 ),
6203 TUA_LDPAG = TST_U_ADR + 0, ! LOAD PAGE TABLE ENTRY
6204 TUA_ACVMA = TST_U_ADR + 3, ! LOAD VMA WITH 0 (AN AC)
6205 TUA_PHYSVMA = TST_U_ADR + 5; ! DO PHYSICAL WRITE TO 0
6206
6207 LOAD_TST_U;
6208 OK = 1;
6209 PAGING_ON;
6210 ERROR_LOOP(1)
6211 (
6212 SET_CRAM_ADR(TUA_LDPAG); ! LOAD PAGE TABLE, DO TEST
6213 CP(6);
6214 ERRINFO[0] = %O'777';
6215 ERRINFO[1] = COR_PF_CAUSE = %O'12';
6216 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
6217 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
6218 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6219 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6220 THEN
6221 (
6222 ERRCAS(1,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6223 OK = 0;
6224 );
6225 EXIT_LOOP(1,1);
6226 0
6227 );
6228
6229 PAGING_ON;
6230 ERROR_LOOP(2)
6231 (
6232 SET_CRAM_ADR(TUA_ACVMA); ! JUST DO TEST
6233 CP(4);
6234 ERRINFO[0] = 0;
6235 ERRINFO[1] = COR_PF_CAUSE = %O'11';
6236 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
6237 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
6238 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6239 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6240 THEN
6241 (
6242 ERRCAS(1,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6243 OK = 0;
6244 );
6245 EXIT_LOOP(2,1);
6246 0
6247 );
6248
6249 PAGING_ON;
6250 ERROR_LOOP(3)
6251 (
6252 SET_CRAM_ADR(TUA_PHYSVMA); ! JUST DO TEST
6253 CP(4);
6254 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
6255 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6256 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6257 THEN
6258 (
6259 ERRCAS(2,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6260 OK = 0;
6261 );
6262 EXIT_LOOP(3,1);
6263 0
6264 );
6265 PAGING_OFF; ! ALL ELSE IS SAME AS BEFORE
6266
6267 ERROR_LOOP(4)
6268 (
6269 SET_CRAM_ADR(TUA_ACVMA); ! JUST DO TEST
6270 CP(4);
6271 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
6272 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6273 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6274 THEN
6275 (
6276 ERRCAS(3,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO);
6277 OK = 0;
6278 );
6279 EXIT_LOOP(4,1);
6280 0
6281 );
6282
6283 IFN .OK THEN NOERR(1);
6284
6285 !*MESSAGE 1
6286 !*STIMULUS:
6287 !* KS10: TURN PAGING ON AND LOAD 0 INTO PAGE TABLE LOC 0
6288 !* WRITE TO MEM LOC \O0 AND CHECK PAGE FAIL CODE
6289 !*RESPONSE:
6290 !* CORRECT: PAGE FAIL \O1 (\S2)
6291 !* ACTUAL: PAGE FAIL \O3 (\S4)
6292
6293 !*MESSAGE 2
6294 !*STIMULUS:
6295 !* KS10: TURN PAGING ON AND LOAD 0 INTO PAGE TABLE LOC 0
6296 !* PHYSICAL WRITE TO MEM LOC \O0 AND CHECK PAGE FAIL CODE
6297 !*RESPONSE:
6298 !* CORRECT: PAGE FAIL \O1 (\S2)
6299 !* ACTUAL: PAGE FAIL \O3 (\S4)
6300
6301 !*MESSAGE 3
6302 !*STIMULUS:
6303 !* KS10: LOAD 0 INTO PAGE TABLE LOC 0 AND TURN PAGING OFF
6304 !* WRITE TO MEM LOC \O0 AND CHECK PAGE FAIL CODE
6305 !*RESPONSE:
6306 !* CORRECT: PAGE FAIL \O1 (\S2)
6307 !* ACTUAL: PAGE FAIL \O3 (\S4)
6308
6309 !]ERROR 1
6310 !]PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL PF_OK NTWK
6311
6312 !]NO ERROR 1
6313 !]PF_OK NTWK
6314
6315 END;
6316
6317 GLOBAL ROUTINE TST41: NOVALUE =
6318
6319 !++
6320 ! FUNCTIONAL DESCRIPTION:
6321 !
6322 ! CHECK SWEEP WHEN WRITING TO PAGE TABLE
6323 !
6324 !--
6325
6326 BEGIN
6327
6328 LOCAL
6329 COR_PF_CAUSE,
6330 ACT_PF_CAUSE,
6331 CRAM_ADR;
6332
6333 LABEL
6334 LOOP1;
6335
6336 BIND
6337 TST_U_ADR = %O'610',
6338 TST_U = PLIT
6339 (
6340 %(0610)% U_J(611) V_DP_N(400000) U_B_T0 U_DEST_AD U,
6341 %(0611)% U_J(612) V_DP_T0 U_MEM U_N(403010) U_SPEC_LDPAGE U,
6342 %(0612)% U_J(613) V_DP_N(400000) U, ! VALID, UNWRITABLE
6343 %(0613)% U_J(614) V_DP_0 U_MEM U_N(403010) U_SPEC_SWEEP U,
6344 %(0614)% U_J(615) V_DP_0 U_SPEC_LDPAGE U,
6345 %(0615)% U_J(616) V_DP_N(040000) U, ! INVALID, WRITABLE
6346 %(0616)% U_J(617) V_DP_T0 U_MEM U_N(430012) U,
6347 %(0617)% V_DP_0 U_MEM U_N(2) U
6348 );
6349
6350 LOAD_TST_U;
6351
6352 PAGING_ON;
6353 ERROR_LOOP(1)
6354 (
6355 SET_CRAM_ADR(TST_U_ADR);
6356 CRAM_ADR = STEP_U_NEXT(9);
6357 ERRINFO[1] = COR_PF_CAUSE = %O'12';
6358 ERRINFO[2] = PF_NAME(.COR_PF_CAUSE);
6359 ERRINFO[3] = ACT_PF_CAUSE = PF_TRAP();
6360 ERRINFO[4] = PF_NAME(.ACT_PF_CAUSE);
6361 IF .CRAM_ADR NEQ O7777 THEN
6362 ERRCAS(1,2,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO)
6363 ELSE
6364 IF .ACT_PF_CAUSE NEQ .COR_PF_CAUSE
6365 THEN
6366 ERRCAS(1,1,.COR_PF_CAUSE,.ACT_PF_CAUSE,2,ERRINFO)
6367 ELSE
6368 NOERR(1);
6369 EXIT_LOOP(1,1);
6370 0
6371 );
6372 PAGING_OFF;
6373
6374 !*MESSAGE 1
6375 !*STIMULUS:
6376 !* MAKE PAGE 400 VALID & UNWRITABLE WITH MEM & #
6377 !* MAKE PAGE 0 INVALID & WRITABLE WITH SWEEP
6378 !* WRITE TO MEM LOC 400000
6379 !*RESPONSE:
6380 !* SHOULD GET PAGE FAIL TRAP (DID)
6381 !* CORRECT: PAGE FAIL \O1 (\S2)
6382 !* ACTUAL: PAGE FAIL \O3 (\S4)
6383
6384 !*MESSAGE 2
6385 !*STIMULUS:
6386 !* MAKE PAGE 400 VALID & UNWRITABLE WITH MEM & #
6387 !* MAKE PAGE 0 INVALID & WRITABLE WITH SWEEP
6388 !* WRITE TO MEM LOC 400000
6389 !*RESPONSE:
6390 !* SHOULD GET PAGE FAIL TRAP (DIDN'T)
6391 !* CORRECT: PAGE FAIL \O1 (\S2)
6392 !* ACTUAL: PAGE FAIL \O3 (\S4)
6393
6394 !]ERROR 1
6395 !]VMA_SWEEP_PT VMA_SWEEP SPEC_SWEEP PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL NTWK
6396
6397 !]NO ERROR 1
6398 !]VMA_SWEEP_PT NTWK
6399
6400 END;
6401
6402 GLOBAL ROUTINE TST42: NOVALUE =
6403
6404 !++
6405 ! FUNCTIONAL DESCRIPTION:
6406 !
6407 ! CHECK BASIC CACHE OPERATION, ENABLES
6408 ! FINAL CRAM ADR = 0: ALU NOT = 0: HIT
6409 ! FINAL CRAM ADR = 1: ALU = 0: MISS
6410 ! ALSO DOES PAGE TABLE RAM CACHABLE PINS
6411 !
6412 !--
6413
6414 BEGIN
6415
6416 MACRO
6417 INFO_COR_ADR = 0,0,36,0 %, ! FINAL CRAM ADR
6418 INFO_CE = 1,0,36,0 %, ! CSL CACHE ENABLE
6419 INFO_PAGING = 2,0,36,0 %, ! PAGING ON
6420 INFO_N_VMA = 3,0,18,0 %, ! VMA IN TOTO
6421 INFO_N_PMA = 3,0,9,0 %, ! PMA (VMA MAPPED TO PAGE 0)
6422 INFO_N_VMA_FLD3 = 3,0,12,0 %, ! #<6:17> FOR VMA
6423 INFO_N_VMA_FLD4 = 3,12,6,0 %, ! #<0:5> FOR VMA
6424 INFO_N_PAG_FLD3 = 4,0,12,0 %, ! #<6:17> FOR PAGE TABLE
6425 INFO_N_PAG_FLD4 = 4,12,6,0 %, ! #<0:5> FOR PAGE TABLE
6426 INFO_N_REF_FLD3 = 5,0,12,0 %, ! #<6:17> FOR MEMORY REFERENCE
6427 INFO_N_REF_FLD4 = 5,12,6,0 %, ! #<0:5> FOR MEMORY REFERENCE
6428 INFO_DESCR = 6,0,36,0 %; ! DESCRIPTION
6429
6430 LOCAL
6431 VMA,
6432 PMA,
6433 ACT_PF_CAUSE,
6434 CRAM_ADR,
6435 COR_CRAM_ADR,
6436 OK;
6437
6438 OWN
6439 HIT_MSG: VECTOR[2] INITIAL
6440 (
6441 UPLIT(%ASCIZ '-1 (CACHE HIT)'),
6442 UPLIT(%ASCIZ '0 (CACHE MISS)')
6443 ),
6444 INFO: BLOCKVECTOR[11,7] INITIAL
6445 (
6446 0, 1, 1, %O'000777', %O'460000', %O'440012', UPLIT(%ASCIZ 'CACHE ENABLED, USER'),
6447 0, 1, 1, %O'400777', %O'460000', %O'440012', UPLIT(%ASCIZ 'CACHE ENABLED, USER'),
6448 0, 1, 1, %O'000377', %O'460000', %O'440012', UPLIT(%ASCIZ 'CACHE ENABLED, USER'),
6449 0, 1, 1, %O'000777', %O'460000', %O'240012', UPLIT(%ASCIZ 'CACHE ENABLED, EXEC'),
6450 0, 1, 1, %O'000377', %O'460000', %O'240012', UPLIT(%ASCIZ 'CACHE ENABLED, EXEC'),
6451 1, 0, 1, %O'000777', %O'460000', %O'440012', UPLIT(%ASCIZ 'CACHE DISABLED'),
6452 1, 1, 0, %O'000777', %O'460000', %O'440012', UPLIT(%ASCIZ 'PAGING DISABLED'),
6453 1, 1, 1, %O'000777', %O'460000', %O'442012', UPLIT(%ASCIZ 'MEM CACHE INHIBIT'),
6454 1, 1, 1, %O'000777', %O'460000', %O'441012', UPLIT(%ASCIZ 'MEM PHYSICAL'),
6455 1, 1, 1, %O'000777', %O'440000', %O'440012', UPLIT(%ASCIZ 'PAGE UNCACHABLE'),
6456 1, 1, 1, %O'400777', %O'440000', %O'440012', UPLIT(%ASCIZ 'PAGE UNCACHABLE')
6457 );
6458
6459 LABEL
6460 LOOP1;
6461
6462 BIND
6463 TST_U_ADR = %O'630',
6464 TST_U = PLIT
6465 (
6466 %(0630)% U_J(631) V_DP_N(000777) U_B_T0 U_DEST_AD U, ! #
6467 %(0631)% U_J(632) V_DP_T0 U_MEM U_N(001010) U_SPEC_LDPAGE U, ! #
6468 %(0632)% U_J(633) V_DP_N(460000) U, ! #
6469 %(0633)% U_J(634) V_DP_T0 U_MEM U_N(030012) U, ! #
6470 %(0634)% V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
6471 %(0635)% U_J(636) V_DP_T0 U_MEM U_N(040012) U, ! #
6472 %(0636)% V_DP_D U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
6473 ),
6474 TUA_PAGVMA = TST_U_ADR + 1,
6475 TUA_PAG = TST_U_ADR + 2,
6476 TUA_WRITE = TST_U_ADR + 3,
6477 TUA_READ = TST_U_ADR + 5;
6478
6479 LOAD_TST_U;
6480 OK = 1;
6481
6482 INCR ERRN FROM 0 TO 10 DO
6483 ERROR_LOOP(1)
6484 (
6485 ERRINFO[2] = .INFO[.ERRN,INFO_DESCR];
6486 ERRINFO[0] = PMA = .INFO[.ERRN,INFO_N_PMA];
6487 ERRINFO[3] = VMA = .INFO[.ERRN,INFO_N_VMA];
6488 ERRINFO[4] = .VMA<9,9>; ! PAGE
6489 COR_CRAM_ADR = .INFO[.ERRN,INFO_COR_ADR];
6490 ERRINFO[5] = .HIT_MSG[.COR_CRAM_ADR];
6491
6492 CE(.INFO[.ERRN,INFO_CE]); ! ENABLE/DISABLE CACHE
6493
6494 IFN .INFO[.ERRN,INFO_PAGING]
6495 THEN
6496 PAGING_ON
6497 ELSE
6498 PAGING_OFF;
6499
6500 SET_CRAM_ADR(TUA_PAG);
6501 MOD_FLD(3,.INFO[.ERRN,INFO_N_PAG_FLD3]);
6502 MOD_FLD(4,.INFO[.ERRN,INFO_N_PAG_FLD4]);
6503
6504 ! USER/EXEC HACKS
6505 SET_CRAM_ADR(TUA_PAGVMA);
6506 MOD_FLD(4,.INFO[.ERRN,INFO_N_REF_FLD4] AND %O'70');
6507 SET_CRAM_ADR(TUA_WRITE);
6508 MOD_FLD(4,(.INFO[.ERRN,INFO_N_REF_FLD4] AND %O'70') OR 3);
6509
6510 SET_CRAM_ADR(TST_U_ADR);
6511 MOD_FLD(3,.INFO[.ERRN,INFO_N_VMA_FLD3]);
6512 MOD_FLD(4,.INFO[.ERRN,INFO_N_VMA_FLD4]);
6513 CP(5);
6514 MEM_DEPOSIT(.PMA,0);
6515
6516 SET_CRAM_ADR(TUA_READ);
6517 MOD_FLD(3,.INFO[.ERRN,INFO_N_REF_FLD3]);
6518 MOD_FLD(4,.INFO[.ERRN,INFO_N_REF_FLD4]);
6519 CRAM_ADR = STEP_U_NEXT(2);
6520 IF .CRAM_ADR NEQ .COR_CRAM_ADR
6521 THEN
6522 (
6523 ERRS(1,1,ERRINFO);
6524 OK = 0;
6525 );
6526 EXIT_LOOP(1,1);
6527 0
6528 );
6529
6530 IFN .OK THEN NOERR(1);
6531
6532 CE(0); ! PUT IT BACK
6533 PAGING_OFF;
6534
6535 !*MESSAGE 1
6536 !*STIMULUS:
6537 !* KS10: TEST CACHE ENABLE CONDITION: \S2
6538 !* MAP PAGE \O4 TO PAGE 0
6539 !* WRITE -1 TO VIRTUAL MEM LOC \O3
6540 !* 8080: WRITE 0 TO PHYSICAL MEM LOC \O0
6541 !* KS10: READ VIRTUAL MEM LOC \O3
6542 !*RESPONSE:
6543 !* SHOULD GET \S5; DIDN'T
6544
6545 !]ERROR 1
6546 !]CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK
6547
6548 !]NO ERROR 1
6549 !]CD_HIT PT_CAC NTWK
6550
6551 END;
6552
6553 GLOBAL ROUTINE TST43: NOVALUE =
6554
6555 !++
6556 ! FUNCTIONAL DESCRIPTION:
6557 !
6558 ! CHECK CACHE DIR RAM DATA I/O PINS
6559 ! FINAL CRAM ADR = 0: ALU NOT = 0: HIT
6560 ! FINAL CRAM ADR = 1: ALU = 0: MISS
6561 !
6562 !--
6563
6564 BEGIN
6565
6566 LOCAL
6567 VMA,
6568 CRAM_ADR;
6569
6570 OWN
6571 PMA: VECTOR[2] INITIAL(%O'377', %O'777'),
6572 ALL_PAGE_BITS: VECTOR[2] INITIAL(%O'777000', 0),
6573 PAGE_BIT: VECTOR[9] INITIAL(1^9,1^10,1^11,1^12,1^13,1^14,1^15,1^16,1^17);
6574
6575 LABEL
6576 LOOP1;
6577
6578 BIND
6579 TST_U_ADR = %O'640',
6580 TST_U = PLIT
6581 (
6582 %(0640)% U_J(641) V_DP_N(000777) U_B_T0 U_DEST_AD U, ! #<6:17> CHANGES
6583 %(0641)% U_J(642) V_DP_T0 U_MEM U_N(401010) U_SPEC_LDPAGE U,
6584 %(0642)% U_J(643) V_DP_N(460000) U,
6585 %(0643)% U_J(644) V_DP_T0 U_MEM U_N(430012) U,
6586 %(0644)% V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
6587 %(0645)% U_J(646) V_DP_T0 U_MEM U_N(440012) U,
6588 %(0646)% V_DP_D U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
6589 ),
6590 TUA_REF = TST_U_ADR + 5;
6591
6592 LOAD_TST_U;
6593 PAGING_ON;
6594 CE(1);
6595 INCR SIDE FROM 0 TO 1 DO
6596 INCR BITNO FROM 0 TO 8 DO
6597 INCR BITVAL FROM 0 TO 1 DO
6598 ERROR_LOOP(1)
6599 (
6600 ERRINFO[0] = .PMA[.SIDE];
6601
6602 VMA = (.PAGE_BIT[.BITNO] XOR .ALL_PAGE_BITS[.BITVAL]) OR .PMA[.SIDE];
6603 ERRINFO[3] = .VMA;
6604 ERRINFO[1] = .VMA<9,9>;
6605
6606 SET_CRAM_ADR(TST_U_ADR);
6607 MOD_FLD(3,.VMA<N_FLD3>);
6608 MOD_FLD(4,.VMA<N_FLD4>);
6609 CP(5);
6610 MEM_DEPOSIT(.PMA,0);
6611
6612 SET_CRAM_ADR(TUA_REF);
6613 CRAM_ADR = STEP_U_NEXT(2);
6614 IFN .CRAM_ADR ! HIT: 0; MISS: 1
6615 THEN
6616 ERRS(1,1,ERRINFO)
6617 ELSE
6618 NOERR(1);
6619 EXIT_LOOP(1,1);
6620 0
6621 );
6622 CE(0); ! PUT IT BACK
6623 PAGING_OFF;
6624
6625 !*MESSAGE 1
6626 !*STIMULUS:
6627 !* KS10: TEST CACHE DIRECTORY RAM DATA I/O PINS
6628 !* MAP PAGE \O1 TO PAGE 0
6629 !* WRITE -1 TO VIRTUAL MEM LOC \O3
6630 !* 8080: WRITE 0 TO PHYSICAL MEM LOC \O0
6631 !* KS10: READ VIRTUAL MEM LOC \O3
6632 !*RESPONSE:
6633 !* SHOULD GET -1 (CACHE HIT); DIDN'T
6634
6635 !]ERROR 1
6636 !]CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK
6637
6638 !]NO ERROR 1
6639 !]CD_IO NTWK
6640
6641 END;
6642
6643 GLOBAL ROUTINE TST44: NOVALUE =
6644
6645 !++
6646 ! FUNCTIONAL DESCRIPTION:
6647 !
6648 ! TEST CACHE DIRECTORY RAM ADDRESS LINES
6649 ! FOR LOCATIONS (0,1,2,4,10,...,200) + (1000,1400):
6650 ! MAP TO PAGE 1, WRITE VMA TO M[VMA], ZERO M (8080), READ M[VMA]
6651 ! IF A PIN IS STUCK, M[0] = M[2**N] (WHICH IS WHICH: HIGH OR LOW)
6652 !
6653 !--
6654
6655 BEGIN
6656
6657 LOCAL
6658 VMA;
6659
6660 OWN
6661 INFO: VECTOR[18] INITIAL
6662 (
6663 %O'1000', %O'1400',
6664 %O'1001', %O'1401',
6665 %O'1002', %O'1402',
6666 %O'1004', %O'1404',
6667 %O'1010', %O'1410',
6668 %O'1020', %O'1420',
6669 %O'1040', %O'1440',
6670 %O'1100', %O'1500',
6671 %O'1200', %O'1600'
6672 );
6673
6674 LABEL
6675 LOOP1;
6676
6677 BIND
6678 TST_U_ADR = %O'650',
6679 TST_U = PLIT
6680 (
6681 %(0650)% U_J(651) V_DP_N(1000) U_B_T0 U_DEST_AD U, ! J,# CHANGE
6682 %(0651)% U_J(652) V_DP_T0 U_MEM U_N(1010) U_SPEC_LDPAGE U,
6683 %(0652)% U_J(653) V_DP_N(460001) U,
6684 %(0653)% U_J(654) V_DP_T0 U_MEM U_N(30012) U,
6685 %(0654)% V_DP_T0 U_DBUS_DP U_MEM U_N(2) U,
6686 %(0655)% U_J(656) V_DP_T0 U_MEM U_N(40012) U,
6687 %(0656)% U_J(657) V_DP_D U_DBM_MEM U_DBUS_DBM U_DEST_Q_AD U_MEM U_N(2) U,
6688 %(0657)% U_A_T0 U_LSRC_AQ U_ALU_XOR U_SKIP_ADEQ0 U
6689 );
6690
6691 LOAD_TST_U;
6692 RPT_ERR_FLAG = 0;
6693 PAGING_ON;
6694 CE(1);
6695 SET_CRAM_ADR(TST_U_ADR); ! FIX J FIELD FOR WRITING
6696 MOD_FLD(0,TST_U_ADR+1); ! AND LOADING THE PAGE TABLE
6697
6698 INCR ERRN FROM 0 TO 17 DO
6699 (
6700 VMA = .INFO[.ERRN];
6701 SET_CRAM_ADR(TST_U_ADR);
6702 MOD_FLD(3,.VMA<N_FLD3>);
6703 CP(6); ! FRIGGING EXTRA CLOCK GETS H-TO-L FOR WRITE
6704
6705 );
6706
6707 SET_CRAM_ADR(TST_U_ADR); ! FIX J FIELD FOR READING
6708 MOD_FLD(0,TST_U_ADR+5);
6709
6710 ! WRITE 0'S ALL OVER PHY PAGE 1 FROM THE 8080 (BYPASS CACHE)
6711 DM(1000,0);
6712 SEND_NUL();
6713 DN(0);
6714 REPEAT(%O'376');
6715 DM(1400,0);
6716 SEND_NUL();
6717 DN(0);
6718 REPEAT(%O'376');
6719
6720 INCR ERRN FROM 0 TO 17 DO
6721 (
6722 VMA = .INFO[.ERRN];
6723 SET_CRAM_ADR(TST_U_ADR);
6724 MOD_FLD(3,.VMA<N_FLD3>);
6725 ERROR_LOOP(1)
6726 (
6727 SET_CRAM_ADR(TST_U_ADR);
6728 IF STEP_U_NEXT(4) EQL 0
6729 THEN
6730 (
6731 ERRINFO[0] = .VMA;
6732 ERRCAS(1,1,.VMA,SERIAL(36),12,ERRINFO);
6733 )
6734 ELSE
6735 NOERR(1);
6736 EXIT_LOOP(1,1);
6737 0
6738 );
6739 );
6740
6741 CE(0);
6742 PAGING_OFF;
6743 RPT_ERR_FLAG = 1;
6744
6745 !*MESSAGE 1
6746 !*STIMULUS:
6747 !* CHECK CACHE DIRECTORY RAM ADDRESS LINES
6748 !* KS10: MAP PHYSICAL PAGE 1 TO VIRTUAL PAGE 1
6749 !* WRITE \O0 TO VIRTUAL MEM LOC \O0 (CACHE ENABLED)
6750 !* ... FOR LOCS 0 AND 2**N FOR EACH SIDE OF RAM PAIRS
6751 !* 8080: ZERO PHYSICAL PAGE 1
6752 !*RESPONSE:
6753 !* KS10: READ VIRTUAL MEM LOC \O0
6754
6755 !]ERROR 1
6756 !]CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK
6757
6758 !]NO ERROR 1
6759 !]CD_ADR NTWK
6760
6761 END;
6762
6763 GLOBAL ROUTINE TST45: NOVALUE =
6764
6765 !++
6766 ! FUNCTIONAL DESCRIPTION:
6767 !
6768 ! TEST CACHE DIRECTORY SWEEP OPERATION
6769 !
6770 !--
6771
6772 BEGIN
6773
6774 LOCAL
6775 VMA;
6776
6777 LABEL
6778 LOOP1;
6779
6780 BIND
6781 TST_U_ADR = %O'660',
6782 TST_U = PLIT
6783 (
6784 %(0660)% U_J(661) V_DP_N(1377) U_B_T0 U_DEST_AD U,
6785 %(0661)% U_J(662) V_DP_N(1777) U_B_T1 U_DEST_AD U,
6786 %(0662)% U_J(663) V_DP_T0 U_MEM U_N(1010) U_SPEC_LDPAGE U,
6787 %(0663)% U_J(664) V_DP_N(460001) U,
6788 %(0664)% U_J(665) V_DP_T1 U_MEM U_N(30012) U,
6789 %(0665)% U_J(666) V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
6790 %(0666)% U_J(667) V_DP_T0 U_MEM U_N(30012) U_SPEC_CLRCSH U,
6791 %(0667)% U_J(670) V_DP_0 U_DBUS_DP U_MEM U_N(2) U,
6792 %(0670)% U_J(671) V_DP_T1 U_MEM U_N(40012) U,
6793 %(0671)% U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
6794 );
6795
6796 LOAD_TST_U;
6797
6798 PAGING_ON;
6799 CE(1);
6800 ERROR_LOOP(1)
6801 (
6802 SET_CRAM_ADR(TST_U_ADR);
6803 IF STEP_U_NEXT(10) EQL 0
6804 THEN
6805 ERR(1)
6806 ELSE
6807 NOERR(1);
6808 EXIT_LOOP(1,1);
6809 0
6810 );
6811
6812 CE(0);
6813 PAGING_OFF;
6814
6815 !*MESSAGE 1
6816 !*STIMULUS:
6817 !* MAP PAGE 1 TO PAGE 1
6818 !* WRITE -1 TO MEM LOC 1777
6819 !* WRITE 0 TO MEM LOC 1377 WITH SWEEP SET
6820 !* READ MEM LOC 1777, SKIP IF 0
6821 !*RESPONSE:
6822 !* SHOULD SKIP (BUT IT DIDN'T)
6823
6824 !]ERROR 1
6825 !]VMA_SWEEP_CD VMA_SWEEP SPEC_SWEEP CD_HIT CD_ADR CD_IO CD_CMP PT_CAC PT_USR PT_IO PT_ADR PT_MESS N_ALL NTWK
6826
6827 !]NO ERROR 1
6828 !]VMA_SWEEP_CD NTWK
6829
6830 END;
6831
6832 GLOBAL ROUTINE TST46: NOVALUE =
6833
6834 !++
6835 ! FUNCTIONAL DESCRIPTION:
6836 !
6837 ! CHECK CACHE HIT COMPARATORS' OUTPUTS STUCK HIGH
6838 !
6839 !--
6840
6841 BEGIN
6842
6843 LOCAL
6844 CRAM_ADR,
6845 OK;
6846
6847 OWN
6848 INFO: VECTOR[2] INITIAL(%O'400777', %O'20777');
6849
6850 LABEL
6851 LOOP1;
6852
6853 BIND
6854 TST_U_ADR = %O'700',
6855 TST_U = PLIT
6856 (
6857 %(0700)% U_J(701) V_DP_N(400777) U_B_T0 U_DEST_AD U, ! # CHANGES
6858 %(0701)% U_J(702) V_DP_N(000777) U_B_T1 U_DEST_AD U,
6859 %(0702)% U_J(703) V_DP_T0 U_MEM U_N(1010) U_SPEC_LDPAGE U,
6860 %(0703)% U_J(704) V_DP_N(460000) U,
6861 %(0704)% U_J(705) V_DP_T1 U_MEM U_N(1010) U_SPEC_LDPAGE U,
6862 %(0705)% U_J(706) V_DP_N(460000) U,
6863 %(0706)% U_J(707) V_DP_T0 U_MEM U_N(30012) U,
6864 %(0707)% V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
6865 %(0710)% U_J(711) V_DP_T1 U_MEM U_N(40012) U,
6866 %(0711)% U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
6867 ),
6868 TUA_VMA = TST_U_ADR + 0,
6869 TUA_TST = TST_U_ADR + 8;
6870
6871 LOAD_TST_U;
6872 OK = 1;
6873 PAGING_ON;
6874 CE(1);
6875
6876 INCR SUBTEST FROM 0 TO 1 DO
6877 ERROR_LOOP(1)
6878 (
6879 SET_CRAM_ADR(TUA_VMA);
6880 MOD_FLD(4,.INFO[.SUBTEST] ^ (-12)); ! VMA LOW BITS STAY OK
6881 CP(8);
6882 DM(777,0);
6883 SET_CRAM_ADR(TUA_TST);
6884 CRAM_ADR = STEP_U_NEXT(2);
6885 IF .CRAM_ADR NEQ 1 ! 1: SKIP: GOT 0: OK
6886 THEN
6887 (
6888 ERRINFO[0] = .INFO[.SUBTEST]; ! CHANGING VMA
6889 ERRINFO[1] = .INFO[.SUBTEST] ^ (-9); ! PAGE #
6890 ERRS(1,1,ERRINFO);
6891 OK = 0;
6892 );
6893 EXIT_LOOP(1,1);
6894 0
6895 );
6896
6897 IFN .OK THEN NOERR(1);
6898
6899 CE(0);
6900 PAGING_OFF;
6901
6902 !*MESSAGE 1
6903 !*STIMULUS:
6904 !* KS10: MAP PAGES \O1 AND 0 TO PAGE 0
6905 !* WRITE -1 TO VIRTUAL MEM LOC \O0
6906 !* 8080: WRITE 0 TO PHYSICAL MEM LOC 777
6907 !* KS10: READ VIRTUAL MEM LOC 777, SKIP IF 0
6908 !*RESPONSE:
6909 !* KS10: SHOULD SKIP = GOT 0 = CACHE MISS (DIDN'T)
6910
6911 !]ERROR 1
6912 !]CD_HIT CD_ADR CD_IO CD_CMP PT_CAC PT_USR PT_IO PT_ADR PT_MESS N_ALL NTWK
6913
6914 !]NO ERROR 1
6915 !] NTWK
6916
6917 END;
6918
6919 GLOBAL ROUTINE TST47: NOVALUE =
6920
6921 !++
6922 ! FUNCTIONAL DESCRIPTION:
6923 !
6924 ! CHECK CACHE DIR CACHE VALID PINS STUCK HIGH
6925 !
6926 !--
6927
6928 BEGIN
6929
6930 LOCAL
6931 OK,
6932 CRAM_ADR;
6933
6934 OWN
6935 INFO: VECTOR[2] INITIAL(%O'777', %O'377');
6936
6937 LABEL
6938 LOOP1;
6939
6940 BIND
6941 TST_U_ADR = %O'720',
6942 TST_U = PLIT
6943 (
6944 %(0720)% U_J(721) V_DP_N(777) U_B_T0 U_DEST_AD U, ! # CHANGES
6945 %(0721)% U_J(722) V_DP_T0 U_MEM U_N(1010) U_SPEC_LDPAGE U,
6946 %(0722)% U_J(723) V_DP_N(460000) U,
6947 %(0723)% U_J(724) V_DP_T0 U_MEM U_N(31012) U,
6948 %(0724)% V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
6949 %(0725)% U_J(726) V_DP_T0 U_MEM U_N(40012) U,
6950 %(0726)% U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
6951 ),
6952 TUA_VMA = TST_U_ADR + 0,
6953 TUA_TST = TST_U_ADR + 5;
6954
6955 LOAD_TST_U;
6956 OK = 1;
6957 CE(1);
6958 PAGING_ON;
6959
6960 INCR SUBTEST FROM 0 TO 1 DO
6961 ERROR_LOOP(1)
6962 (
6963 SET_CRAM_ADR(TUA_VMA);
6964 MOD_FLD(3,.INFO[.SUBTEST]); ! VMA HIGH BITS STAY OK
6965 CP(5);
6966 MEM_DEPOSIT(.INFO[.SUBTEST],0);
6967 SET_CRAM_ADR(TUA_TST);
6968 CRAM_ADR = STEP_U_NEXT(2);
6969 IF .CRAM_ADR NEQ 1 ! 1: SKIP: GOT 0: OK
6970 THEN
6971 (
6972 ERRINFO[0] = .INFO[.SUBTEST]; ! CHANGING VMA
6973 ERRS(1,1,ERRINFO);
6974 OK = 0;
6975 );
6976 EXIT_LOOP(1,1);
6977 0
6978 );
6979
6980 IFN .OK THEN NOERR(1);
6981
6982 CE(0);
6983 PAGING_OFF;
6984
6985 !*MESSAGE 1
6986 !*STIMULUS:
6987 !* KS10: MAP PAGE 0 TO PAGE 0
6988 !* WRITE -1 TO PHYSICAL MEM LOC \O0
6989 !* 8080: WRITE 0 TO PHYSICAL MEM LOC \O0
6990 !* KS10: READ VIRTUAL MEM LOC \O0, SKIP IF 0
6991 !*RESPONSE:
6992 !* KS10: SHOULD SKIP = GOT 0 = CACHE MISS (DIDN'T)
6993
6994 !]ERROR 1
6995 !]CD_VAL CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK
6996
6997 !]NO ERROR 1
6998 !]CD_VAL NTWK
6999
7000 END;
7001
7002 GLOBAL ROUTINE TST48: NOVALUE =
7003
7004 !++
7005 ! FUNCTIONAL DESCRIPTION:
7006 !
7007 ! TEST PAGE TABLE RAM CONTENTS
7008 ! CAUSE ECC ERROR ON EVERY VIRTUAL PAGE
7009 ! MAPPED TO PHYSICAL PAGES MAX_PAG[0], MAX_PAG[1]
7010 ! ALSO CHECKS FOR VALID OR WRITABLE BEING STUCK LOW
7011 ! ALSO TESTS USER STUCK HIGH OR STUCK LOW
7012 !
7013 ! 2901 REGISTER USAGE:
7014 ! 0 VMA
7015 ! 1 PTE
7016 ! 2 PMA
7017 ! 11 VMA FLAGS, VMA TO R/W MMC STATUS
7018 ! 12 PMA MASK FOR MMC STATUS
7019 ! 13 FORCE BITS FOR MMC STATUS
7020 !
7021 !--
7022
7023 BEGIN
7024
7025 LOCAL
7026 DAT,
7027 PTE,
7028 VMA,
7029 COR_PMA,
7030 ACT_PMA,
7031 TICKS,
7032 CRAM_ADR,
7033 LOOPING,
7034 PMA_HIGH_BIT,
7035 OK;
7036
7037 LABEL
7038 LOOP1;
7039
7040 BIND
7041 TST_U_ADR = %O'730',
7042 TST_U = PLIT
7043 (
7044 %(0730)% U_J(731) V_DP_N(440000) U_B(1) U_DEST_AD U, ! #<6:17>
7045 %(0731)% U_J(732) V_DP_NN(377777) U_B(2) U_DEST_AD U_NO_CLKL U, ! #<0:17>
7046 %(0732)% U_J(733) V_DP_NN(0) U_B(2) U_DEST_AD U_NO_CLKR U, ! #<6:17>
7047 %(0733)% U_J(734) V_DP_N(777) U_B(0) U_DEST_AD U,
7048 %(0734)% U_J(735) V_DP_NN(400376) U_B(13) U_DEST_AD U,
7049 %(0735)% U_J(736) V_DP_NN(100000) U_B(11) U_DEST_AD U_NO_CLKL U,
7050 %(0736)% U_J(737) V_DP_NN(17) U_B(12) U_DEST_AD U_NO_CLKR U,
7051 %(0737)% U_J(741) V_DP_NN(777777) U_B(12) U_DEST_AD U_NO_CLKL U,
7052 %(0740)% U_J(741) V_D_N(1000) U_A(0) U_B(0) U_ALU_ADD U_DEST_AD U_LSRC_0A U_RSRC_DA U,
7053 %(0741)% U_J(742) V_DP_NN(211200) U_B(11) U_DEST_AD U_NO_CLKR U,
7054 %(0742)% U_J(743) V_DP_R(11) U_MEM U_N(36) U,
7055 %(0743)% U_J(744) V_DP_R(13) U_MEM U_N(2) U,
7056 %(0744)% U_J(745) V_DP_R(0) U_MEM U_N(003010) U_SPEC_LDPAGE U, ! #<0:5>
7057 %(0745)% U_J(746) V_DP_R(1) U,
7058 %(0746)% U_J(747) V_DP_R(0) U_MEM U_N(032012) U, ! #<0:5>
7059 %(0747)% U_J(750) V_DP_0 U_MEM U_N(2) U,
7060 %(0750)% U_J(751) V_DP_R(0) U_MEM U_N(042012) U, ! #<0:5>
7061 %(0751)% U_J(752) U_MEM U_N(2) U,
7062 %(0752)% U_J(753) V_DP_NN(241200) U_B(11) U_DEST_AD U_NO_CLKR U,
7063 %(0753)% U_J(754) V_DP_R(11) U_MEM U_N(36) U,
7064 %(0754)% U_J(755) U_DBM_MEM U_DBUS_DBM U_LSRC_DA U_A(12) U_ALU_AND U_DEST_Q_AD U_MEM U_N(2) U,
7065 %(0755)% U_LSRC_AQ U_A(2) U_ALU_XOR U_SKIP_ADEQ0 U
7066 ),
7067 TUA_PAG = TST_U_ADR + 0, ! WHERE TO DIDDLE PAGE MAP
7068 TUA_VMA = TST_U_ADR + %O'10', ! WHERE TO INCREMENT VMA
7069 TUA_TST = TST_U_ADR + %O'11'; ! WHERE TO RESTART TEST
7070
7071 IFN .INH_PT_RAM THEN RETURN; ! FORGET IT IF HE SAID TO
7072
7073 LOAD_TST_U;
7074 PMA_HIGH_BIT = 0;
7075 RPT_ERR_FLAG = 0;
7076 OK = 1;
7077
7078 PAGING_ON;
7079
7080 INCR PHY_PAG FROM 0 TO 1 DO ! STUCK LOW, THEN STUCK HIGH
7081 (
7082 DAT = .MAX_PAG[.PHY_PAG];
7083 ERRINFO[0] = COR_PMA = (.DAT ^ 9) OR %O'777';
7084 ERRINFO[2] = PTE = %O'440000' OR .DAT;
7085
7086 ERRINFO[6] = .FORCE_NAME[.PHY_PAG]; ! TEST USER RAM BIT TOO
7087 SET_CRAM_ADR(TUA_TST+3);
7088 MOD_FLD(4,.FORCE_MODE[.PHY_PAG]); ! #<0:5>
7089 SET_CRAM_ADR(TUA_TST+5);
7090 MOD_FLD(4,.FORCE_MODE[.PHY_PAG] OR 3); ! #<0:5>
7091 SET_CRAM_ADR(TUA_TST+7);
7092 MOD_FLD(4,.FORCE_MODE[.PHY_PAG] OR 4); ! #<0:5>
7093
7094 SET_CRAM_ADR(TUA_PAG+1); ! LOW 18 BITS OF PMA
7095 MOD_FLD(3,.COR_PMA<N_FLD3>); ! #<6:17>
7096 MOD_FLD(4,.COR_PMA<N_FLD4>); ! #<0:5>
7097
7098 IF .COR_PMA<18,12> NEQ .PMA_HIGH_BIT
7099 THEN
7100 (
7101 SET_CRAM_ADR(TUA_PAG+2); ! HIGH BIT OF PMA
7102 PMA_HIGH_BIT = .COR_PMA<18,12>;
7103 MOD_FLD(3,.PMA_HIGH_BIT); ! #<6:17>
7104 );
7105
7106 SET_CRAM_ADR(TUA_PAG);
7107 MOD_FLD(3,.PTE<N_FLD3>); ! #<6:17>
7108
7109 INCR VIR_PAG FROM 0 TO %O'777' DO ! DO THE WHOLE THING
7110 (
7111 ERRINFO[3] = .VIR_PAG;
7112 ERRINFO[1] = VMA = (.VIR_PAG ^ 9) OR %O'777';
7113 IFN .VIR_PAG
7114 THEN
7115 (
7116 SET_CRAM_ADR(TUA_VMA);
7117 TICKS = 14;
7118 )
7119 ELSE
7120 TICKS = 21;
7121 LOOPING = 0; ! FIRST TIME THROUGH ERROR LOOP
7122 ERROR_LOOP(1)
7123 (
7124 IFN .LOOPING THEN SET_CRAM_ADR(TUA_TST);
7125 CRAM_ADR = STEP_U_NEXT(.TICKS);
7126 IF .CRAM_ADR EQL O7777 ! IF -1 WE HAD PAGE FAIL
7127 THEN
7128 (
7129 ERRINFO[4] = PF_TRAP();
7130 ERRINFO[5] = PF_NAME(.ERRINFO[4]);
7131 ERRS(1,1,ERRINFO);
7132 PAGING_ON;
7133 )
7134 ELSE
7135 IF .CRAM_ADR EQL 0 ! 1: SKIP: XOR=0: MATCH
7136 THEN
7137 (
7138 ACT_PMA = EI(100000) AND %O'17777777';
7139 ERRCAS(1,2,.COR_PMA,.ACT_PMA,8,ERRINFO);
7140 OK = 0;
7141 );
7142 LOOPING = 1;
7143 TICKS = 13;
7144 EXIT_LOOP(1,1);
7145 0
7146 );
7147 );
7148 );
7149
7150 IFN .OK THEN NOERR(1);
7151
7152 PAGING_OFF;
7153 RPT_ERR_FLAG = 1;
7154
7155 !*MESSAGE 1
7156 !*STIMULUS:
7157 !* LOAD \O2 INTO PAGE TABLE LOC \O3 (\S6)
7158 !* DEPOSIT 376 TO I/O REGISTER 100000
7159 !* (SETTING ALL MMC ECC FORCE BITS)
7160 !* DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC) (\S6)
7161 !* READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR) (\S6)
7162 !*RESPONSE:
7163 !* PAGE FAIL U-TRAP TO CRAM ADDR 7777 (SHOULDN'T HAPPEN)
7164 !* PAGE FAIL CODE \O4 (\S5)
7165
7166 !*MESSAGE 2
7167 !*STIMULUS:
7168 !* LOAD \O2 INTO PAGE TABLE LOC \O3 (\S6)
7169 !* DEPOSIT 376 TO I/O REGISTER 100000
7170 !* (SETTING ALL MMC ECC FORCE BITS)
7171 !* DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC) (\S6)
7172 !* READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR) (\S6)
7173 !* READ I/O REGISTER 100000 BITS <14:35>
7174 !*RESPONSE:
7175 !* SHOULD GET \O0 (PHYSICAL ADDR OF LAST ERROR)
7176
7177 !]ERROR 1
7178 !]PT_RAM_PAG_USR PT_IO PT_VAL_WRT PT_USR PT_MESS NTWK
7179
7180 !]NO ERROR 1
7181 !]PT_RAM_PAG_USR NTWK
7182
7183 END;
7184
7185 GLOBAL ROUTINE TST49: NOVALUE =
7186
7187 !++
7188 ! FUNCTIONAL DESCRIPTION:
7189 !
7190 ! TEST PAGE TABLE RAM CONTENTS
7191 ! VALID OR WRITABLE STUCK HIGH
7192 !
7193 !--
7194
7195 BEGIN
7196
7197 MACRO
7198 INFO_PTE = 0,0,18,0 %, ! # FOR PAGE TABLE ENTRY
7199 INFO_PTE_FLD4 = 0,12,6,0 %, ! #<0:5>
7200 INFO_PF_CAUSE = 1,0,36,0 %; ! CORRECT PAGE FAIL CAUSE
7201
7202 LOCAL
7203 COR_PF_CAUSE,
7204 VMA,
7205 TICKS,
7206 CRAM_ADR,
7207 LOOPING,
7208 OK;
7209
7210 OWN
7211 INFO: BLOCKVECTOR[2,2] INITIAL
7212 (
7213 %O'040000', %O'12', ! INVALID
7214 %O'400000', %O'10' ! UNWRITABLE
7215 );
7216
7217 LABEL
7218 LOOP1;
7219
7220 BIND
7221 TST_U_ADR = %O'760',
7222 TST_U = PLIT
7223 (
7224 %(0760)% U_J(761) V_DP_N(440000) U_B(1) U_DEST_AD U, ! #
7225 %(0761)% U_J(763) V_DP_N(777) U_B(0) U_DEST_AD U,
7226 %(0762)% U_J(763) V_D_N(1000) U_A(0) U_B(0) U_ALU_ADD U_DEST_AD U_LSRC_0A U_RSRC_DA U,
7227 %(0763)% U_J(764) V_DP_R(0) U_MEM U_N(3010) U_SPEC_LDPAGE U, ! #
7228 %(0764)% U_J(765) V_DP_R(1) U,
7229 %(0765)% U_J(766) V_DP_R(0) U_MEM U_N(32012) U, ! #
7230 %(0766)% U_J(7777) V_DP_0 U_MEM U_N(2) U ! J IN CASE NO PF
7231 ),
7232 TUA_PAG = TST_U_ADR + 0, ! WHERE TO DIDDLE PAGE MAP
7233 TUA_VMA = TST_U_ADR + 2, ! WHERE TO INCREMENT VMA
7234 TUA_TST = TST_U_ADR + 3; ! WHERE TO RESTART TEST
7235
7236 IFN .INH_PT_RAM THEN RETURN; ! FORGET IT IF HE SAID TO
7237
7238 LOAD_TST_U;
7239 OK = 1;
7240 RPT_ERR_FLAG = 0;
7241
7242 SET_CRAM_ADR(PHU_ADR);
7243 MOD_FLD(0,PFU_ADR+1); ! ALWAYS DISPATCH (DON'T HANG)
7244 PAGING_ON;
7245
7246 INCR SUBTEST FROM 0 TO 1 DO
7247 (
7248 ERRINFO[2] = .INFO[.SUBTEST,INFO_PTE];
7249 SET_CRAM_ADR(TUA_PAG);
7250 MOD_FLD(4,.INFO[.SUBTEST,INFO_PTE_FLD4]);
7251
7252 ERRINFO[8] = COR_PF_CAUSE = .INFO[.SUBTEST,INFO_PF_CAUSE];
7253 ERRINFO[9] = PF_NAME(.ERRINFO[8]);
7254
7255 INCR VIR_PAG FROM 0 TO %O'777' DO ! DO THE WHOLE THING
7256 (
7257 ERRINFO[3] = .VIR_PAG;
7258 VMA = (.VIR_PAG ^ 9) OR %O'777';
7259 IFN .VIR_PAG
7260 THEN
7261 (
7262 SET_CRAM_ADR(TUA_VMA);
7263 TICKS = 7;
7264 )
7265 ELSE
7266 TICKS = 8;
7267 LOOPING = 0; ! FIRST TIME THROUGH ERROR LOOP
7268 ERROR_LOOP(1)
7269 (
7270 IFN .LOOPING THEN SET_CRAM_ADR(TUA_TST);
7271 ERRINFO[4] = CRAM_ADR = STEP_U_NEXT(.TICKS);
7272 ERRINFO[5] = PF_NAME(.ERRINFO[4]);
7273 IF .CRAM_ADR NEQ .COR_PF_CAUSE
7274 THEN
7275 (
7276 ERRS(1,1,ERRINFO);
7277 OK = 0;
7278 );
7279 ! PAGE FAIL RE-INIT
7280 MR();
7281 SET_CRAM_ADR(TIU_ADR);
7282 CP_NOSS(TIU_CNT);
7283 PAGING_ON;
7284 ! GET READY TO DO IT OVER (IF ERROR OCCURED)
7285 LOOPING = 1;
7286 TICKS = 6;
7287 EXIT_LOOP(1,1);
7288 0
7289 );
7290 );
7291 );
7292
7293 IFN .OK THEN NOERR(1);
7294
7295 PAGING_OFF;
7296 SET_CRAM_ADR(PHU_ADR);
7297 MOD_FLD(0,O7777); ! GO BACK TO HANGING AS USUAL
7298 RPT_ERR_FLAG = 1;
7299
7300 !*MESSAGE 1
7301 !*STIMULUS:
7302 !* LOAD \O2 INTO PAGE TABLE LOC \O3
7303 !* DEPOSIT 0 TO VIRTUAL MEM LOC 777
7304 !* DO A PAGE FAIL DISPATCH
7305 !*RESPONSE:
7306 !* CORRECT: PAGE FAIL CODE \O8 (\S9)
7307 !* ACTUAL: PAGE FAIL CODE \O4 (\S5)
7308
7309 !]ERROR 1
7310 !]PT_RAM_VAL_WRT PT_IO PT_VAL_WRT PT_USR PT_MESS PF_CODE NTWK
7311
7312 !]NO ERROR 1
7313 !]PT_RAM_VAL_WRT NTWK
7314
7315 END;
7316
7317 GLOBAL ROUTINE TST50: NOVALUE =
7318
7319 !++
7320 ! FUNCTIONAL DESCRIPTION:
7321 !
7322 ! TEST CACHE DIRECTORY RAM CONTENTS
7323 ! CACHE HIT TEST AT EACH LOC ON PAGES 1, 776
7324 ! ALSO CHECKS FOR VALID BEING STUCK LOW
7325 ! ALSO TESTS USER STUCK HIGH OR STUCK LOW
7326 !
7327 !--
7328
7329 BEGIN
7330
7331 LOCAL
7332 VMA,
7333 PF_CAUSE,
7334 CRAM_ADR,
7335 TICKS,
7336 LOOPING;
7337
7338 OWN
7339 VIR_PAG: VECTOR[2] INITIAL(1, %O'776');
7340
7341 LABEL
7342 LOOP1;
7343
7344 BIND
7345 TST_U_ADR = %O'770',
7346 TST_U = PLIT
7347 (
7348 %(0770)% U_J(775) U_A_BR U_B(0) U_LSRC_AB U_ALU_ADD U_DEST_AD U, ! J
7349 %(0771)% U_J(777) U_A_BR U_B(0) U_LSRC_AB U_ALU_ADD U_DEST_AD U,
7350 %(0772)% U_J(773) V_DP_N(1000) U_B(0) U_DEST_AD U, ! J, #
7351 %(0773)% U_J(774) V_DP_R(0) U_MEM U_N(1010) U_SPEC_LDPAGE U, ! #
7352 %(0774)% U_J(775) V_DP_N(460001) U,
7353 %(0775)% U_J(776) V_DP_R(0) U_MEM U_N(10012) U, ! #
7354 %(0776)% U_J(770) V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
7355 %(0777)% U_J(1000) V_DP_R(0) U_MEM U_N(40012) U, ! #
7356 %(1000)% U_J(770) V_DP_D U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
7357 ),
7358 TUA_J = TST_U_ADR + 0, ! JUMP TO AFTER INCR'NG VMA
7359 TUA_VMA = TST_U_ADR + 2, ! VMA TO USE
7360 TUA_LD_PT = TST_U_ADR + 3, ! # TO LOAD PAGE TABLE
7361 TUA_WRITE = TST_U_ADR + 5, ! # TO DO THE WRITE
7362 TUA_READ = TST_U_ADR + 7; ! # TO DO THE READ
7363
7364 IFN .INH_CD_RAM THEN RETURN; ! FORGET IT IF HE SAID TO
7365
7366 LOAD_TST_U;
7367 RPT_ERR_FLAG = 0;
7368
7369 PAGING_ON;
7370 CE(1); ! MAKE THE CACHE WORK
7371
7372 INCR ERRN FROM 0 TO 1 DO
7373 (
7374 ERRINFO[0] = .VIR_PAG[.ERRN];
7375 VMA = .VIR_PAG[.ERRN] ^ 9;
7376 ERRINFO[5] = .FORCE_NAME[.ERRN];
7377
7378 SET_CRAM_ADR(TUA_READ);
7379 MOD_FLD(4,.FORCE_MODE[.ERRN] + 4);
7380
7381 SET_CRAM_ADR(TUA_WRITE);
7382 MOD_FLD(4,.FORCE_MODE[.ERRN] + 1);
7383
7384 SET_CRAM_ADR(TUA_LD_PT);
7385 MOD_FLD(4,.FORCE_MODE[.ERRN]);
7386
7387 SET_CRAM_ADR(TUA_J);
7388 MOD_FLD(0,TUA_WRITE);
7389
7390 SET_CRAM_ADR(TUA_VMA);
7391 MOD_FLD(0,TUA_LD_PT);
7392 MOD_FLD(3,.VMA<N_FLD3>);
7393 MOD_FLD(4,.VMA<N_FLD4>);
7394
7395 CP(3 + (3 * 512)); ! WRITE -1 ALL OVER PAGE FROM KS10
7396
7397 ! WRITE 0'S ALL OVER PHY PAGE 1 FROM THE 8080 (BYPASS CACHE)
7398 DM(1000,0);
7399 SEND_NUL();
7400 DN(0);
7401 REPEAT(%O'376');
7402 DM(1400,0);
7403 SEND_NUL();
7404 DN(0);
7405 REPEAT(%O'376');
7406
7407 SET_CRAM_ADR(TUA_J);
7408 MOD_FLD(0,TUA_READ);
7409
7410 SET_CRAM_ADR(TUA_VMA);
7411 MOD_FLD(0,TUA_READ);
7412
7413 INCR OFFSET FROM 0 TO %O'777' DO ! SEE IF WE GET HITS
7414 (
7415 ERRINFO[1] = .VMA + .OFFSET;
7416 ERRINFO[2] = %O'1000' + .OFFSET;
7417 LOOPING = 0;
7418 ERROR_LOOP(1)
7419 (
7420 IFN .LOOPING
7421 THEN
7422 (
7423 SET_CRAM_ADR(TUA_READ);
7424 TICKS = 2;
7425 )
7426 ELSE
7427 TICKS = 3;
7428 CRAM_ADR = STEP_U_NEXT(.TICKS);
7429 IF .CRAM_ADR EQL O7777 ! SHOULDN'T PAGE FAIL
7430 THEN
7431 (
7432 ERRINFO[3] = PF_TRAP();
7433 ERRINFO[4] = PF_NAME(.ERRINFO[3]);
7434 ERRS(1,2,ERRINFO);
7435 PAGING_ON;
7436 CE(1); ! MAKE THE CACHE WORK
7437 SET_CRAM_ADR(TUA_J);
7438 )
7439 ELSE
7440 IF .CRAM_ADR ! SKIPPING SETS LOW BIT
7441 THEN
7442 ERRS(1,1,ERRINFO)
7443 ELSE
7444 NOERR(1);
7445 LOOPING = 1;
7446 EXIT_LOOP(1,1);
7447 0
7448 );
7449 );
7450 );
7451
7452 PAGING_OFF;
7453 CE(0); ! MAKE THE CACHE QUIT
7454 RPT_ERR_FLAG = 1;
7455
7456 !*MESSAGE 1
7457 !*STIMULUS:
7458 !* KS10: MAP PAGE \O0 TO PAGE 1, \S5 MODE
7459 !* WRITE -1 TO VIR MEM LOC \O1
7460 !* 8080: WRITE 0 TO PHY MEM LOC \O2
7461 !* KS10: READ VIR MEM LOC \O1
7462 !*RESPONSE:
7463 !* SHOULD GET -1 (CACHE HIT); DON'T
7464
7465 !*MESSAGE 2
7466 !*STIMULUS:
7467 !* KS10: MAP PAGE \O0 TO PAGE 1, \S5 MODE
7468 !* WRITE -1 TO VIR MEM LOC \O1
7469 !* 8080: WRITE 0 TO PHY MEM LOC \O2
7470 !* KS10: READ VIR MEM LOC \O1
7471 !*RESPONSE:
7472 !* SHOULD GET -1 (CACHE HIT) BUT PAGE FAIL HAPPENED
7473 !* PAGE FAIL CODE \O3 (\S4)
7474
7475 !]ERROR 1
7476 !]CD_RAM_PAG_USR CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK
7477
7478 !]NO ERROR 1
7479 !]CD_RAM_PAG_USR NTWK
7480
7481 END;
7482
7483 GLOBAL ROUTINE TST51: NOVALUE =
7484
7485 !++
7486 ! FUNCTIONAL DESCRIPTION:
7487 !
7488 ! TEST CACHE DIRECTORY RAM CONTENTS
7489 ! CACHE ENTRY VALID STUCK HIGH AT EACH LOC ON PAGE 1
7490 !
7491 !--
7492
7493 BEGIN
7494
7495 LOCAL
7496 PF_CAUSE,
7497 CRAM_ADR,
7498 TICKS,
7499 LOOPING;
7500
7501 LABEL
7502 LOOP1;
7503
7504 BIND
7505 TST_U_ADR = %O'1010',
7506 TST_U = PLIT
7507 (
7508 %(1010)% U_J(1015) U_A_BR U_B(0) U_LSRC_AB U_ALU_ADD U_DEST_AD U, ! J
7509 %(1011)% U_J(1017) U_A_BR U_B(0) U_LSRC_AB U_ALU_ADD U_DEST_AD U,
7510 %(1012)% U_J(1013) V_DP_N(1000) U_B(0) U_DEST_AD U, ! J
7511 %(1013)% U_J(1014) V_DP_R(0) U_MEM U_N(1010) U_SPEC_LDPAGE U,
7512 %(1014)% U_J(1015) V_DP_N(460001) U,
7513 %(1015)% U_J(1016) V_DP_R(0) U_MEM U_N(11012) U,
7514 %(1016)% U_J(1010) V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
7515 %(1017)% U_J(1020) V_DP_R(0) U_MEM U_N(40012) U,
7516 %(1020)% U_J(1010) V_DP_D U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
7517 ),
7518 TUA_J = TST_U_ADR + 0, ! JUMP TO AFTER INCR'NG VMA
7519 TUA_VMA = TST_U_ADR + 2, ! VMA TO USE
7520 TUA_LD_PT = TST_U_ADR + 3, ! # TO LOAD PAGE TABLE
7521 TUA_WRITE = TST_U_ADR + 5, ! # TO DO THE WRITE
7522 TUA_READ = TST_U_ADR + 7; ! # TO DO THE READ
7523
7524 IFN .INH_CD_RAM THEN RETURN; ! FORGET IT IF HE SAID TO
7525
7526 LOAD_TST_U;
7527 RPT_ERR_FLAG = 0;
7528
7529 PAGING_ON;
7530 CE(1); ! MAKE THE CACHE WORK
7531
7532 SET_CRAM_ADR(TUA_J);
7533 MOD_FLD(0,TUA_WRITE);
7534
7535 SET_CRAM_ADR(TUA_VMA);
7536 MOD_FLD(0,TUA_LD_PT);
7537
7538 CP(3 + (3 * 512)); ! WRITE -1 ALL OVER PAGE FROM KS10
7539
7540 ! WRITE 0'S ALL OVER PHY PAGE 1 FROM THE 8080(BYPASS CACHE)
7541 DM(1000,0);
7542 SEND_NUL();
7543 DN(0);
7544 REPEAT(%O'376');
7545 DM(1400,0);
7546 SEND_NUL();
7547 DN(0);
7548 REPEAT(%O'376');
7549
7550 SET_CRAM_ADR(TUA_J);
7551 MOD_FLD(0,TUA_READ);
7552
7553 SET_CRAM_ADR(TUA_VMA);
7554 MOD_FLD(0,TUA_READ);
7555
7556 INCR OFFSET FROM 0 TO %O'777' DO ! SEE IF WE GET HITS
7557 (
7558 ERRINFO[1] = ERRINFO[2] = %O'1000' + .OFFSET;
7559 LOOPING = 0;
7560 ERROR_LOOP(1)
7561 (
7562 IFN .LOOPING
7563 THEN
7564 (
7565 SET_CRAM_ADR(TUA_READ);
7566 TICKS = 2;
7567 )
7568 ELSE
7569 TICKS = 3;
7570 CRAM_ADR = STEP_U_NEXT(.TICKS);
7571 IF .CRAM_ADR EQL O7777 ! SHOULDN'T PAGE FAIL
7572 THEN
7573 (
7574 ERRINFO[3] = PF_TRAP();
7575 ERRINFO[4] = PF_NAME(.ERRINFO[3]);
7576 ERRS(1,2,ERRINFO);
7577 PAGING_ON;
7578 CE(1); ! MAKE THE CACHE WORK
7579 SET_CRAM_ADR(TUA_J);
7580 )
7581 ELSE
7582 IF .CRAM_ADR<0,1> EQL 0 ! SKIPPING SETS LOW BIT
7583 THEN
7584 ERRS(1,1,ERRINFO)
7585 ELSE
7586 NOERR(1);
7587 LOOPING = 1;
7588 EXIT_LOOP(1,1);
7589 0
7590 );
7591 );
7592
7593 PAGING_OFF;
7594 CE(0); ! MAKE THE CACHE QUIT
7595 RPT_ERR_FLAG = 1;
7596
7597 !*MESSAGE 1
7598 !*STIMULUS:
7599 !* KS10: MAP PAGE 1 TO PAGE 1
7600 !* WRITE -1 TO PHY MEM LOC \O1
7601 !* 8080: WRITE 0 TO PHY MEM LOC \O2
7602 !* KS10: READ VIR MEM LOC \O1
7603 !*RESPONSE:
7604 !* SHOULD GET 0 (CACHE MISS); DON'T
7605
7606 !*MESSAGE 2
7607 !*STIMULUS:
7608 !* KS10: MAP PAGE 1 TO PAGE 1
7609 !* WRITE -1 TO PHY MEM LOC \O1
7610 !* 8080: WRITE 0 TO PHY MEM LOC \O2
7611 !* KS10: READ VIR MEM LOC \O1
7612 !*RESPONSE:
7613 !* SHOULD GET 0 (CACHE MISS) BUT PAGE FAIL HAPPENED
7614 !* PAGE FAIL CODE \O3 (\S4)
7615
7616 !]ERROR 1
7617 !]CD_RAM_VAL CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK
7618
7619 !]NO ERROR 1
7620 !]CD_RAM_VAL NTWK
7621
7622 END;
7623
7624 GLOBAL ROUTINE TST52: NOVALUE =
7625
7626 !++
7627 ! FUNCTIONAL DESCRIPTION:
7628 !
7629 ! TEST PAGE TABLE RAM CONTENTS
7630 ! CACHABLE STUCK HIGH OR LOW
7631 !
7632 !--
7633
7634 BEGIN
7635
7636 LOCAL
7637 PF_CAUSE,
7638 VMA,
7639 TICKS,
7640 CRAM_ADR,
7641 LOOPING,
7642 OK;
7643
7644 OWN
7645 PTE: INITIAL(%O'440000'),
7646 INFO: VECTOR[2] INITIAL
7647 (
7648 UPLIT(%ASCIZ '-1 (CACHE MISS)'),
7649 UPLIT(%ASCIZ '0 (CACHE HIT)')
7650 );
7651
7652 LABEL
7653 LOOP1;
7654
7655 BIND
7656 TST_U_ADR = %O'1020',
7657 TST_U = PLIT
7658 (
7659 %(1020)% U_J(1023) V_D_N(1000) U_A(0) U_B(0) U_ALU_ADD U_DEST_AD U_LSRC_0A U_RSRC_DA U,
7660 %(1021)% U_J(1023) V_D_N(1000) U_A(0) U_B(0) U_ALU_ADD U_DEST_AD U_LSRC_0A U_RSRC_DA U,
7661 %(1022)% U_J(1023) V_DP_N(777) U_B(0) U_DEST_AD U,
7662 %(1023)% U_J(1024) V_DP_R(0) U_MEM U_N(3010) U_SPEC_LDPAGE U,
7663 %(1024)% U_J(1025) V_DP_N(460000) U, ! #
7664 %(1025)% U_J(1026) V_DP_R(0) U_MEM U_N(30012) U,
7665 %(1026)% U_J(1027) V_DP__1 U_DBUS_DP U_MEM U_N(2) U,
7666 %(1027)% U_J(1030) V_DP_R(0) U_MEM U_N(40012) U,
7667 %(1030)% U_J(1020) U_MEM U_N(2) V_DP_D U_SKIP_ADEQ0 U_DBM_MEM U_DBUS_DBM U
7668 ),
7669 TUA_PAG = TST_U_ADR + 4, ! WHERE TO DIDDLE PAGE MAP
7670 TUA_VMA = TST_U_ADR + 2, ! WHERE TO INCREMENT VMA
7671 TUA_TST = TST_U_ADR + 3; ! WHERE TO RESTART TEST
7672
7673 IFN .INH_PT_RAM THEN RETURN; ! FORGET IT IF HE SAID TO
7674
7675 LOAD_TST_U;
7676 OK = 1;
7677 RPT_ERR_FLAG = 0;
7678 CE(1); ! LET THE CACHE WORK IT IT WANTS
7679
7680 PAGING_ON;
7681
7682 INCR SUBTEST FROM 0 TO 1 DO
7683 (
7684 ERRINFO[1] = .INFO[.SUBTEST];
7685
7686 PTE<13,1> = .SUBTEST; ! PAGE CACHABLE BIT
7687 ERRINFO[2] = .PTE;
7688 SET_CRAM_ADR(TUA_PAG);
7689 MOD_FLD(4,.PTE<N_FLD4>);
7690
7691 SET_CRAM_ADR(TUA_VMA);
7692
7693 INCR VIR_PAG FROM 0 TO %O'777' DO ! DO THE WHOLE THING
7694 (
7695 ERRINFO[3] = .VIR_PAG;
7696 ERRINFO[0] = VMA = (.VIR_PAG ^ 9) OR %O'777';
7697 LOOPING = 0; ! FIRST TIME THROUGH ERROR LOOP
7698 ERROR_LOOP(1)
7699 (
7700 IF .LOOPING EQL 0
7701 THEN
7702 TICKS = 5
7703 ELSE
7704 (
7705 SET_CRAM_ADR(TUA_TST);
7706 TICKS = 4;
7707 );
7708 CP(.TICKS); ! GET PAST WRITE
7709 DM(777,0); ! ZAP IN MAIN MEMORY
7710 CRAM_ADR = STEP_U_NEXT(2); ! READ IT BACK
7711 IF .CRAM_ADR EQL O7777
7712 THEN
7713 (
7714 ERRINFO[4] = PF_TRAP();
7715 ERRINFO[5] = PF_NAME(.ERRINFO[4]);
7716 ERRS(1,1,ERRINFO);
7717 OK = 0;
7718 PAGING_ON;
7719 )
7720 ELSE
7721 IF .SUBTEST EQL .CRAM_ADR<0,1>
7722 THEN
7723 (
7724 ERRINFO[6] = .SUBTEST;
7725 ERRINFO[7] = .CRAM_ADR<0,1>;
7726 ERRS(1,2,ERRINFO);
7727 OK = 0;
7728 );
7729 ! GET READY TO DO IT OVER (IF ERROR OCCURED)
7730 LOOPING = 1;
7731 EXIT_LOOP(1,1);
7732 0
7733 );
7734 );
7735 );
7736
7737 IFN .OK THEN NOERR(1);
7738
7739 CE(0); ! MAKE THE CACHE GO AWAY AGAIN
7740 PAGING_OFF;
7741 RPT_ERR_FLAG = 1;
7742
7743 !*MESSAGE 1
7744 !*STIMULUS:
7745 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
7746 !* DEPOSIT -1 TO VIRTUAL MEM LOC \O0
7747 !* 8080: DEPOSIT 0 TO PHYSICAL MEM LOC 777
7748 !* KS10: READ VIRTUAL MEM LOC \O0
7749 !*RESPONSE:
7750 !* SHOULD GET \S1 (BUT GOT PAGE FAIL)
7751 !* PAGE FAIL CODE \O4 (\S5)
7752
7753 !*MESSAGE 2
7754 !*STIMULUS:
7755 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
7756 !* DEPOSIT -1 TO VIRTUAL MEM LOC \O0
7757 !* 8080: DEPOSIT 0 TO PHYSICAL MEM LOC 777
7758 !* KS10: READ VIRTUAL MEM LOC \O0
7759 !*RESPONSE:
7760 !* SHOULD GET \S1 (BUT DIDN'T)
7761
7762 ! THERE USED TO BE A "PT_ALL" BELOW, BUT I THINK IT OUGHT TO BE "N_ALL"
7763
7764 !]ERROR 1
7765 !]PT_RAM_CAC CD_IO CD_CMP CD_HIT PT_IO PT_ADR PT_CAC PT_MESS N_ALL NTWK
7766
7767 !]NO ERROR 1
7768 !]PT_RAM_CAC NTWK
7769
7770 END;
7771
7772 GLOBAL ROUTINE TST53: NOVALUE =
7773
7774 !++
7775 ! FUNCTIONAL DESCRIPTION:
7776 !
7777 ! CHECK FOR MEMORY BUS PARITY ERRORS
7778 !
7779 !--
7780
7781 BEGIN
7782
7783 LOCAL
7784 OK,
7785 COM_ADR_ERR,
7786 TICKS,
7787 CRAM_ADR,
7788 PAR_ERR,
7789 NXT_DAT,
7790 DAT,
7791 LOOPING;
7792
7793 LABEL
7794 LOOP1,
7795 LOOP2;
7796
7797 BIND
7798 TST_U_ADR = %O'1040',
7799 TST_U = PLIT
7800 (
7801 %(1040)% U_J(1042) V_DP_R(5) U_B_T0 U_DEST_AD_DIV2 U, ! BR = 5
7802 %(1041)% U_J(1042) U_A_T0 U_B_T0 U_LSRC_AB U_ALU_ADD U_DEST_AD U,
7803 %(1042)% U_J(1043) V_DP_0 U_MEM U_N(11012) U,
7804 %(1043)% U_J(1044) V_DP_T0 U_DBUS_DP U_MEM U_N(2) U,
7805 %(1044)% U_J(1045) V_DP_0 U_MEM U_N(41012) U,
7806 %(1045)% U_J(1046) U_MEM U_N(2) U_DBM_MEM U_DBUS_DBM V_CHK U,
7807 %(1046)% U_J(1041) U ! NOP
7808 ),
7809 TUA_INIT = TST_U_ADR + 0, ! INITIALIZE DATA TO WRITE
7810 TUA_NEXT = TST_U_ADR + 1, ! SHIFT DATA UP TO NEXT BIT
7811 TUA_TST = TST_U_ADR + 2; ! RESTART TEST (FOR LOOPING)
7812
7813 LOAD_TST_U;
7814 RPT_ERR_FLAG = 0;
7815 COM_ADR_ERR = 0; ! ALL IS WELL (SO FAR)
7816
7817 ERROR_LOOP(1)
7818 (
7819 SET_CRAM_ADR(TUA_INIT); ! WORRY ABOUT COM/ADR PAR ERR
7820 CP(2);
7821 PAR_ERR = RD_100;
7822 IFN ((NOT .PAR_ERR) AND %O'14')
7823 THEN
7824 (
7825 COM_ADR_ERR = 1; ! REMEMBER THAT WE LOST
7826 ERRINFO[6] = .PAR_ERR<2,1>; ! DP PE L
7827 ERRINFO[7] = .PAR_ERR<3,1>; ! MEM PE L
7828 ERRS(1,1,ERRINFO);
7829 MR(); ! CLEAR FAULT
7830 );
7831 EXIT_LOOP(1,1);
7832 0
7833 );
7834 IFN .COM_ADR_ERR THEN RETURN; ! FATAL, GIVE UP
7835
7836 SET_CRAM_ADR(TUA_INIT); ! START THE REAL TEST
7837 DAT = 0;
7838 NXT_DAT = 1;
7839
7840 INCR ERRN FROM 0 TO 36 DO ! 0, THEN 2**N FOR N=0 TO 35
7841 (
7842 LOOPING = 0; ! FIRST TIME THROUGH ERROR LOOP
7843 ERRINFO[0] = .DAT;
7844 DAT = .NXT_DAT;
7845 NXT_DAT = .NXT_DAT ^ 1;
7846
7847 ERROR_LOOP(2)
7848 (
7849 IF .LOOPING EQL 0
7850 THEN
7851 TICKS = 3
7852 ELSE
7853 (
7854 SET_CRAM_ADR(TUA_TST);
7855 TICKS = 2;
7856 );
7857
7858 INCR RW FROM 0 TO 1 DO ! WRITE, THEN READ
7859 (
7860 CRAM_ADR = STEP_U_NEXT(.TICKS); ! GET PAST WRITE
7861 PAR_ERR = RD_100;
7862 IFN ((NOT .PAR_ERR) AND %O'14')
7863 THEN
7864 (
7865 ERRINFO[6] = .PAR_ERR<2,1>; ! DP PE L
7866 ERRINFO[7] = .PAR_ERR<3,1>; ! MEM PE L
7867 ERRS(1,2 + .RW,ERRINFO);
7868 MR(); ! CLEAR FAULT
7869 SET_CRAM_ADR ! MR SCREWS IT
7870 (TUA_TST + (IF .RW THEN 2 ELSE 0));
7871 OK = 0;
7872 );
7873 TICKS = 3;
7874 );
7875 LOOPING = 1;
7876 EXIT_LOOP(2,(.ERRN + 2));
7877 0
7878 );
7879 );
7880
7881 IFN .OK THEN NOERR(1);
7882
7883 RPT_ERR_FLAG = 1;
7884
7885 !*MESSAGE 1
7886 !*STIMULUS:
7887 !* KS10: WRITE TO PHYSICAL MEM LOC 0
7888 !* STOP AFTER COMMAND/ADDRESS CYCLE
7889 !*RESPONSE:
7890 !* SHOULDN'T INDICATE PARITY ERROR (BUT IT DID)
7891 !* MEM PARITY ERROR L = \O7; DP PARITY ERROR L = \O6
7892
7893 !*MESSAGE 2
7894 !*STIMULUS:
7895 !* KS10: WRITE \U0 TO PHYSICAL MEM LOC 0
7896 !* 8080: READ REGISTER 100
7897 !*RESPONSE:
7898 !* SHOULDN'T INDICATE PARITY ERROR (BUT IT DID)
7899 !* MEM PARITY ERROR L = \O7; DP PARITY ERROR L = \O6
7900
7901 !*MESSAGE 3
7902 !*STIMULUS:
7903 !* KS10: WRITE \U0 TO PHYSICAL MEM LOC 0
7904 !* READ FROM PHYSICAL MEM LOC 0
7905 !* 8080: READ REGISTER 100
7906 !*RESPONSE:
7907 !* SHOULDN'T INDICATE PARITY ERROR (BUT IT DID)
7908 !* MEM PARITY ERROR L = \O7; DP PARITY ERROR L = \O6
7909
7910 !]ERROR 1
7911 !]BUS_PAR BUS_ALL BUS_MUX NTWK
7912
7913 !]NO ERROR 1
7914 !]BUS_PAR NTWK
7915
7916 END;
7917
7918 GLOBAL ROUTINE TST54: NOVALUE =
7919
7920 !++
7921 ! FUNCTIONAL DESCRIPTION:
7922 !
7923 ! APR FLAGS
7924 !
7925 ! (ORIGINALLY WRITTEN BY JEAN BASMAJI)
7926 !
7927 !--
7928
7929 BEGIN
7930
7931 LOCAL
7932 OK,
7933 ACT_APR;
7934
7935 LABEL
7936 LOOP1,
7937 LOOP2,
7938 LOOP3,
7939 LOOP4,
7940 LOOP5,
7941 LOOP6,
7942 LOOP7,
7943 LOOP8;
7944
7945 BIND
7946 TST_U_ADR = %O'2000',
7947 TST_U_1 = PLIT
7948 (
7949 %(2000)% U_J(2001) V_DP_N(7760) U_DEST_AD U_SPEC_APRFLAGS U,
7950 %(2001)% U_J(2002) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
7951 %(2002)% U_ALU_XOR U_A(0) U_LSRC_AQ U_SKIP_ADEQ0 U
7952 ),
7953 TST_U_2 = PLIT
7954 (
7955 %(2000)% U_J(2001) V_DP_N(7760) U_DEST_AD U,
7956 %(2001)% U_J(2002) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
7957 %(2002)% U_ALU_XOR U_A(0) U_LSRC_AQ U_SKIP_ADEQ0 U
7958 ),
7959 TST_U_3_4 = PLIT
7960 (
7961 %(2000)% U_J(2001) V_DP_N(7760) U_DEST_AD U, ! 4 ONLY
7962 %(2001)% U_J(2002) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
7963 %(2002)% U_ALU_AND U_A(0) U_LSRC_AQ U_SKIP_ADEQ0 U
7964 ),
7965 TST_U_5 = PLIT
7966 (
7967 %(2000)% U_J(2001) V_DP_N(0) U_SPEC_APRFLAGS U,
7968 %(2001)% U_J(2002) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
7969 %(2002)% U_ALU_AND U_A(0) U_LSRC_AQ U_SKIP_ADEQ0 U
7970 ),
7971 TST_U_6 = PLIT
7972 (
7973 %(2000)% U_J(2001) V_DP_N(100) U_DEST_AD U,
7974 %(2001)% U_J(2002) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
7975 %(2002)% U_ALU_XOR U_A(0) U_LSRC_AQ U_SKIP_ADEQ0 U
7976 ),
7977 TST_U_7 = PLIT
7978 (
7979 %(2000)% U_J(2003) V_DP_N(400) U_DEST_AD U,
7980 %(2001)% U_J(2002) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
7981 %(2002)% U_ALU_XOR U_A(0) U_LSRC_AQ U_SKIP_ADEQ0 U,
7982 %(2003)% U_J(2004) V_DP__1 U_MEM U_N(43016) U,
7983 %(2004)% U_J(2001) U_MEM U_N(2) U
7984 ),
7985 TST_U_8 = PLIT
7986 (
7987 %(2000)% U_J(2003) V_DP_N(200) U_DEST_AD U,
7988 %(2001)% U_J(2002) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
7989 %(2002)% U_J(2003) U_N(400) U_ALU_XOR U_A(0) U_LSRC_AQ U_SKIP_ADEQ0 U,
7990 %(2003)% U_J(2004) V_DP_0 U_MEM U_N(43012) U,
7991 %(2004)% U_J(2001) U_MEM U_N(2) U
7992 );
7993
7994 OK = 1;
7995 RPT_ERR_FLAG = 0;
7996
7997 LOADUC(TST_U_ADR,TST_U_1);
7998
7999 ERROR_LOOP(1)
8000 (
8001 WRT205(CLR_INT); ! RESET INTERRUPT-10 BIT
8002 SET_CRAM_ADR(TST_U_ADR);
8003 ACT_APR = STEP_U_NEXT(3);
8004 IF .ACT_APR EQL 0
8005 THEN
8006 (
8007 ERRCAS(1,1,%O'7760',SERIAL(36),12,ERRINFO); ! DIDN'T SKIP
8008 OK = 0;
8009 )
8010 ELSE
8011 (
8012 ACT_APR = RD_301;
8013 IF (.ACT_APR AND TEN_INT) EQL 0
8014 THEN
8015 (
8016 ERRCAS(1,2,(.ACT_APR OR TEN_INT),.ACT_APR,3,ERRINFO);
8017 OK = 0;
8018 );
8019 );
8020 EXIT_LOOP(1,1);
8021 0
8022 );
8023
8024 !*MESSAGE 1
8025 !*STIMULUS:
8026 !* KS10: LOAD APR FLAGS FROM DP WITH 7760
8027 !* READ APR FLAGS VIA DBM
8028 !*RESPONSE:
8029 !* APR FLAGS SHOULD BE SET
8030
8031 !*MESSAGE 2
8032 !*STIMULUS:
8033 !* 8080: CLEAR INTERRUPT-10 BIT IN REG 205
8034 !* KS10: LOAD APR FLAGS FROM DP WITH 7760
8035 !* 8080: EXAMINE INTERRUPT-10 APR FLAG
8036 !*RESPONSE:
8037 !* INTERRUPT-10 SHOULD BE SET
8038
8039 LOADUC(TST_U_ADR,TST_U_2);
8040
8041 ERROR_LOOP(2)
8042 (
8043 SET_CRAM_ADR(TST_U_ADR);
8044 ACT_APR = STEP_U_NEXT(3);
8045 IF .ACT_APR EQL 0
8046 THEN
8047 (
8048 ERRCAS(1,3,%O'7760',SERIAL(36),12,ERRINFO);
8049 OK = 0;
8050 );
8051 EXIT_LOOP(2,1);
8052 0
8053 );
8054
8055 !*MESSAGE 3
8056 !*STIMULUS:
8057 !* LOAD APR FLAGS FROM DP WITH 7760
8058 !* LOAD APR FROM PREVIOUS ???
8059 !* CHECK TO SEE IF THEY STAY SET
8060 !*RESPONSE:
8061 !* THEY SHOULD STAY SET
8062
8063 LOADUC(TST_U_ADR,TST_U_3_4);
8064
8065 ERROR_LOOP(3)
8066 (
8067 MR();
8068 SET_CRAM_ADR(TST_U_ADR + 1);
8069 ACT_APR = STEP_U_NEXT(2);
8070 IF .ACT_APR EQL 0
8071 THEN
8072 (
8073 ACT_APR = SERIAL(36) AND NOT %O'4000'; ! VERSION 1.2
8074 IF .ACT_APR NEQ 0 THEN
8075 (
8076 ERRCAS(1,4,0,.ACT_APR,12,ERRINFO);
8077 OK = 0;
8078 );
8079 );
8080 EXIT_LOOP(3,1);
8081 0
8082 );
8083
8084 !*MESSAGE 4
8085 !*STIMULUS:
8086 !* LOAD APR FLAGS FROM DP WITH 7760
8087 !* DO A MASTER RESET
8088 !*RESPONSE:
8089 !* APR FLAGS SHOULD BE CLEARED
8090
8091 ERROR_LOOP(4)
8092 (
8093 SET_CRAM_ADR(TST_U_ADR);
8094 ACT_APR = STEP_U_NEXT(3);
8095 IF .ACT_APR EQL 0
8096 THEN
8097 (
8098 ACT_APR = SERIAL(36) AND NOT %O'4000'; ! VERSION 1.2
8099 IF .ACT_APR NEQ 0 THEN
8100 (
8101 ERRCAS(1,5,0,.ACT_APR,12,ERRINFO);
8102 OK = 0;
8103 );
8104 );
8105 EXIT_LOOP(4,1);
8106 0
8107 );
8108
8109 !*MESSAGE 5
8110 !*STIMULUS:
8111 !* DO A MASTER RESET TO CLEAR THE APR FLAGS
8112 !* LOAD FROM PREVIOUS ???
8113 !*RESPONSE:
8114 !* APR FLAGS SHOULD STAY CLEAR
8115
8116 LOADUC(TST_U_ADR,TST_U_5);
8117
8118 ERROR_LOOP(5)
8119 (
8120 WRT205(CLR_INT); ! RESET INTERRUPT-10
8121 SET_CRAM_ADR(TST_U_ADR);
8122 ACT_APR = STEP_U_NEXT(3);
8123 IF .ACT_APR EQL 0
8124 THEN
8125 (
8126 ACT_APR = SERIAL(36) AND NOT %O'4000'; ! VERSION 1.2
8127 IF .ACT_APR NEQ 0 THEN
8128 (
8129 ERRCAS(1,6,0,.ACT_APR,12,ERRINFO);
8130 OK = 0;
8131 );
8132 )
8133 ELSE
8134 (
8135 ACT_APR = RD_301;
8136 IFN (.ACT_APR AND TEN_INT) ! CHECK INTERRUPT-10 BIT
8137 THEN
8138 (
8139 ERRCAS(5,7,(.ACT_APR XOR TEN_INT),.ACT_APR,3,ERRINFO);
8140 OK = 0;
8141 );
8142 );
8143 EXIT_LOOP(5,1);
8144 0
8145 );
8146
8147 !*MESSAGE 6
8148 !*STIMULUS:
8149 !* LOAD APR FLAGS FROM DP WITH 0
8150 !* READ APR FLAGS VIA DBM
8151 !*RESPONSE:
8152 !* APR FLAGS SHOULD BE CLEAR
8153
8154 !*MESSAGE 7
8155 !*STIMULUS:
8156 !* 8080: CLEAR INTERRUPT-10 BIT IN REG 205
8157 !* KS10: LOAD APR FLAGS FROM DP WITH 0
8158 !* 8080: EXAMINE INTERRUPT-10 APR FLAG
8159 !*RESPONSE:
8160 !* INTERRUPT-10 SHOULD BE CLEAR
8161
8162 LOADUC(TST_U_ADR,TST_U_6);
8163
8164 ERROR_LOOP(6)
8165 (
8166 DI(100000,222); ! GET MMC CORECTED DATA
8167 DM(0,0);
8168 EM(0);
8169 SET_CRAM_ADR(TST_U_ADR);
8170 ACT_APR = STEP_U_NEXT(3);
8171 IF .ACT_APR EQL 0
8172 THEN
8173 (
8174 ERRCAS(1,8,%O'100',SERIAL(36),12,ERRINFO);
8175 OK = 0;
8176 );
8177 EXIT_LOOP(6,1);
8178 0
8179 );
8180
8181 !*MESSAGE 8
8182 !*STIMULUS:
8183 !* 8080: SET MMC FORCE BITS TO GET CORRECTABLE ECC ERROR
8184 !* DEPOSIT 0 TO PHYSICAL MEM LOC 0
8185 !* KS10: READ PHYSICAL MEM LOC 0
8186 !* READ APR FLAGS
8187 !*RESPONSE:
8188 !* MMC CORRECTED DATA APR FLAG SHOULD BE ASSERTED
8189
8190 LOADUC(TST_U_ADR,TST_U_7);
8191
8192 ERROR_LOOP(7)
8193 (
8194 SET_CRAM_ADR(TST_U_ADR);
8195 ACT_APR = STEP_U_NEXT(5);
8196 IF .MAX_MEM_ADR GTR %O'3777777' ! BE SURE WE HAVE AN NXM LOC
8197 THEN
8198 OK = 0 ! WE DON'T, SO WE CAN'T BE OK
8199 ELSE
8200 IF .ACT_APR EQL 0
8201 THEN
8202 (
8203 ERRCAS(1,9,%O'400',SERIAL(36),12,ERRINFO);
8204 OK = 0;
8205 );
8206 EXIT_LOOP(7,1);
8207 0
8208 );
8209
8210 !*MESSAGE 9
8211 !*STIMULUS:
8212 !* LOAD VMA WITH -1 AND PERFORM A MEMORY READ
8213 !*RESPONSE:
8214 !* NXM APR FLAG SHOULD BE ASSERTED
8215
8216 SET_CRAM_ADR(TIU_MEMCLR);
8217 CP_NOSS(3); ! SINGLE STEP CLEARS MEMORY CYCLE
8218
8219 LOADUC(TST_U_ADR,TST_U_8);
8220
8221 ERROR_LOOP(8)
8222 (
8223 DI(100000,176);
8224 DM(0,0);
8225 SET_CRAM_ADR(TST_U_ADR);
8226 ACT_APR = STEP_U_NEXT(5);
8227 IF .ACT_APR EQL 0
8228 THEN
8229 (
8230 ERRCAS(1,10,%O'400',SERIAL(36),12,ERRINFO);
8231 OK = 0;
8232 );
8233 EXIT_LOOP(8,1);
8234 0
8235 );
8236
8237 !*MESSAGE 10
8238 !*STIMULUS:
8239 !* 8080: SET MMC FORCE BITS TO GET UNCORRECTABLE ECC ERROR
8240 !* DEPOSIT 0 TO PHYSICAL MEM LOC 0
8241 !* KS10: READ PHYSICAL MEM LOC 0
8242 !* READ APR FLAGS
8243 !*RESPONSE:
8244 !* MMC BAD DATA ERR APR FLAG SHOULD BE ASSERTED
8245
8246 IFN .OK THEN NOERR(1);
8247
8248 SET_CRAM_ADR(TIU_MEMCLR);
8249 CP_NOSS(5); ! CLEAR ALL INTERRUPTS
8250 RPT_ERR_FLAG = 1;
8251
8252 !]ERROR 1
8253 !]APR DBM_APR DBM_SEL_APR NTWK
8254
8255 !]NO ERROR 1
8256 !]APR DBM_APR DBM_SEL_APR NTWK
8257
8258 END;
8259
8260 GLOBAL ROUTINE TST55: NOVALUE =
8261
8262 !++
8263 ! FUNCTIONAL DESCRIPTION:
8264 !
8265 ! APR ENABLES
8266 !
8267 ! (ORIGINALLY WRITTEN BY JEAN BASMAJI)
8268 !
8269 !--
8270
8271 BEGIN
8272
8273 MACRO
8274 INFO_FLAGS = 0,0,36,0 %, ! # TO LOAD APR FLAGS
8275 INFO_FLAGS_F3 = 0,0,12,0 %,
8276 INFO_FLAGS_F4 = 0,12,6,0 %,
8277 INFO_ENABLES = 1,0,36,0 %, ! # TO LOAD APR ENABLES
8278 INFO_ENABLES_F3 = 1,0,12,0 %,
8279 INFO_ENABLES_F4 = 1,12,6,0 %,
8280 INFO_TICKS = 2,0,36,0 %, ! # CLOCK PULSES ???
8281 INFO_COR = 3,0,36,0 %; ! CORRECT ???
8282
8283 LOCAL
8284 OK,
8285 LOOPING;
8286
8287 OWN
8288 INFO: BLOCKVECTOR[11,4] INITIAL
8289 (
8290 %O'4000', %O'4000', 5, %O'10',
8291 %O'2000', %O'2000', 5, %O'10',
8292 %O'1000', %O'1000', 5, %O'10',
8293 %O'400', %O'400', 5, %O'10',
8294 %O'200', %O'200', 5, %O'10',
8295 %O'100', %O'100', 5, %O'10',
8296 %O'40', %O'40', 5, %O'10',
8297 %O'20', %O'20', 5, %O'10',
8298 %O'30010', %O'30010', 5, %O'10',
8299 0, %O'7760', 4, 0,
8300 %O'7760', 0, 4, 0
8301 );
8302
8303 LABEL
8304 LOOP1;
8305
8306 BIND
8307 TST_U_ADR = %O'2005',
8308 TST_U = PLIT
8309 (
8310 %(2005)% U_J(2006) V_DP_N(4000) U_SPEC_APRFLAGS U, ! #
8311 %(2006)% U_J(2007) V_DP_N(4000) U_SPEC_APR_EN U, ! #
8312 %(2007)% U_J(2010) V_DP_N(10) U_B(0) U_DEST_AD U, ! #
8313 %(2010)% U_J(2011) U_A(0) U_ALU_AND U_LSRC_DA U_DEST_Q_AD U_DBUS_DBM U_DBM_APR_FLAGS U,
8314 %(2011)% U_A(0) U_ALU_XOR U_LSRC_AQ U_SKIP_ADEQ0 U
8315 );
8316
8317 LOAD_TST_U;
8318 OK = 1;
8319 RPT_ERR_FLAG = 0;
8320
8321 INCR ERRN FROM 0 TO 10 DO
8322 (
8323 ERRINFO[0] = .INFO[.ERRN,INFO_FLAGS];
8324 ERRINFO[1] = .INFO[.ERRN,INFO_ENABLES];
8325
8326 IF .ERRN GTR 0
8327 THEN
8328 (
8329 MOD_FLD(3,.INFO[.ERRN,INFO_FLAGS_F3]);
8330 IF .INFO[.ERRN-1,INFO_FLAGS_F4] NEQ .INFO[.ERRN,INFO_FLAGS_F4]
8331 THEN
8332 MOD_FLD(4,.INFO[.ERRN,INFO_FLAGS_F4]);
8333
8334 SET_CRAM_ADR(TST_U_ADR + 1);
8335 MOD_FLD(3,.INFO[.ERRN,INFO_ENABLES_F3]);
8336 IF .INFO[.ERRN-1,INFO_ENABLES_F4] NEQ .INFO[.ERRN,INFO_ENABLES_F4]
8337 THEN
8338 MOD_FLD(4,.INFO[.ERRN,INFO_ENABLES_F4]);
8339
8340 IF .ERRN EQL 9
8341 THEN
8342 (
8343 LC(2007);
8344 MOD_FLD(4,3);
8345 )
8346 ELSE
8347 IF .ERRN EQL 10
8348 THEN
8349 (
8350 LC(2010);
8351 MOD_FLD(0,0);
8352 MOD_FLD(1,%O'6607');
8353 MOD_FLD(2,2);
8354 );
8355 );
8356
8357 LOOPING = 0;
8358 ERROR_LOOP(1)
8359 (
8360 SET_CRAM_ADR(TST_U_ADR);
8361 IF STEP_U_NEXT(.INFO[.ERRN,INFO_TICKS]) EQL 0
8362 THEN
8363 (
8364 ERRCAS(1,1,.INFO[.ERRN,INFO_COR],SERIAL(36),12,ERRINFO);
8365 OK = 0;
8366 );
8367 LOOPING = 1;
8368 EXIT_LOOP(1,1);
8369 0
8370 );
8371 );
8372 RPT_ERR_FLAG = 1;
8373
8374 IFN .OK THEN NOERR(1);
8375
8376 !*MESSAGE 1
8377 !*STIMULUS:
8378 !* LOAD APR FLAGS FROM DP WITH \O0
8379 !* LOAD APR ENABLES FROM DP WITH \O1
8380 !* READ APR FLAGS VIA DBM
8381 !* CHECK BITS 22 (TRAP), 23 (PAGE), 32 (IRQ)
8382 !*RESPONSE:
8383
8384 !]ERROR 1
8385 !]APR_EN DBM_APR_EN DBM_SEL_APR_EN APR NTWK
8386
8387 !]NO ERROR 1
8388 !]APR_EN DBM_APR_EN DBM_SEL_APR_EN NTWK
8389
8390 END;
8391
8392 GLOBAL ROUTINE TST56: NOVALUE =
8393
8394 !++
8395 ! FUNCTIONAL DESCRIPTION:
8396 !
8397 ! TEST PAGE TABLE DATA INPUTS/OUTPUTS PARITY CHECKING
8398 ! WRITE (& CHECK FOR DP PAR ERR) AT VMA 377777
8399 ! MAPPED TO PMA 777, 1777, 2777, 4777, ..., MAX_MEM_ADR
8400 ! (WITH WRITABLE AND WRITE-TEST ON)
8401 !
8402 !--
8403
8404 BEGIN
8405
8406 MACRO
8407 INFO_PTE = 0,0,36,0 %, ! PAGE TABLE ENTRY
8408 INFO_PTE_FLD3 = 0,0,12,0 %,
8409 INFO_PTE_FLD4 = 0,12,6,0 %,
8410 INFO_VMA = 1,0,36,0 %, ! VMA TO USE (FLD 3 SAME)
8411 INFO_VMA_FLD4 = 1,12,6,0 %,
8412 INFO_USER = 2,0,36,0 %; ! USER BIT FOR IT ALL
8413
8414 LOCAL
8415 ERRN,
8416 VMA,
8417 CURR_PAGE,
8418 COR_MEM_ADR,
8419 ACT_MEM_ADR,
8420 CRAM_ADR,
8421 OLD_PTE,
8422 OLD_VMA,
8423 OLD_USER,
8424 OK;
8425
8426 OWN
8427 INFO: BLOCKVECTOR[18,3] INITIAL
8428 (
8429 %O'440000', %O'377777', 0, ! LEFT PT RAM PARITY PINS
8430 %O'440001', %O'377777', 0, ! LEFT PT RAM PARITY PINS
8431 %O'460000', %O'777777', 0, ! CACHABLE
8432 %O'440000', %O'777777', 0, ! RIGHT PT RAM PARITY PINS
8433 %O'440001', %O'777777', 0, ! RIGHT PT RAM PARITY PINS
8434 %O'440002', %O'777777', 0,
8435 %O'440004', %O'777777', 0,
8436 %O'440010', %O'777777', 0,
8437 %O'440020', %O'777777', 0,
8438 %O'440040', %O'777777', 0,
8439 %O'440100', %O'777777', 0,
8440 %O'440200', %O'777777', 0,
8441 %O'440400', %O'777777', 0,
8442 %O'441000', %O'777777', 0,
8443 %O'442000', %O'777777', 0,
8444 %O'400000', %O'777777', 0, ! UNWRITABLE
8445 %O'440000', %O'777777', 1, ! USER
8446 %O'000000', %O'777777', 0 ! INVALID
8447 );
8448
8449 LABEL
8450 LOOP1;
8451
8452 BIND
8453 TST_U_ADR = %O'1050',
8454 TST_U = PLIT
8455 (
8456 %(1050)% U_J(1051) V_DP_N(377777) U_B_T0 U_DEST_AD U, ! #
8457 %(1051)% U_J(1052) V_DP_T0 U_MEM U_N(203010) U_SPEC_LDPAGE U, ! #
8458 %(1052)% U_J(1053) V_DP_N(440000) U, ! #
8459 %(1053)% U_J(1054) V_DP_T0 U_MEM U_N(242012) U, ! #
8460 %(1054)% V_DP_0 U_MEM U_N(2) U
8461 ),
8462 TUA_VMA = TST_U_ADR + 0, ! WHERE TO FIX VMA PAGE #
8463 TUA_LDPAG = TST_U_ADR + 1, ! WHERE TO FIX # TO LOAD PTE
8464 TUA_PAG = TST_U_ADR + 2, ! WHERE TO FIX PAGE TABLE ENTRY
8465 TUA_READ = TST_U_ADR + 3; ! WHERE TO FIX # TO DO READ
8466
8467 LOAD_TST_U;
8468
8469 PAGING_ON;
8470 OLD_PTE = .INFO[0,INFO_PTE];
8471 OLD_VMA = .INFO[0,INFO_VMA];
8472 OLD_USER = .INFO[0,INFO_USER];
8473 RPT_ERR_FLAG = 0;
8474 OK = 1;
8475
8476 INCR ERRN FROM 0 TO 17 DO
8477 IF .INFO[.ERRN,INFO_PTE_FLD3] LEQ (.MAX_MEM_ADR ^ (-9))
8478 THEN
8479 (
8480 ERRINFO[0] = .FORCE_NAME[.INFO[.ERRN,INFO_USER]];
8481 ERRINFO[1] = .INFO[.ERRN,INFO_PTE];
8482 ERRINFO[2] = VMA = .INFO[.ERRN,INFO_VMA];
8483 ERRINFO[3] = .VMA ^ (-9); ! PAGE NUMBER
8484
8485 IF .OLD_PTE NEQ .INFO[.ERRN,INFO_PTE]
8486 THEN
8487 (
8488 SET_CRAM_ADR(TUA_PAG);
8489 IF .OLD_PTE<N_FLD3> NEQ .INFO[.ERRN,INFO_PTE_FLD3]
8490 THEN
8491 MOD_FLD(3,.INFO[.ERRN,INFO_PTE_FLD3]);
8492 IF .OLD_PTE<N_FLD4> NEQ .INFO[.ERRN,INFO_PTE_FLD4]
8493 THEN
8494 MOD_FLD(4,.INFO[.ERRN,INFO_PTE_FLD4]);
8495 OLD_PTE = .INFO[.ERRN,INFO_PTE];
8496 );
8497
8498 IF .OLD_USER NEQ .INFO[.ERRN,INFO_USER]
8499 THEN
8500 (
8501 OLD_USER = .INFO[.ERRN,INFO_USER];
8502 SET_CRAM_ADR(TUA_LDPAG);
8503 MOD_FLD(4,.FORCE_MODE[.OLD_USER]);
8504 SET_CRAM_ADR(TUA_READ);
8505 MOD_FLD(4,(.FORCE_MODE[.OLD_USER] OR 4));
8506 );
8507
8508 IF .OLD_VMA NEQ .INFO[.ERRN,INFO_VMA]
8509 THEN
8510 (
8511 OLD_VMA = .INFO[.ERRN,INFO_VMA];
8512 SET_CRAM_ADR(TUA_VMA);
8513 MOD_FLD(4,.OLD_VMA<N_FLD4>);
8514 );
8515
8516 ERROR_LOOP(1)
8517 (
8518 SET_CRAM_ADR(TST_U_ADR);
8519 CP(5);
8520 IF (RD_303 AND 1) EQL 0 ! RAM PARITY ERROR?
8521 THEN
8522 (
8523 ERRS(1,1,ERRINFO);
8524 OK = 0;
8525 MR(); ! CLEAR THE FAULT
8526 );
8527
8528 EXIT_LOOP(1,1);
8529 0
8530 );
8531 );
8532
8533 IFN .OK THEN NOERR(1);
8534
8535 RPT_ERR_FLAG = 1;
8536 PAGING_OFF;
8537
8538 !*MESSAGE 1
8539 !*STIMULUS:
8540 !* KS10: LOAD \O1 INTO PAGE TABLE LOC \O3, \S0 MODE
8541 !* READ VIRTUAL MEM LOC \O2, \S0 MODE
8542 !* 8080: READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
8543 !*RESPONSE:
8544 !* SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
8545
8546 !]ERROR 1
8547 !]PT_PAR PT_PAR_GEN PAR_ERR BUS_T BUS_R BUS_PAR NTWK
8548
8549 !]NO ERROR 1
8550 !]PT_PAR PT_PAR_GEN NTWK
8551
8552 END;
8553
8554 GLOBAL ROUTINE TST57: NOVALUE =
8555
8556 !++
8557 ! FUNCTIONAL DESCRIPTION:
8558 !
8559 ! TEST PAGE TABLE RAM CONTENTS
8560 ! PAGE PARITY STUCK HIGH/LOW
8561 !
8562 !--
8563
8564 BEGIN
8565
8566 LOCAL
8567 VMA,
8568 PTE,
8569 TICKS,
8570 LOOPING,
8571 OK;
8572
8573 LABEL
8574 LOOP1;
8575
8576 BIND
8577 TST_U_ADR = %O'1060',
8578 TST_U = PLIT
8579 (
8580 %(1060)% U_J(1061) V_DP_N(440000) U_B(1) U_DEST_AD U, ! #
8581 %(1061)% U_J(1063) V_DP_N(777) U_B(0) U_DEST_AD U,
8582 %(1062)% U_J(1063) V_D_N(1000) U_A(0) U_B(0) U_ALU_ADD U_DEST_AD U_LSRC_0A U_RSRC_DA U,
8583 %(1063)% U_J(1064) V_DP_R(0) U_MEM U_N(3010) U_SPEC_LDPAGE U,
8584 %(1064)% U_J(1065) V_DP_R(1) U,
8585 %(1065)% U_J(1066) V_DP_R(0) U_MEM U_N(32012) U,
8586 %(1066)% V_DP_0 U_MEM U_N(2) U
8587 ),
8588 TUA_PAG = TST_U_ADR + 0, ! WHERE TO DIDDLE PAGE MAP
8589 TUA_VMA = TST_U_ADR + 2, ! WHERE TO INCREMENT VMA
8590 TUA_TST = TST_U_ADR + 3; ! WHERE TO RESTART TEST
8591
8592 IFN .INH_PT_RAM THEN RETURN; ! FORGET IT IF HE SAID TO
8593
8594 LOAD_TST_U;
8595 RPT_ERR_FLAG = 0;
8596 OK = 1;
8597 SET_CRAM_ADR(PHU_ADR);
8598 PAGING_ON;
8599
8600 INCR SUBTEST FROM 0 TO 1 DO ! CHECK FOR STUCK HIGH & LOW
8601 (
8602 SET_CRAM_ADR(TUA_PAG); ! WE START RUNNING HERE, TOO
8603 ERRINFO[2] = PTE = %O'440000' OR .SUBTEST;
8604 IFN .SUBTEST ! LOADED U-CODE MAPS TO PAGE 0
8605 THEN
8606 MOD_FLD(3,.PTE<N_FLD3>);
8607
8608 INCR VIR_PAG FROM 0 TO %O'777' DO ! DO THE WHOLE THING
8609 (
8610 ERRINFO[3] = .VIR_PAG;
8611 ERRINFO[0] = VMA = (.VIR_PAG ^ 9) OR %O'777';
8612 IFN .VIR_PAG
8613 THEN
8614 (
8615 SET_CRAM_ADR(TUA_VMA);
8616 TICKS = 7;
8617 )
8618 ELSE
8619 TICKS = 8;
8620 LOOPING = 0; ! FIRST TIME THROUGH ERROR LOOP
8621 ERROR_LOOP(1)
8622 (
8623 IFN .LOOPING THEN SET_CRAM_ADR(TUA_TST);
8624 CP(.TICKS);
8625 IF (RD_303 AND 1) EQL 0
8626 THEN
8627 (
8628 ERRS(1,1,ERRINFO);
8629 OK = 0;
8630 );
8631 ! GET READY TO DO IT OVER (IF ERROR OCCURED)
8632 LOOPING = 1;
8633 TICKS = 6;
8634 EXIT_LOOP(1,1);
8635 0
8636 );
8637 );
8638 );
8639
8640 IFN .OK THEN NOERR(1);
8641
8642 PAGING_OFF;
8643 RPT_ERR_FLAG = 1;
8644
8645 !*MESSAGE 1
8646 !*STIMULUS:
8647 !* KS10: LOAD \O2 INTO PAGE TABLE LOC \O3
8648 !* DEPOSIT 0 TO VIRTUAL MEM LOC \O0
8649 !* 8080: READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
8650 !*RESPONSE:
8651 !* SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
8652
8653 !]ERROR 1
8654 !]PT_RAM_PAR PT_PAR PT_PAR_GEN PAR_ERR BUS_T BUS_R BUS_PAR NTWK
8655
8656 !]NO ERROR 1
8657 !]PT_RAM_PAR PT_PAR PT_PAR_GEN NTWK
8658
8659 END;
8660
8661 GLOBAL ROUTINE TST58: NOVALUE =
8662
8663 !++
8664 ! FUNCTIONAL DESCRIPTION:
8665 !
8666 ! TEST CACHE DIRECTORY DATA INPUTS/OUTPUTS PARITY CHECKING
8667 ! WRITE AND READ AT VARIOUS VMA VALUES MAPPED TO PAGE 0
8668 !
8669 !--
8670
8671 BEGIN
8672
8673 MACRO
8674 INFO_USER = 0,0,36,0 %, ! USER BIT FOR IT ALL
8675 INFO_VMA = 1,0,36,0 %, ! VMA TO USE
8676 INFO_VMA_FLD3 = 1,0,12,0 %,
8677 INFO_VMA_FLD4 = 1,12,6,0 %;
8678
8679 LOCAL
8680 OK,
8681 VMA,
8682 PMA,
8683 CRAM_ADR,
8684 OLD_VMA,
8685 OLD_USER;
8686
8687 OWN
8688 INFO: BLOCKVECTOR[13,2] INITIAL
8689 (
8690 1, %O'000377',
8691 0, %O'000377',
8692 0, %O'000777',
8693 0, %O'001377',
8694 0, %O'001777',
8695 0, %O'002377',
8696 0, %O'004377',
8697 0, %O'010377',
8698 0, %O'020377',
8699 0, %O'040377',
8700 0, %O'100377',
8701 0, %O'200377',
8702 0, %O'400377'
8703 );
8704
8705 LABEL
8706 LOOP1;
8707
8708 BIND
8709 TST_U_ADR = %O'1070',
8710 TST_U = PLIT
8711 (
8712 %(1070)% U_J(1071) V_DP_N(000377) U_B_T0 U_DEST_AD U, ! #
8713 %(1071)% U_J(1072) V_DP_T0 U_MEM U_N(403010) U_SPEC_LDPAGE U, ! #
8714 %(1072)% U_J(1073) V_DP_N(460000) U,
8715 %(1073)% U_J(1074) V_DP_T0 U_MEM U_N(430012) U, ! #
8716 %(1074)% V_DP__1 U_MEM U_N(2) U,
8717 %(1075)% U_J(1076) V_DP_T0 U_MEM U_N(440012) U, ! #
8718 %(1076)% V_DP_D U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
8719 ),
8720 TUA_VMA = TST_U_ADR + 0, ! WHERE TO FIX VMA PAGE #
8721 TUA_LDPAG = TST_U_ADR + 1, ! WHERE TO FIX # TO LOAD PTE
8722 TUA_WRITE = TST_U_ADR + 3, ! WHERE TO FIX # TO DO WRITE
8723 TUA_READ = TST_U_ADR + 5; ! WHERE TO FIX # TO DO READ
8724
8725 LOAD_TST_U;
8726 OK = 1;
8727
8728 PAGING_ON;
8729 CE(1); ! TURN CACHE ON
8730 OLD_VMA = .INFO[0,INFO_VMA];
8731 OLD_USER = .INFO[0,INFO_USER];
8732 RPT_ERR_FLAG = 0;
8733 INCR ERRN FROM 0 TO 12 DO
8734 (
8735 ERRINFO[0] = .FORCE_NAME[.INFO[.ERRN,INFO_USER]];
8736 ERRINFO[2] = VMA = .INFO[.ERRN,INFO_VMA];
8737 ERRINFO[1] = PMA = .VMA<0,9>; ! MAPPED TO PAGE 0
8738 ERRINFO[3] = .VMA<9,9>; ! PAGE NUMBER
8739
8740 IF .OLD_USER NEQ .INFO[.ERRN,INFO_USER]
8741 THEN
8742 (
8743 OLD_USER = .INFO[.ERRN,INFO_USER];
8744 SET_CRAM_ADR(TUA_LDPAG);
8745 MOD_FLD(4,.FORCE_MODE[.OLD_USER]);
8746 SET_CRAM_ADR(TUA_WRITE);
8747 MOD_FLD(4,(.FORCE_MODE[.OLD_USER] OR 3));
8748 SET_CRAM_ADR(TUA_READ);
8749 MOD_FLD(4,(.FORCE_MODE[.OLD_USER] OR 4));
8750 );
8751
8752 IF .OLD_VMA NEQ .INFO[.ERRN,INFO_VMA]
8753 THEN
8754 (
8755 SET_CRAM_ADR(TUA_VMA);
8756 IF .OLD_VMA<N_FLD3> NEQ .INFO[.ERRN,INFO_VMA_FLD3]
8757 THEN
8758 MOD_FLD(3,.INFO[.ERRN,INFO_VMA_FLD3]);
8759 IF .OLD_VMA<N_FLD4> NEQ .INFO[.ERRN,INFO_VMA_FLD4]
8760 THEN
8761 MOD_FLD(4,.INFO[.ERRN,INFO_VMA_FLD4]);
8762 OLD_VMA = .INFO[.ERRN,INFO_VMA];
8763 );
8764
8765 ERROR_LOOP(1)
8766 (
8767 SET_CRAM_ADR(TST_U_ADR);
8768 CP(6); ! WRITE -1 TO MEM; EXTRA TICK?
8769 MEM_DEPOSIT(.PMA,0); ! DIDDLE MEM BUT NOT CACHE
8770 SET_CRAM_ADR(TUA_READ);
8771 CRAM_ADR = STEP_U_NEXT(2);
8772 IF (RD_303 AND 1) EQL 0 ! RAM PARITY ERROR?
8773 THEN
8774 (
8775 ERRS(1,1,ERRINFO);
8776 MR(); ! CLEAR FAULT
8777 OK = 0;
8778 )
8779 ELSE
8780 IFN .CRAM_ADR ! FAULT: MISS: READ 0: ALU=0: SKIP: ADR=1
8781 THEN
8782 (
8783 ERRS(1,2,ERRINFO);
8784 MR(); ! CLEAR FAULT
8785 OK = 0;
8786 );
8787
8788 EXIT_LOOP(1,1);
8789 0
8790 );
8791 );
8792
8793 IFN .OK THEN NOERR(1);
8794
8795 RPT_ERR_FLAG = 1;
8796 PAGING_OFF;
8797 CE(0); ! TURN CACHE OFF
8798
8799 !*MESSAGE 1
8800 !*STIMULUS:
8801 !* KS10: LOAD 460000 INTO PAGE TABLE LOC \O3, \S0 MODE
8802 !* WRITE, THEN READ VIRTUAL MEM LOC \O2, \S0 MODE
8803 !* 8080: READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
8804 !*RESPONSE:
8805 !* SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
8806
8807 !*MESSAGE 2
8808 !*STIMULUS:
8809 !* KS10: LOAD 460000 INTO PAGE TABLE LOC \O3, \S0 MODE
8810 !* WRITE -1 TO VIRTUAL MEM LOC \O2, \S0 MODE
8811 !* 8080: WRITE 0 TO PHYSICAL MEM LOC \O1
8812 !* KS10: READ VIRTUAL MEM LOC \O2, \S0 MODE
8813 !*RESPONSE:
8814 !* SHOULD GET 0 (CACHE HIT); DIDN'T (CACHE DIR PAR ERR?)
8815
8816 !]ERROR 1
8817 !]CD_PAR PAR_ERR N_ALL PT_IO PT_CAC CD_IO CD_CMP CD_HIT PT_MESS NTWK
8818
8819 !]NO ERROR 1
8820 !]CD_PAR NTWK
8821
8822 END;
8823
8824 GLOBAL ROUTINE TST59: NOVALUE =
8825
8826 !++
8827 ! FUNCTIONAL DESCRIPTION:
8828 !
8829 ! TEST CACHE DIRECTORY RAM CONTENTS PARITY BIT TEST
8830 !
8831 !--
8832
8833 BEGIN
8834
8835 MACRO
8836 INFO_USER = 0,0,36,0 %, ! USER BIT FOR IT ALL
8837 INFO_VMA = 1,0,36,0 %, ! VMA TO USE
8838 INFO_VMA_FLD3 = 1,0,12,0 %,
8839 INFO_VMA_FLD4 = 1,12,6,0 %;
8840
8841 LOCAL
8842 VMA,
8843 PMA,
8844 CRAM_ADR,
8845 OLD_VMA,
8846 LOOPING;
8847
8848 LABEL
8849 LOOP1;
8850
8851 BIND
8852 TST_U_ADR = %O'1100',
8853 TST_U = PLIT
8854 (
8855 %(1100)% U_J(1101) V_DP_N(002000) U_B_T0 U_DEST_AD U, ! #
8856 %(1101)% U_J(1102) V_DP_T0 U_MEM U_N(3010) U_SPEC_LDPAGE U,
8857 %(1102)% U_J(1103) V_DP_N(460001) U,
8858 %(1103)% U_J(1104) V_DP_T0 U_MEM U_N(30012) U,
8859 %(1104)% V_DP__1 U_MEM U_N(2) U,
8860 %(1105)% U_J(1106) V_DP_T0 U_MEM U_N(40012) U,
8861 %(1106)% V_DP_D U_DBM_MEM U_DBUS_DBM U_SKIP_ADEQ0 U_MEM U_N(2) U
8862 ),
8863 TUA_VMA = TST_U_ADR + 0, ! WHERE TO FIX VMA PAGE #
8864 TUA_READ = TST_U_ADR + 5; ! WHERE TO START READ
8865
8866 IFN .INH_CD_RAM THEN RETURN; ! FORGET IT IF HE SAID TO
8867
8868 LOAD_TST_U;
8869
8870 PAGING_ON;
8871 CE(1); ! TURN CACHE ON
8872 OLD_VMA = %O'2000';
8873 RPT_ERR_FLAG = 0;
8874
8875 INCR ERRN FROM 0 TO %O'1777' DO ! EACH LOC, 2 PAGES (HIGH, LOW)
8876 (
8877 ERRINFO[2] = VMA = %O'2000' OR .ERRN;
8878 ERRINFO[1] = PMA = .VMA<0,9> OR %O'1000'; ! MAP TO PAGE 1
8879 ERRINFO[3] = .VMA<9,9>; ! PAGE NUMBER
8880
8881 IF .OLD_VMA NEQ .VMA
8882 THEN
8883 (
8884 SET_CRAM_ADR(TUA_VMA);
8885 IF .OLD_VMA<N_FLD3> NEQ .VMA<N_FLD3> THEN MOD_FLD(3,.VMA<N_FLD3>);
8886 IF .OLD_VMA<N_FLD4> NEQ .VMA<N_FLD4> THEN MOD_FLD(4,.VMA<N_FLD4>);
8887 OLD_VMA = .VMA
8888 );
8889
8890 LOOPING = 0;
8891 ERROR_LOOP(1)
8892 (
8893 IFN .LOOPING THEN SET_CRAM_ADR(TST_U_ADR);
8894 CP(6); ! WRITE -1 TO MEM; EXTRA TICK?
8895 MEM_DEPOSIT(.PMA,0); ! DIDDLE MEM BUT NOT CACHE
8896 SET_CRAM_ADR(TUA_READ);
8897 CRAM_ADR = STEP_U_NEXT(2);
8898 IF (RD_303 AND 1) EQL 0 ! RAM PARITY ERROR?
8899 THEN
8900 (
8901 ERRS(1,1,ERRINFO);
8902 MR(); ! CLEAR FAULT
8903 )
8904 ELSE
8905 IFN .CRAM_ADR ! FAULT: MISS: READ 0: ALU=0: SKIP: ADR=1
8906 THEN
8907 (
8908 ERRS(1,2,ERRINFO);
8909 MR(); ! CLEAR FAULT
8910 )
8911 ELSE
8912 NOERR(1);
8913 LOOPING = 1;
8914 EXIT_LOOP(1,1);
8915 0
8916 );
8917 );
8918
8919 RPT_ERR_FLAG = 1;
8920 PAGING_OFF;
8921 CE(0); ! TURN CACHE OFF
8922
8923 !*MESSAGE 1
8924 !*STIMULUS:
8925 !* KS10: LOAD 460001 INTO PAGE TABLE LOC \O3
8926 !* WRITE, THEN READ VIRTUAL MEM LOC \O2
8927 !* 8080: READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
8928 !*RESPONSE:
8929 !* SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
8930
8931 !*MESSAGE 2
8932 !*STIMULUS:
8933 !* KS10: LOAD 460001 INTO PAGE TABLE LOC \O3
8934 !* WRITE -1 TO VIRTUAL MEM LOC \O2
8935 !* 8080: WRITE 0 TO PHYSICAL MEM LOC \O1
8936 !* KS10: READ VIRTUAL MEM LOC \O2
8937 !*RESPONSE:
8938 !* SHOULD GET 0 (CACHE HIT); DIDN'T (CACHE DIR PAR ERR?)
8939
8940 !]ERROR 1
8941 !]CD_RAM_PAR CD_PAR PAR_ERR N_ALL PT_IO PT_CAC CD_IO CD_CMP CD_HIT PT_MESS NTWK
8942
8943 !]NO ERROR 1
8944 !]CD_RAM_PAR NTWK
8945
8946 END;
8947
8948 GLOBAL ROUTINE TST60: NOVALUE =
8949
8950 !++
8951 ! FUNCTIONAL DESCRIPTION:
8952 !
8953 ! TEST PREVIOUS EXECUTE (PXCT) REGISTER & MUX
8954 !
8955 !--
8956
8957 BEGIN
8958
8959 MACRO
8960 INFO_PXCT = 0,0,36,0 %,
8961 INFO_PXCT_BITS = 0,0,1,0 %,
8962 INFO_PXCT_ON = 0,1,1,0 %,
8963 INFO_PXCT_FLD3 = 1,0,36,0 %,
8964 INFO_PXCT_SEL = 1,6,3,0 %,
8965 INFO_VMA_PREV = 2,0,36,0 %;
8966
8967 LOCAL
8968 OK,
8969 OLD_PXCT,
8970 VMA_PREV,
8971 LOOPING;
8972
8973 OWN
8974 INFO: BLOCKVECTOR[17,3] INITIAL
8975 (
8976 0, %O'3010', 0,
8977 0, %O'3110', 0,
8978 0, %O'3210', 0,
8979 0, %O'3310', 0,
8980 0, %O'3410', 0,
8981 0, %O'3510', 0,
8982 0, %O'3610', 0,
8983 0, %O'3710', 0,
8984 1, %O'3010', 0,
8985 1, %O'3110', 1,
8986 1, %O'3210', 1,
8987 1, %O'3310', 1,
8988 1, %O'3410', 1,
8989 1, %O'3510', 1,
8990 1, %O'3610', 1,
8991 1, %O'3710', 1,
8992 2, %O'3710', 0
8993 );
8994
8995 LABEL
8996 LOOP1;
8997
8998 BIND
8999 TST_U_ADR = %O'1120',
9000 TST_U = PLIT
9001 (
9002 %(1120)% V_DP_0 U_SPEC_LDPXCT U,
9003 %(1121)% V_DP__1 U_SPEC_LDPXCT U,
9004 %(1122)% V_DP__1 U_SPEC_PXCT_OFF U,
9005 %(1123)% U_J(1124) U_MEM U_N(3010) U, ! #<9:11>
9006 %(1124)% U_DBM_VMA U_DBUS_DBM V_DP_D U_DEST_Q_AD U
9007 ),
9008 TUA_INIT = TST_U_ADR + 0, ! LOAD REGISTER
9009 TUA_NEXT = TST_U_ADR + 3; ! DO NEXT SELECT
9010
9011 LOAD_TST_U;
9012 OK = 1;
9013
9014 RPT_ERR_FLAG = 0;
9015 INCR ERRN FROM 0 TO 16 DO
9016 (
9017 LOOPING = 0;
9018 IF (.ERRN EQL 0) OR (.INFO[.ERRN,INFO_PXCT] NEQ .OLD_PXCT)
9019 THEN
9020 (
9021 SET_CRAM_ADR(TUA_INIT + .INFO[.ERRN,INFO_PXCT]);
9022 CP(2);
9023 );
9024 OLD_PXCT = .INFO[.ERRN,INFO_PXCT];
9025 SET_CRAM_ADR(TUA_NEXT);
9026 IFN .ERRN THEN MOD_FLD(3,.INFO[.ERRN,INFO_PXCT_FLD3]);
9027 ERROR_LOOP(1)
9028 (
9029 IFN .LOOPING THEN SET_CRAM_ADR(TUA_NEXT);
9030 VMA_PREV = STEP_U_NEXT(14); ! (CP(2); SERIAL(9,1))
9031 IF .VMA_PREV NEQ .INFO[.ERRN,INFO_VMA_PREV]
9032 THEN
9033 (
9034 ERRINFO[0] = .INFO[.ERRN,INFO_PXCT_BITS];
9035 ERRINFO[1] = .INFO[.ERRN,INFO_PXCT_SEL];
9036 ERRINFO[2] = .INFO[.ERRN,INFO_VMA_PREV];
9037 ERRINFO[3] = .VMA_PREV;
9038 ERRINFO[4] = .INFO[.ERRN,INFO_PXCT_ON];
9039 ERRS(1,1,ERRINFO);
9040 OK = 0;
9041 );
9042 LOOPING = 1;
9043 EXIT_LOOP(1,1);
9044 0
9045 );
9046 );
9047
9048 IFN .OK THEN NOERR(1);
9049
9050 RPT_ERR_FLAG = 1;
9051
9052 !*MESSAGE 1
9053 !*STIMULUS:
9054 !* SET ALL PXCT BITS TO \O0, PXCT ON = \O4
9055 !* LOAD VMA, PXCT SEL #<9:11> = \O1
9056 !*RESPONSE:
9057 !* VMA PREV SHOULD BE \O2 BUT IT WAS \O3
9058
9059 !]ERROR 1
9060 !]PXCT PXCT_MUX DBM_VMA DBM_SEL_VMA SPEC_PXCT_EN SPEC_PXCT_OFF NTWK
9061
9062 !]NO ERROR 1
9063 !]PXCT PXCT_MUX DBM_VMA DBM_SEL_VMA SPEC_PXCT_EN SPEC_PXCT_OFF NTWK
9064
9065 END;
9066
9067 GLOBAL ROUTINE TST61: NOVALUE =
9068
9069 !++
9070 ! FUNCTIONAL DESCRIPTION:
9071 !
9072 ! TEST PREVIOUS EXECUTE (PXCT) MUX OUTPUT TO DPE BOARD
9073 !
9074 !--
9075
9076 BEGIN
9077
9078 LOCAL
9079 OK,
9080 CRAM_ADR;
9081
9082 LABEL
9083 LOOP1;
9084
9085 BIND
9086 TST_U_ADR = %O'1130',
9087 TST_U = PLIT
9088 (
9089 %(1130)% U_J(1131) V_DP_NN(100) U_SPEC_LDACBLK U, ! CUR=0, PREV=1
9090 %(1131)% U_J(1132) V_DP_0 U_DBUS_DP U_FMWRITE U_RAM_N U_N(0) U,
9091 %(1132)% V_DP__1 U_DBUS_DP U_FMWRITE U_RAM_N U_N(20) U,
9092 %(1133)% U_J(1135) V_DP__1 U_SPEC_LDPXCT U,
9093 %(1134)% U_J(1135) V_DP_0 U_SPEC_PXCT_OFF U,
9094 %(1135)% U_J(1136) V_DP_0 U_DBUS_DP U_SPEC_LOADXR U_N(700) U,
9095 %(1135)% U_RAM_XR U_DBUS_RAM V_DP_D U_SKIP_ADEQ0 U
9096 ),
9097 TUA_INIT = TST_U_ADR + 0, ! LOAD AC BLK & AC
9098 TUA_TEST = TST_U_ADR + 3; ! DO THE TESTS
9099
9100 LOAD_TST_U;
9101 OK = 1;
9102
9103 SET_CRAM_ADR(TUA_INIT);
9104 CP(4);
9105 INCR ERRN FROM 0 TO 1 DO
9106 ERROR_LOOP(1)
9107 (
9108 SET_CRAM_ADR(TUA_TEST + .ERRN);
9109 CRAM_ADR = STEP_U_NEXT(3);
9110 IF .CRAM_ADR NEQ .ERRN
9111 THEN
9112 (
9113 ERRINFO[0] = (NOT .ERRN) AND 1;
9114 ERRINFO[1] = - .ERRN;
9115 ERRS(1,1,ERRINFO);
9116 OK = 0;
9117 );
9118 EXIT_LOOP(1,1);
9119 0
9120 );
9121
9122 IFN .OK THEN NOERR(1);
9123
9124 !*MESSAGE 1
9125 !*STIMULUS:
9126 !* SET CURRENT AC BLOCK TO 0; PREVIOUS AC BLOCK TO 1
9127 !* SET AC0 BLOCK 0 TO 0; AC0 BLOCK 1 TO -1
9128 !* SET XR PREVIOUS TO \O0 AND READ XR0
9129 !*RESPONSE:
9130 !* SHOULD GET \O1 (BUT DIDN'T)
9131
9132 !]ERROR 1
9133 !]PXCT PXCT_MUX_DPE SPEC_PXCT_EN SPEC_PXCT_OFF NTWK
9134
9135 !]NO ERROR 1
9136 !]PXCT PXCT_MUX_DPE SPEC_PXCT_EN SPEC_PXCT_OFF NTWK
9137
9138 END;
9139
9140 GLOBAL ROUTINE TST62: NOVALUE =
9141
9142 !++
9143 ! FUNCTIONAL DESCRIPTION:
9144 !
9145 ! SC SIGN TEST
9146 !
9147 ! (ORIGINALLY WRITTEN BY RICH MURATORI)
9148 !
9149 !--
9150
9151 BEGIN
9152
9153 LOCAL
9154 ACTUAL,
9155 OK;
9156
9157 LABEL
9158 LOOP1,
9159 LOOP2;
9160
9161 BIND
9162 TST_U_ADR = %O'3000',
9163 TST_U = PLIT
9164 (
9165 %(3000)% U_J(3002) U_LOADSC U_SCADA_SN U_SN(0) U_SCAD_A U,
9166 %(3001)% U_J(3002) U_LOADSC U_SCADA_SN U_SN(1000) U_SCAD_A U,
9167 %(3002)% U_SKIP_SC U
9168 ),
9169 TUA_0 = TST_U_ADR + 0, ! CLEAR THE BIT
9170 TUA_1 = TST_U_ADR + 1; ! SET THE BIT
9171
9172 LOAD_TST_U;
9173 OK = 1;
9174
9175 ERROR_LOOP(1)
9176 (
9177
9178 SET_CRAM_ADR(TUA_1); ! WE WILL SET THE SC SIGN BIT
9179 ACTUAL = STEP_U_NEXT(2); ! EXECUTE SC SIGN BIT SKIP
9180 IF .ACTUAL EQL 0 ! DID WE TAKE SKIP?
9181 THEN
9182 (
9183 ERRCAS(1,1,1,.ACTUAL,4,ERRINFO); ! NO, REPORT ERROR
9184 OK = 0;
9185 );
9186 EXIT_LOOP(1,1);
9187 0
9188 );
9189
9190 !*MESSAGE 1
9191 !*STIMULUS:
9192 !* SET 'DPM SC SIGN'; JUMP TO 0 AND SKIP ON SC SIGN
9193 !*RESPONSE:
9194 !* NEXT CRAM ADDRESS SHOULD BE 1 (BUT IT WASN'T)
9195
9196 ERROR_LOOP(2)
9197 (
9198
9199 SET_CRAM_ADR(TUA_0); ! WE WILL CLEAR THE SC SIGN BIT
9200 ACTUAL = STEP_U_NEXT(2); ! EXECUTE SC SIGN BIT SKIP
9201 IFN .ACTUAL ! DID WE TAKE SKIP?
9202 THEN
9203 (
9204 ERRCAS(1,2,0,.ACTUAL,4,ERRINFO); ! YES, REPORT ERROR
9205 OK = 0;
9206 );
9207 EXIT_LOOP(2,1);
9208 0
9209 );
9210
9211 IFN .OK THEN NOERR(1);
9212
9213 !*MESSAGE 2
9214 !*STIMULUS:
9215 !* CLEAR 'DPM SC SIGN'; JUMP TO 0 AND SKIP ON SC SIGN
9216 !*RESPONSE:
9217 !* NEXT CRAM ADDRESS SHOULD BE 0 (BUT IT WASN'T)
9218
9219 !]ERROR 1
9220 !]SCAD_A SC_EN SC_SIGN SCADA_SN SCADA_SEL_SN NTWK
9221
9222 !]NO ERROR 1
9223 !]SCAD_A SC_EN SC_SIGN SCADA_SN SCADA_SEL_SN NTWK
9224
9225 END;
9226
9227 GLOBAL ROUTINE TST63: NOVALUE =
9228
9229 !++
9230 ! FUNCTIONAL DESCRIPTION:
9231 !
9232 ! THIS TEST CHECKS THAT THE FAST SHIFTING CONTROL LOGIC FUNCTIONS
9233 ! CORRECTLY. SPECIFICALLY, THAT 'CRA/M CLK ENABLE' NEGATES AND 'DPE/M
9234 ! CLK ENABLE' ASSERTS WHEN 'CRM2 MULTI SHIFT' AND 'FE SIGN' ARE ASSERTED.
9235 !
9236 ! THIS TEST CHECKS THAT THE FAST SHIFTING CONTROL LOGIC FUNCTIONS
9237 ! CORRECTLY. SPECIFICALLY, THAT 'DPE/M CLK ENABLE' NEGATES AND 'CRA/M
9238 ! CLK ENABLE' ASSERTS WHEN 'CRM2 MULTI SHIFT' IS ASSERTED AND 'FE SIGN'
9239 !
9240 ! (ORIGINALLY WRITTEN BY RICH MURATORI)
9241 !
9242 !--
9243
9244 BEGIN
9245
9246 MACRO
9247 INFO_TUA = 0,0,36,0 %,
9248 INFO_TICKS = 1,0,36,0 %,
9249 INFO_SN = 2,0,36,0 %,
9250 INFO_CR = 3,0,36,0 %,
9251 INFO_CR_MSG = 4,0,36,0 %,
9252 INFO_DP = 5,0,36,0 %,
9253 INFO_DP_MSG = 6,0,36,0 %;
9254
9255 LOCAL
9256 OK,
9257 TEMP;
9258
9259 LABEL
9260 LOOP1;
9261
9262 BIND
9263 TST_U_ADR = %O'3010',
9264 TST_U = PLIT
9265 (
9266 %(3010)% U_J(3012) U_T(0) U_LOADFE U_SCAD_A U_SCADA_SN U_SN(1000) U,
9267 %(3011)% U_J(3012) U_T(0) U_LOADFE U_SCAD_A U_SCADA_SN U_SN(0) U,
9268 %(3012)% U_T(0) U_MULTI_SHIFT U
9269 ),
9270 TUA_0 = TST_U_ADR + 0,
9271 TUA_1 = TST_U_ADR + 1;
9272
9273 OWN
9274 INFO: BLOCKVECTOR[2,7] INITIAL
9275 (
9276 TUA_0, 16, %O'1000', 0, 1, 0, 2,
9277 TUA_1, 9, %O'0000', CR_CLK_ENB, 3, DP_CLK_ENBL, 4
9278 );
9279
9280 LOAD_TST_U;
9281 OK = 1;
9282
9283 INCR SUBTEST FROM 0 TO 1 DO
9284 ERROR_LOOP(1)
9285 (
9286 MR();
9287 SET_CRAM_ADR(.INFO[.SUBTEST,INFO_TUA]);
9288 SYNC_CLK(); ! STOP CLOCK AND SYNC IT
9289 WRT206(SINGLE_CLK); ! ASSERT 'SINGLE CLK'
9290 CYCLE(4); ! EXECUTE 1ST MICRO-INSTR
9291 WRT206(SINGLE_CLK); ! ASSERT 'SINGLE CLK'
9292 TICK(.INFO[.SUBTEST,INFO_TICKS]); ! EXECUTE 2ND MICRO-INSTR
9293 TEMP = RD_303; ! READ STATES OF CLOCK ENABLES
9294
9295 ! CRA M CLK ENABLE
9296 IF (.TEMP AND CR_CLK_ENB) NEQ .INFO[.SUBTEST,INFO_CR]
9297 THEN
9298 (
9299 ERRS(1,.INFO[.SUBTEST,INFO_CR_MSG],ERRINFO);
9300 OK = 0;
9301 );
9302
9303 EXIT_LOOP(1,1);
9304
9305 ! DPE M CLK ENABLE
9306 IF (.TEMP AND DP_CLK_ENBL) NEQ .INFO[.SUBTEST,INFO_DP]
9307 THEN
9308 (
9309 ERRS(1,.INFO[.SUBTEST,INFO_DP_MSG],ERRINFO);
9310 OK = 0;
9311 );
9312
9313 EXIT_LOOP(1,1);
9314
9315 0
9316 );
9317
9318 IFN .OK THEN NOERR(1);
9319
9320 MR();
9321
9322 !*MESSAGE 1
9323 !*STIMULUS:
9324 !* ASSERT AND NEGATE 'RESET'
9325 !* STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
9326 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9327 !* GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
9328 !* THIS LOADS 'FE SIGN' WITH A 1.
9329 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9330 !* GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
9331 !* THIS ASSERTS 'MULTI SHIFT'.'MULTI SHIFT' AND
9332 !* 'FE SIGN' SHOULD ASSERT 'FS (1)'. THIS WILL
9333 !* HOLD 'ENABLE (1)' ASSERTED AND CAUSE 'CRA/M
9334 !* CLK ENABLE' TO NEGATE WHILE 'DPE/M CLK ENABLE'
9335 !* IS ASSERTED.
9336 !*RESPONSE:
9337 !* 'CRA/M CLK ENABLE' DIDN'T NEGATE.
9338
9339 !*MESSAGE 2
9340 !*STIMULUS:
9341 !* ASSERT AND NEGATE 'RESET'
9342 !* STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
9343 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9344 !* GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
9345 !* THIS LOADS 'FE SIGN' WITH A 1.
9346 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9347 !* GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
9348 !* THIS ASSERTS 'MULTI SHIFT'.'MULTI SHIFT' AND
9349 !* 'FE SIGN' SHOULD ASSERT 'FS (1)'. THIS WILL
9350 !* HOLD 'ENABLE (1)' ASSERTED AND CAUSE 'CRA/M
9351 !* CLK ENABLE' TO NEGATE WHILE 'DPE/M CLK ENABLE'
9352 !* IS ASSERTED.
9353 !*RESPONSE:
9354 !* 'DPE/M CLK ENABLE' DIDN'T STAY ASSERTED.
9355
9356 !*MESSAGE 3
9357 !*STIMULUS:
9358 !* ASSERT AND NEGATE 'RESET'
9359 !* STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
9360 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9361 !* GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
9362 !* THIS LOADS 'FE SIGN' WITH A 0.
9363 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9364 !* GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
9365 !* THIS ASSERTS 'MULTI SHIFT'. WITH 'FE SIGN'
9366 !* NEGATED, 'CRA/M CLK ENABLE' SHOULD ASSERT AND
9367 !* 'DPE/M CLK ENABLE' SHOULD NEGATE.
9368 !*RESPONSE:
9369 !* 'CRA/M CLK ENABLE' DIDN'T ASSERT.
9370
9371 !*MESSAGE 4
9372 !*STIMULUS:
9373 !* ASSERT AND NEGATE 'RESET'
9374 !* STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
9375 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9376 !* GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
9377 !* THIS LOADS 'FE SIGN' WITH A 0.
9378 !* WRT 206/2 - ASSERT 'SINGLE CLK'
9379 !* GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
9380 !* THIS ASSERTS 'MULTI SHIFT'. WITH 'FE SIGN'
9381 !* NEGATED, 'CRA/M CLK ENABLE' SHOULD ASSERT AND
9382 !* 'DPE/M CLK ENABLE' SHOULD NEGATE.
9383 !*RESPONSE:
9384 !* 'DPE/M CLK ENABLE' DIDN'T NEGATE.
9385
9386 !]ERROR 1
9387 !]FE_SIGN FE_EN SCAD_A_DEC SCADA_SN SCADA_SEL_SN NTWK
9388
9389 !]NO ERROR 1
9390 !]FE_SIGN FE_EN NTWK
9391
9392 END;
9393
9394 GLOBAL ROUTINE TST64: NOVALUE =
9395
9396 !++
9397 ! FUNCTIONAL DISCREPTION:
9398 !
9399 ! MSEC COUNTER OUTPUT PINS
9400 !
9401 ! (ORIGINALLY WRITTEN BY JEAN BASMAJI)
9402 !
9403 !--
9404
9405 BEGIN
9406
9407 LOCAL
9408 OK,
9409 RCVDATA;
9410
9411 LABEL
9412 LOOP1,
9413 LOOP2;
9414
9415 BIND
9416 TST_U_ADR = %O'2020',
9417 TST_U = PLIT
9418 (
9419 %(2020)% U_J(2020) U_ALU_AND U_LSRC_DQ U_DEST_Q_AD U_DBUS_DBM U_DBM_MSEC U_SKIP_ADEQ0 U,
9420 %(2021)% U_J(2021) U,
9421 %(2022)% U_J(2020) V_DP_N(7774) U_DEST_Q_AD U
9422 );
9423
9424 LOAD_TST_U;
9425 RPT_ERR_FLAG = 0;
9426 OK = 1;
9427
9428 ERRINFO[0] = UPLIT(%ASCIZ'HIGH');
9429 ERROR_LOOP(1)
9430 (
9431 SET_CRAM_ADR(TST_U_ADR + 2);
9432 CS(); ! START THE CLOCK
9433 WAIT(1000); ! WAIT FOR AT LEAST 1 MILLISECOND
9434 CH(); ! STOP THE CLOCK
9435 IF EX_NXT NEQ (TST_U_ADR + 1) ! DID WE SKIP
9436 THEN
9437 (
9438 SET_CRAM_ADR(0);
9439 ERRCAS(1,1,0,SERIAL(36),12,ERRINFO); ! NO
9440 OK = 0;
9441 );
9442 EXIT_LOOP(1,1);
9443 0
9444 );
9445
9446 SET_CRAM_ADR(TST_U_ADR);
9447 MOD_FLD(5,%O'5662'); ! MODIFY ALU TO 5
9448 ERRINFO[0] = UPLIT(%ASCIZ'LOW');
9449 ERROR_LOOP(2)
9450 (
9451 SET_CRAM_ADR(TST_U_ADR + 2);
9452 CS(); ! START THE CLOCK
9453 WAIT(1000); ! WAIT AT LEAST 1 MILLISECOND
9454 CH(); ! STOP THE CLOCK
9455 IF EX_NXT NEQ (TST_U_ADR + 1) ! DID WE SKIP?
9456 THEN
9457 (
9458 SET_CRAM_ADR(0); ! SET FOR SERIAL
9459 RCVDATA = SERIAL(36) XOR %O'7774';
9460 ERRCAS(1,1,%O'7774',.RCVDATA,12,ERRINFO); ! NO
9461 OK = 0;
9462 );
9463 EXIT_LOOP(2,1);
9464 0
9465 );
9466
9467 IFN .OK THEN NOERR(1);
9468 RPT_ERR_FLAG = 1;
9469
9470 !*MESSAGE 1
9471 !*STIMULUS:
9472 !* CHECK OUTPUT PINS OF MILLISECOND COUNTER FOR STUCK \S0
9473 !*RESPONSE:
9474 !* GET THE MILLISECOND COUNTER OUTPUT THROUGH DBM BITS 24:33
9475
9476 !]ERROR 1
9477 !]MSEC DBM_MSEC NTWK
9478
9479 !]NO ERROR 1
9480 !]MSEC DBM_MSEC NTWK
9481
9482 END;
9483
9484 GLOBAL ROUTINE TST65: NOVALUE =
9485
9486 !++
9487 ! FUNCTIONAL DISCREPTION:
9488 !
9489 ! MILISECOND COUNTER TIMING
9490 !
9491 ! (ORIGINALLY WRITTEN BY JEAN BASMAJI)
9492 !
9493 !--
9494
9495 BEGIN
9496
9497 LOCAL
9498 RCVDATA;
9499
9500 LABEL
9501 LOOP1;
9502
9503 BIND
9504 TST_U_ADR = %O'2030',
9505 TST_U = PLIT
9506 (
9507 %(2030)% U_J(2030) U_ALU_AND U_LSRC_DA U_DBUS_DBM U_DBM_MSEC U_SKIP_ADEQ0 U_LOADFE U_N(510000) U,
9508 %(2031)% U_J(2032) U_LOADFE U_N(510000) U,
9509 %(2032)% U_J(2032) U_ALU_AND U_LSRC_DA U_DBUS_DBM U_DBM_MSEC U_SKIP_ADEQ0 U_LOADFE U_N(410001) U,
9510 %(2033)% U_J(2033) U_ALU_OR U_LSRC_D0 U_DEST_Q_AD U_DBUS_DBM U_DBM_SCAD U_N(110000) U,
9511 %(2034)% U_J(2030) V_DP_N(3774) U_DEST_AD U
9512 );
9513
9514 LOAD_TST_U;
9515 ERROR_LOOP(1)
9516 (
9517 SET_CRAM_ADR(TST_U_ADR + 4);
9518 CS(); ! START THE CLOCK
9519 WAIT(1000); ! WAIT AT LEAST 1 MILLISECOND
9520 CH(); ! STOP THE CLOCK
9521 SET_CRAM_ADR(0); ! SET UP FOR SERIAL
9522 RCVDATA = SCAD_Q(); ! GET THE SCAD
9523 IF ((.RCVDATA GEQ 660) AND (.RCVDATA LEQ 672)) ! WITHIN 1%?
9524 THEN
9525 NOERR(1)
9526 ELSE
9527 ERR(1);
9528 EXIT_LOOP(1,1);
9529 0
9530 );
9531
9532 !*MESSAGE 1
9533 !*STIMULUS:
9534 !* CHECK MILLISECOND COUNTER TIMING
9535 !*RESPONSE:
9536 !* THE MILLISECOND COUNTER IS OFF BY MORE THAN 1%
9537
9538 !]ERROR 1
9539 !]MSEC_FREQ DBM_MSEC NTWK
9540
9541 !]NO ERROR 1
9542 !]MSEC_FREQ DBM_MSEC NTWK
9543
9544 END;
9545
9546 END
9547 ELUDOM
AC0 886+# 890+# 894+# 898+# 902+# 906+# 910+# 914+# 918+# 922+# 926+# 930+#
934+# 938+# 942+# 946+# 950+# 954+# 958+# 962+# 966+# 970+# 974+# 1021+#
1471# 1513#
ACT 1900 1935# 1938 1939 1995 2032# 2035 2036 2092 2129# 2132 2133
2189 2221# 2222 2227 2228 2284 2316# 2317 2320 2362 2392# 2393
2396 2438 2470# 2471 2476 2477 2534 2570# 2571 2576 2577 2633
2676# 2677 2684 2687 2690 2794 2830# 2831 2838 2839 2895 2928#
2929 2935 2936 2992 3025# 3026 3032 3033 3092 3131# 3132 3136
3179 3215# 3218 3219 3270 3319# 3322 3323 3375 3411# 3412 3419
3420 3613 3659# 3660 3661 3663 3669 3843 3887# 3888 3889 3891
3897 4147 4188# 4191 4234 4269# 4270 4274 4476 4511# 4513 4517
4518 4520 4590 4626# 4628 4632 4633 4635 4707 4740# 4742 4746
4747 4749
ACTUAL 9154 9179# 9180 9183 9200# 9201 9204
ACT_APR 7933 8003# 8004 8012# 8013 8016 8044# 8045 8069# 8070 8073# 8074
8076 8094# 8095 8098# 8099 8101 8122# 8123 8126# 8127 8129 8135#
8136 8139 8170# 8171 8195# 8200 8226# 8227
ACT_BYTE 2635 2694# 2695
ACT_MEM_ADR 5020 5091# 5093 5096 8419
ACT_PF_CAUSE 5343 5412# 5414 5417 5617 5673# 5674 5675 5678 5736 5768# 5769
5778 5844 5882# 5883 5888 5892 5898# 5899 5900 5904 5910# 5911
5912 5915 5922# 5923 5924 5928 6009 6047# 6048 6056 6060 6066#
6067 6068 6072 6078# 6079 6080 6084 6090# 6091 6092 6096 6180
6217# 6218 6219 6222 6237# 6238 6239 6242 6254# 6255 6256 6259
6271# 6272 6273 6276 6330 6359# 6360 6362 6364 6366 6433
ACT_PMA 5171 5263# 5265 5268 7030 7138# 7139
ACT_PREV 5487 5566# 5568
ACT_PTR 2637 2677# 2682 2690# 2694
ACT_USER 5488 5567# 5568
ADDR 717+ 718+ 719+ 720+ 897+ 898+
ADPT1_PE 1276+#
ADPT2_PE 1237+#
ADPT3_PE 1242+#
ADPT4_PE 1275+#
ALL_DIF 3612 3652# 3662# 3687 3692 3842 3880# 3890# 3908 3913 4477 4504#
4518# 4530 4591 4619# 4633# 4645 4708 4733# 4747# 4759
ALL_PAGE_BITS 6572 6602
BAD_DATA 1141+#
BEGIN_XLIST 715+#
BITNO 6596 6602
BITVAL 6597 6602
BLISS36 4
BOOT 1292+#
BUSREQ 1295+#
BUS_REQ 1180+#
BYTE_NUMBER 2678 2680 2691 2695
CACHE_ENB 1079+#
CE 773+ 1631 6492 6532 6594 6622 6694 6741 6799 6812 6874 6899
6957 6982 7370 7436 7453 7530 7578 7594 7678 7739 8729 8797
8871 8921
CEREAL_VAL 1868 1871# 1873 1874
CH 775+ 9434 9454 9520
CHK_ERR_MSG 758+
CLK_RUN 1169+#
CLOSE_LATCH 1174+#
CLR_INT 1163+# 8001 8120
COM_ADR 1140+#
COM_ADR_ERR 7785 7815# 7825# 7834
CONS_ENB 1293+#
CONTINUE 1185+#
CONTINUE_H 1280+#
CONTROL 744+*
COR 1899 1934# 1938 1939 1994 2031# 2035 2036 2091 2128# 2132 2133
2188 2220# 2222 2227 2228 2283 2313# 2317 2320 2361 2389# 2393
2396 2437 2469# 2471 2476 2477 2533 2569# 2571 2576 2577 2632
2675# 2684 2687 2689 2793 2829# 2831 2838 2839 2894 2927# 2929
2935 2936 2991 3024# 3026 3032 3033 3091 3128# 3132 3136 3178
3214# 3218 3219 3269 3318# 3322 3323 3374 3410# 3412 3419 3420
3614 3660# 3661 3663 3669 3844 3888# 3889 3891 3897 4146 4182#
4183 4189 4190 4191 4233 4265# 4266 4270 4273 4274 4475 4512#
4513 4517 4518 4520 4589 4627# 4628 4632 4633 4635 4706 4741#
4742 4746 4747 4749
COR_BYTE 2634 2693# 2695
COR_CRAM_ADR 6435 6489# 6490 6520
COR_MEM_ADR 5019 5057# 5093 5096 8418
COR_PF_CAUSE 5342 5381# 5414 5417 5616 5657# 5665 5675 5678 5735 5757# 5758
5778 5843 5880# 5881 5888 5892 5900 5904 5908# 5909 5912 5915
5924 5928 6008 6045# 6046 6056 6060 6068 6072 6076# 6077 6080
6084 6092 6096 6179 6215# 6216 6219 6222 6235# 6236 6239 6242
6256 6259 6273 6276 6329 6357# 6358 6362 6364 6366 7203 7252#
7273
COR_PMA 5170 5234# 5265 5268 7029 7083# 7095 7096 7098 7102 7139
COR_PREV 5489 5556# 5568
COR_PTR 2636 2689# 2693
COR_USER 5490 5557# 5568
CP 714+ 763+ 2219 2315 2391 2468 2566 2681 2828 2926 3023 3130
3409 3530 3532 3534 3658 3793 3886 3994 4082 4268 4332 4341
4412 4421 4510 4625 4739 4867 4871 4939 4948 4970 5069 5071
5223 5392 5549 5564 5582 5648 5653 5763 5873 5897 5921 6034
6065 6089 6213 6233 6253 6270 6513 6609 6703 6881 6965 7395
7538 7708 7820 8519 8624 8768 8894 9022 9104
CP_NOSS 764+ 1351 1353 1643 1733 1827 7282 8217 8249
CRAM_ADDR 711+
CRAM_ADR 5021 5072# 5073 5737 5766# 5770 5845 5879# 5884 6010 6044# 6049
6181 6331 6356# 6361 6434 6519# 6520 6568 6613# 6614 6844 6884#
6885 6932 6968# 6969 7032 7125# 7126 7135 7206 7271# 7273 7334
7428# 7429 7440 7497 7570# 7571 7582 7640 7710# 7711 7721 7725
7787 7860# 8420 8683 8771# 8780 8844 8897# 8905 9080 9109# 9110
CRAM_ADR_LD 1153+#
CRAM_PE 1241+#
CRAM_RESET 1149+#
CRAM_WRT 1154+#
CRA_PE 1238+#
CRA_R_CLK 1176+#
CRA_T_CLK 1177+#
CRM_PE_DET 1081+#
CR_CLK_ENB 1310+# 9277 9296
CR_LF 882+# 886+ 914+
CS 774+ 9432 9452 9518
CSL_EXECUTE 5485 5555# 5562
CSL_INT 1145+#
CTY_BIT 1287+#
CTY_CHAR_LEN 1286+#
CURR_PAGE 5017 5052# 5054 5057 5058 5060 5105# 8417
CYCLE 1327# 9290
DAT 7026 7082# 7083 7084 7790 7837# 7843 7844#
DATA 717+ 719+
DATA0 1134+#
DATA1 1133+#
DATA10 1121+#
DATA11 1120+#
DATA12 1116+#
DATA13 1115+#
DATA14 1114+#
DATA15 1113+#
DATA16 1112+#
DATA17 1111+#
DATA18 1110+#
DATA19 1109+#
DATA2 1132+#
DATA20 1105+#
DATA21 1104+#
DATA22 1103+#
DATA23 1102+#
DATA24 1101+#
DATA25 1100+#
DATA26 1099+#
DATA27 1098+#
DATA28 1094+#
DATA29 1093+#
DATA3 1131+#
DATA30 1092+#
DATA31 1091+#
DATA32 1090+#
DATA33 1089+#
DATA34 1088+#
DATA35 1087+#
DATA4 1127+#
DATA5 1126+#
DATA6 1125+#
DATA7 1124+#
DATA8 1123+#
DATA9 1122+#
DATA_ACK 1291+#
DATA_CYCLE 1138+#
DC_035 782+
DEST 296+ 297+
DI 719+# 4080 5067 5243 6037 8166 8223
DIAG1 1158+#
DIAG10 1161+#
DIAG2 1159+#
DIAG4 1160+#
DIF 3611 3661# 3662 3671 3841 3889# 3890 3899
DM 717+# 5761 6040 6107 6711 6715 6882 7398 7402 7541 7545 7709
8167 8224
DM_CHK 784+
DN 788+ 6713 6717 7400 7404 7543 7547
DP 309+ 310+ 330+ 331+
DP_CLK_ENBL 1309+# 9277 9306
DP_PE_DET 1080+#
DP_PE 1239+#
DP_RESET 1151+#
EB_AC 872+# 996+
EC 780+
EC_AC 873+# 997+
EI 720+# 4088 5091 5263 7138
EI_AC 869+# 993+
EI_CHK 791+
EJ 778+
EJ_AC 870+# 994+
EK_AC 871+# 995+
EM 718+# 5767 8168
EM_AC 874+# 998+
EM_CHK 787+
END_LIST 716+#
EN_1MS 1078+#
EOP_UUO 988+#
ERMCAS 752+ 2687 3669 3897 4517 4632 4746
ERMCA 751+
ERMS 753+
ERR 746+ 6805 9527
ERRCAS 748+ 1936 2033 2130 2225 2320 2396 2474 2574 2836 2933 3030
3136 3216 3320 3417 3553 3777 3798 4091 4191 4274 4348 4428
4880 4954 4963 5096 5268 5417 5678 5892 5904 5915 5928 6060
6072 6084 6096 6222 6242 6259 6276 6362 6366 6732 7139 8007
8016 8048 8076 8101 8129 8139 8174 8203 8230 8364 9183 9204
9439 9460
ERRCA 747+ 3998 4026
ERRFLG 820+
ERRINFO 1386 1934# 1939 2031# 2036 2128# 2133 2220# 2228 2312# 2313# 2320
2388# 2389# 2396 2469# 2477 2567# 2568# 2569# 2577 2674# 2675# 2687
2829# 2834# 2835# 2839 2927# 2932# 2936 3024# 3029# 3033 3128# 3135#
3136 3214# 3219 3316# 3317# 3318# 3323 3410# 3415# 3416# 3420 3539#
3541# 3543# 3544# 3553 3666# 3667# 3668# 3669 3798 3894# 3895# 3896#
3897 4085 4091 4189# 4190# 4191 4273# 4274 4346# 4347# 4348 4426#
4427# 4428 4516# 4517 4631# 4632 4745# 4746 4876# 4877# 4878# 4879#
4880 4945# 4954 4963 5057# 5058# 5063# 5064# 5076# 5077# 5078 5085
5096 5234# 5235# 5236# 5237# 5249# 5250# 5251 5258 5268 5380# 5381#
5382# 5401# 5402# 5412# 5413# 5417 5423 5555# 5556# 5557# 5558# 5559#
5560# 5561# 5566# 5567# 5571 5645# 5646# 5651# 5656# 5657# 5665# 5673#
5674# 5678 5684 5757# 5758# 5767# 5768# 5769# 5772 5776 5780 5880#
5881# 5882# 5883# 5886 5892 5898# 5899# 5904 5908# 5909# 5910# 5911#
5915 5922# 5923# 5928 6045# 6046# 6047# 6048# 6052 6060 6066# 6067#
6072 6076# 6077# 6078# 6079# 6084 6090# 6091# 6096 6214# 6215# 6216#
6217# 6218# 6222 6234# 6235# 6236# 6237# 6238# 6242 6254# 6255# 6259
6271# 6272# 6276 6357# 6358# 6359# 6360# 6362 6366 6485# 6486# 6487#
6488# 6490# 6523 6600# 6603# 6604# 6616 6731# 6732 6888# 6889# 6890
6972# 6973 7083# 7084# 7086# 7111# 7112# 7129# 7130# 7131 7139 7248#
7252# 7253# 7257# 7271# 7272# 7276 7374# 7376# 7415# 7416# 7432# 7433#
7434 7442 7558# 7574# 7575# 7576 7584 7684# 7687# 7695# 7696# 7714#
7715# 7716 7724# 7725# 7726 7826# 7827# 7828 7843# 7865# 7866# 7867
8007 8016 8048 8076 8101 8129 8139 8174 8203 8230 8323# 8324#
8364 8480# 8481# 8482# 8483# 8523 8603# 8610# 8611# 8628 8735# 8736#
8737# 8738# 8775 8783 8877# 8878# 8879# 8901 8908 9034# 9035# 9036#
9037# 9038# 9039 9113# 9114# 9115 9183 9204 9299 9309 9428# 9439
9448# 9460
ERRM 750+
ERRN 1348 1349 3526 3529 3531 3533 3536 3540 3542 3543 3546 3553
3555 3670 3671 3673 3675 3676 3691 3692 3694 3898 3899 3901
3903 3904 3912 3913 3915 4519 4520 4522 4524 4525 4529 4530
4634 4635 4637 4639 4640 4644 4645 4748 4749 4751 4753 4754
4758 4759 4860 4863 4866 4870 4873 4876 4877 4878 4879 4880
5214 5216 5217 5232 5234 5235 5236 5237 6482 6485 6486 6487
6489 6492 6494 6501 6502 6506 6508 6511 6512 6517 6518 6698
6700 6720 6722 7372 7374 7375 7376 7379 7382 7385 7840 7876
8321 8323 8324 8326 8329 8330 8332 8335 8336 8338 8340 8347
8361 8364 8415 8476 8477 8480 8481 8482 8485 8489 8491 8492
8494 8495 8498 8501 8508 8511 8733 8735 8736 8740 8743 8752
8756 8758 8759 8761 8762 8875 8877 9015 9018 9021 9024 9026
9031 9034 9035 9036 9038 9105 9108 9110 9113 9114
ERROR_LOOP 1346# 1928 2025 2122 2216 2310 2386 2465 2563 2672 2825 2923
3020 3126 3208 3310 3406 3527 3655 3771 3790 3883 3990 4020
4078 4180 4263 4334 4414 4507 4622 4736 4861 4943 5065 5241
5405 5553 5666 5759 5874 6035 6210 6230 6250 6267 6353 6483
6598 6725 6800 6877 6961 7122 7268 7418 7560 7698 7817 7847
7999 8041 8065 8091 8118 8164 8192 8221 8358 8516 8621 8765
8891 9027 9106 9175 9196 9284 9429 9449 9515
ER_AC 868+# 992+
EXAMINE_COUNT 1789 1828
EXECUTE_B 1281+#
EXIT_LOOP 1348# 1943 1944 2040 2041 2137 2138 2232 2233 2323 2399 2481
2482 2581 2582 2698 2843 2844 2940 2941 3037 3038 3139 3223
3327 3424 3425 3555 3676 3780 3801 3904 4001 4029 4096 4194
4277 4354 4434 4525 4640 4754 4883 4957 4966 5100 5272 5426
5575 5688 5784 5933 6101 6225 6245 6262 6279 6369 6526 6619
6736 6808 6893 6976 7144 7287 7446 7588 7731 7831 7876 8020
8051 8080 8105 8143 8177 8206 8233 8368 8528 8634 8788 8914
9043 9118 9186 9207 9303 9313 9442 9463 9528
EXNEXT 721+ 767+
EXP_VAL 3750 3794# 3795 3798
EX_NXT 714+ 721+# 9435 9455
FAILURE 755+ 2695 3673 3901 4522 4637 4751
FILNAM_ADR 1021+
FIRSTONE 1394 1434
FLP_CHK 757+
FORCE_MODE 1382 7088 7090 7092 7379 7382 7385 8503 8505 8745 8747 8749
FORCE_NAME 1384 7086 7376 8480 8735
FORCE_PAR 1077+#
FRDPAG 1023+#
FSELECT 1021+#
FUNC 256+ 257+
HALTED 1028+#
HALT_LOOP 1283+#
HIT_MSG 6439 6490
I 2702
IFN 1322# 1349 1515 1519 1948 2045 2142 2237 2327 2403 2486 2586
2702 2848 2945 3042 3143 3227 3331 3429 3559 3560 3561 3671
3805 3899 4083 4089 4198 4281 4358 4438 4863 4887 4974 5082
5109 5255 5277 5434 5579 5695 5774 5937 6105 6283 6494 6530
6614 6897 6980 7071 7113 7124 7150 7236 7259 7270 7293 7364
7420 7524 7562 7673 7737 7822 7834 7862 7881 8136 8246 8374
8533 8592 8604 8612 8623 8640 8780 8793 8866 8893 8905 9026
9029 9048 9122 9201 9211 9318 9467
INFO 1918 1930 1931 1934 2015 2027 2028 2031 2112 2124 2125 2128
2206 2218 2219 2220 2299 2312 2313 2376 2388 2389 2455 2467
2469 2553 2565 2567 2568 2569 2662 2674 2675 2680 2814 2827
2829 2834 2835 2913 2925 2927 2932 3010 3022 3024 3029 3114
3128 3129 3130 3135 3198 3210 3211 3214 3300 3312 3316 3317
3318 3395 3408 3410 3415 3416 3505 3529 3531 3533 3536 3540
3542 3543 3553 3636 3657 3660 3666 3667 3668 3873 3885 3888
3894 3895 3896 4170 4182 4184 4185 4253 4265 4267 4496 4509
4512 4516 4611 4624 4627 4631 4726 4738 4741 4745 4848 4863
4866 4870 4873 4876 4877 4878 4879 4880 5175 5216 5235 5237
5494 5555 5556 5557 5558 5559 5560 5561 6444 6485 6486 6487
6489 6492 6494 6501 6502 6506 6508 6511 6512 6517 6518 6661
6700 6722 6848 6880 6888 6889 6935 6964 6966 6972 7211 7248
7250 7252 7646 7684 8288 8323 8324 8329 8330 8332 8335 8336
8338 8361 8364 8427 8470 8471 8472 8477 8480 8481 8482 8485
8489 8491 8492 8494 8495 8498 8501 8508 8511 8688 8730 8731
8735 8736 8740 8743 8752 8756 8758 8759 8761 8762 8974 9018
9021 9024 9026 9031 9034 9035 9036 9038 9274 9287 9292 9296
9299 9306 9309
INFO_A 2789# 2835 3370# 3416 3471# 3529 3540
INFO_B 3472# 3531 3542
INFO_CE 6418# 6492
INFO_COND 4820# 4878
INFO_COR 1895# 1934 1990# 2031 2087# 2128 2184# 2220 2279# 2313 2357# 2388
2389 2433# 2469 2527# 2569 2628# 2675 2787# 2829 2889# 2927 2986#
3024 3086# 3128 3174# 3214 3263# 3318 3368# 3410 3605# 3666 4143#
4182 4229# 4265 4471# 4512 4585# 4627 4702# 4741 8281# 8364
INFO_CORR 3473# 3536 3543 3553 4821# 4873 4879 4880
INFO_COR_ADR 6417# 6489
INFO_COR_PREV 5476# 5556
INFO_COR_USER 5477# 5557
INFO_CP 1894# 1931 1989# 2028 2086# 2125 2183# 2219 3085# 3130 3173# 3211
INFO_CR 9250# 9296
INFO_CR_MSG 9251# 9299
INFO_DBM028 3835# 3896
INFO_DESCR 6428# 6485
INFO_DP 2528# 2567 2627# 2674 2890# 2932 2987# 3029 3087# 3135 3264# 3316
3606# 3667 3836# 3895 9252# 9306
INFO_DP_MSG 9253# 9309
INFO_ENABLES 8277# 8324
INFO_ENABLES_F3 8278# 8335
INFO_ENABLES_F4 8279# 8336 8338
INFO_EXECUTE 5478# 5555
INFO_FE 2788# 2834 3369# 3415
INFO_FLAGS_F3 8275# 8329
INFO_FLAGS_F4 8276# 8330 8332
INFO_FLAGS 8274# 8323
INFO_FUNC 3470# 3533
INFO_INI_ADR 4816# 4863 4866
INFO_MEM 4819# 4877
INFO_N 2278# 2312 2356# 3607# 3668 3837# 3894 4818# 4876 5482# 5560
INFO_NAM 4472# 4516 4586# 4631
INFO_N_PAG_FLD3 6424# 6501
INFO_N_PAG_FLD4 6425# 6502
INFO_N_PMA 6421# 6486
INFO_N_REF_FLD3 6426# 6517
INFO_N_REF_FLD4 6427# 6506 6508 6518
INFO_N_VMA_FLD3 6422# 6511
INFO_N_VMA_FLD4 6423# 6512
INFO_N_VMA 6420# 6487
INFO_OPCODE 4703# 4745
INFO_PAGING 6419# 6494
INFO_PCU 5480# 5559
INFO_PF_CAUSE 7200# 7252
INFO_PTE 7198# 7248 8407# 8470 8481 8485 8495
INFO_PTE_FLD3 8408# 8477 8489 8491
INFO_PTE_FLD4 7199# 7250 8409# 8492 8494
INFO_PXCT 8960# 9018 9021 9024
INFO_PXCT_BITS 8961# 9034
INFO_PXCT_FLD3 8963# 9026
INFO_PXCT_ON 8962# 9038
INFO_PXCT_SEL 8964# 9035
INFO_SC 2529# 2568
INFO_SCAD 3265# 3317
INFO_SN 9249#
INFO_SPEC 5481# 5561
INFO_TICKS 4142# 4185 8280# 8361 9248# 9292
INFO_TST_ADR 4817# 4870
INFO_TUA 1893# 1930 1988# 2027 2085# 2124 2182# 2218 2432# 2467 2526# 2565
2626# 2680 2786# 2827 2888# 2925 2985# 3022 3084# 3129 3172# 3210
3262# 3312 3367# 3408 3604# 3657 3834# 3885 4141# 4184 4228# 4267
4470# 4509 4584# 4624 4701# 4738 9247# 9287
INFO_USER 5479# 5558 8412# 8472 8480 8498 8501 8674# 8731 8735 8740 8743
8836#
INFO_VALU 3838# 3888
INFO_VALUE 3608# 3660
INFO_VMA 8410# 8471 8482 8508 8511 8675# 8730 8736 8752 8762 8837#
INFO_VMA_FLD3 8676# 8756 8758 8838#
INFO_VMA_FLD4 8411# 8677# 8759 8761 8839#
INFO_VMA_PREV 8965# 9031 9036
INH_CD_RAM 1380 1474# 1515 1523 7364 7524 8866
INH_PT_RAM 1381 1477# 1519 1523 7071 7236 7673 8592
IO_DATA 1139+#
IO_DEPOSIT 719+ 789+
IO_EXAMINE 720+ 790+
KLINIK_BIT 1285+#
KLINIK_CARR 1301+#
KLINIK_LEN 1284+#
K_MEM 1377 1431# 1432
LANGUAGE 4
LATCH_DATA 1175+#
LC 712+# 8343 8350
LCA 712+ 781+
LOADUC 711+ 770+ 1326 1638 1639 1640 1641 7997 8039 8063 8116 8162
8190 8219
LOAD_TST_U 1326# 1925 2022 2119 2213 2306 2382 2462 2560 2669 2822 2920
3017 3123 3205 3307 3403 3521 3651 3768 3879 3989 4076 4176
4259 4329 4409 4503 4618 4732 4857 4936 5044 5207 5372 5547
5640 5756 5868 6029 6207 6350 6479 6592 6691 6796 6871 6955
7073 7238 7366 7526 7675 7813 8317 8467 8594 8725 8868 9011
9100 9172 9280 9424 9514
LOAD_U 711+#
LOC 4312 4337# 4338 4340 4342 4346 4352# 4392 4417# 4418 4420 4422
4426 4432# 4919 4940# 4942 4945 4947 4951 4954 4959 4968#
LOC_0_VAL 3969 3995# 3996 3998
LOOP 1347 1349
LOOP1 1903 1998 2095 2192 2287 2365 2441 2537 2640 2797 2898 2995
3095 3182 3273 3378 3476 3617 3754 3847 3972 4064 4151 4237
4317 4397 4480 4594 4711 4824 4923 5024 5189 5356 5510 5621
5741 5850 6014 6185 6334 6460 6576 6675 6778 6851 6938 7038
7218 7342 7502 7653 7794 7936 8304 8450 8574 8706 8849 8996
9083 9158 9260 9412 9501
LOOP2 1904 1999 2096 2193 2899 2996 3618 3755 3848 3973 4152 4238
6186 7795 7937 9159 9413
LOOP3 6187 7938
LOOP4 6188 7939
LOOP5 7940
LOOP6 7941
LOOP7 7942
LOOP8 7943
LOOPING 7033 7121# 7124 7142# 7207 7267# 7270 7285# 7336 7417# 7420 7445#
7499 7559# 7562 7587# 7641 7697# 7700 7730# 7791 7842# 7849 7875#
8285 8357# 8367# 8570 8620# 8623 8632# 8846 8890# 8893 8913# 8971
9017# 9029 9042#
LOOPN 1346 1347 1348 1349
LOOP_CHK 756+ 1349
LPONTST 817+
MAINT_CLK 1165+#
MAX_MEM_ADR 1378 1432# 1433 4338 4418 4942 5054 5864 8196 8477
MAX_PAG 1379 1433# 1434# 7082
MEM 1181+#
MEMSIZE 745+ 1431
MEM_ADR 4061 4088# 4089 4091
MEM_DEPOSIT 717+ 785+ 1637 3992 4022 4183 4266 4336 4340 4350 4416 4420
4430 4869 4946 4947 6514 6610 6966 8769 8895
MEM_EXAMINE 718+ 786+ 3995 4269 4342 4347 4422 4427 4872 4950 4959
MEM_PE 1240+#
MEM_REF_ERR 1029+#
MEM_VAL 5738 5767# 5774 5846
MMC_REF_ERR 1247+#
MNT_CLK_ENB 1164+#
MOD_FLD 783+ 5046 5048 5060 5212 5219 5221 5222 5230 5239 5240 5379
5388 5389 5391 5397 5404 6501 6502 6506 6508 6511 6512 6517
6518 6607 6608 6696 6702 6708 6724 6880 6964 7088 7090 7092
7095 7096 7103 7107 7243 7250 7297 7379 7382 7385 7388 7391
7392 7393 7408 7411 7533 7536 7551 7554 7689 8329 8332 8335
8338 8344 8351 8352 8353 8491 8494 8503 8505 8513 8606 8745
8747 8749 8758 8761 8885 8886 9026 9447
MR 771+ 1628 1731 4095 5087 5092 5259 5264 5574 7280 7829 7868
8067 8525 8776 8784 8902 8909 9286 9320
MSDPMT 3#
MSGADR 893+ 894+ 917+ 918+
MSGFIL 1360#
MSGWORD 889+ 890+
MSG_CHK_UUO 1013+#
N 714+ 1327 1340 1341 1342 1343
NEXM 1296+#
NEXT_PAGE 5018 5053# 5105 5106#
NOERR 754+ 1951 1952 2048 2049 2145 2146 2240 2241 2327 2403 2489
2490 2589 2590 2702 2851 2852 2948 2949 3045 3046 3143 3227
3331 3432 3433 3559 3560 3561 3689 3694 3805 3910 3915 4000
4028 4093 4198 4281 4358 4438 4530 4645 4759 4887 4974 5109
5277 5434 5579 5695 5782 5937 6105 6283 6368 6530 6618 6735
6807 6897 6980 7150 7293 7444 7586 7737 7881 8246 8374 8533
8640 8793 8912 9048 9122 9211 9318 9467 9525
NO_SUBSET 816+
NUM 909+ 910+ 929+ 930+ 933+ 934+ 937+ 938+ 941+ 942+ 945+ 946+
949+ 950+ 953+ 954+ 957+ 958+ 961+ 962+ 965+ 966+ 969+ 970+
973+ 974+
NXT_DAT 7789 7838# 7844 7845#
N_FLD3 1323# 5219 5221 5239 5388 6607 6702 6724 7095 7107 7392 8489
8606 8756 8885
N_FLD4 1324# 5222 5240 5389 5391 5404 6608 7096 7393 7689 8492 8513
8759 8886
O1776 1369# 2303 2379 3510 3517
O1777 1368# 2209 2301 2303 2379 2458 2556 2817 2818 2916 3303 3397
3398 3399 3508 3509 3513 3515 3518 3540 3542
O7777 1370# 5073 5246 5409 5670 5770 5884 5896 6049 6064 6361 7126
7297 7429 7571 7711
OFFSET 7413 7415 7416 7556 7558
OK 1898 1924# 1941# 1948 1993 2021# 2038# 2045 2090 2118# 2135# 2142
2187 2212# 2230# 2237 2282 2307# 2321# 2327 2360 2383# 2397# 2403
2436 2461# 2479# 2486 2532 2559# 2579# 2586 2631 2668# 2688# 2702
2792 2821# 2841# 2848 2893 2919# 2938# 2945 2990 3016# 3035# 3042
3090 3122# 3137# 3143 3177 3204# 3221# 3227 3268 3306# 3325# 3331
3373 3402# 3422# 3429 3751 3769# 3777 3778# 3799# 3805 4148 4177#
4192# 4198 4232 4260# 4275# 4281 4314 4330# 4349# 4358 4394 4410#
4429# 4438 4844 4858# 4881# 4887 4920 4937# 4955# 4964# 4974 5015
5051# 5079# 5086# 5097# 5109 5172 5209# 5269# 5277 5344 5374# 5418#
5424# 5434 5491 5550# 5572# 5579 5618 5641# 5679# 5685# 5695 5847
5869# 5893# 5905# 5917# 5929# 5937 6011 6030# 6053# 6061# 6073# 6085#
6097# 6105 6182 6208# 6223# 6243# 6260# 6277# 6283 6436 6480# 6524#
6530 6845 6872# 6891# 6897 6931 6956# 6974# 6980 7035 7076# 7140#
7150 7208 7239# 7277# 7293 7642 7676# 7717# 7727# 7737 7784 7871#
7881 7932 7994# 8008# 8017# 8049# 8077# 8102# 8130# 8140# 8175# 8198#
8204# 8231# 8246 8284 8318# 8365# 8374 8424 8474# 8524# 8533 8571
8596# 8629# 8640 8680 8726# 8777# 8785# 8793 8968 9012# 9040# 9048
9079 9101# 9116# 9122 9155 9173# 9184# 9205# 9211 9256 9281# 9300#
9310# 9318 9408 9426# 9440# 9461# 9467
OK_ADD 3499 3522# 3548# 3559
OK_SUB 3500 3523# 3549# 3560
OK_SUBB 3501 3524# 3550# 3561
OLD_PTE 8421 8470# 8485 8489 8492 8495#
OLD_PXCT 8969 9018 9024#
OLD_USER 8423 8472# 8498 8501# 8503 8505 8685 8731# 8740 8743# 8745 8747
8749
OLD_VMA 8422 8471# 8508 8511# 8513 8684 8730# 8752 8756 8759 8762# 8845
8872# 8881 8885 8886 8887#
O_CRAM_ADDR 252+ 253+ 712+ 713+
O_N 562+ 563+
O_SN 603+ 604+
PAGE_BIT 6573 6602
PAGE_USER 5649 5651 5652 5659
PAGING_OFF 1352# 1644 5279 5431 5687 5783 5932 6100 6265 6372 6498 6533
6623 6742 6813 6900 6983 7152 7295 7452 7593 7740 8536 8642
8796 8920
PAGING_ON 1350# 5227 5252 5407 5668 5764 5876 6041 6209 6229 6249 6352
6496 6593 6693 6798 6873 6958 7078 7132 7244 7283 7369 7435
7529 7577 7680 7718 8469 8598 8728 8870
PAIR_SIDE 5061 5068
PAR_ERR 1030+# 7788 7821# 7822 7826 7827 7861# 7862 7865 7866
PAR_LEFT 1273+#
PAR_RIGHT 1274+#
PBELL 977+#
PE 772+ 1635
PE0_ADR 1353 1562# 5048
PE1_ADR 1351 1563# 5046
PE_1 1294+#
PE_DET_ENB 1082+#
PFU 1564# 1640
PFU_ADR 1561# 1640 1685 7243
PF_CAUSE 1728 1730# 1736 1740 1772 7333 7496 7637
PF_DISPATCH 59 1649* 1730 5882 5910 6047 6078
PF_INFO 5349 5380 5381
PF_INFO_CAUSE 5336# 5381
PF_INFO_PTE 5337# 5380
PF_NAME 61 1740* 5077 5250 5382 5413 5665 5674 5758 5769 5881 5883
5899 5909 5911 5923 6046 6048 6067 6077 6079 6091 6216 6218
6236 6238 6255 6272 6358 6360 7130 7253 7272 7433 7575 7715
PF_TRAP 60 1695* 5076 5249 5412 5673 5768 5898 5922 6066 6090 6217
6237 6254 6271 6359 7129 7432 7574 7714
PHU 1574# 1641
PHU_ADR 1573# 1641 7242 7296 8597
PHY_PAG 7080 7082 7086 7088 7090 7092
PI_REQ_1 1254+#
PI_REQ_2 1253+#
PI_REQ_3 1252+#
PI_REQ_4 1251+#
PI_REQ_5 1250+#
PI_REQ_6 1249+#
PI_REQ_7 1248+#
PMA 6432 6486# 6514 6571 6600 6602 6610 8682 8737# 8769 8843 8878#
8895
PMA_HIGH_BIT 7034 7074# 7098 7102# 7103
PM_AC 875+# 999+
PNTSIX 889+#
POCT_SUP 973+#
POINT 739+ 2677 2689 2690
POWER_OF_2 1320# 1321
PRGNAM 1361#
PRINT_CRLF 885+#
PRINT_DEC 909+#
PRINT_MSG 893+#
PRINT_OCT_1 933+#
PRINT_OCT_11 965+#
PRINT_OCT_12 969+#
PRINT_OCT_2 937+#
PRINT_OCT_3 941+#
PRINT_OCT_4 945+#
PRINT_OCT_5 949+#
PRINT_OCT_6 953+#
PRINT_OCT_7 957+#
PRINT_OCT_8 961+#
PRINT_TXT 901+#
PRINT_WORD 897+#
PRT_CRLF_F 913+#
PRT_DEC_F 929+#
PRT_MSG_F 917+#
PRT_TXT_F 921+# 1473 1476
PTE 5168 5217# 5219 5236# 5340 5380# 5388 5389 7027 7084# 7107 7645
7686# 7687 7689 8568 8603# 8606
PTSTNUM 762+
PTXT_CRLF 905+#
PTXT_CRLF_F 925+# 1517 1521
Q_BIT_NUMBER 1828
Q_REG 1824 1826# 1829# 1831
RAC_LO 1265+#
RAM_ERR 1308+#
RBAD_DATA 1261+#
RCOM_ADR 1260+#
RCVDATA 9409 9459# 9460 9498 9522# 9523
RDATA 1258+#
RDATA0 1272+#
RDATA1 1271+#
RDATA10 1227+#
RDATA11 1226+#
RDATA12 1222+#
RDATA13 1221+#
RDATA14 1220+#
RDATA15 1219+#
RDATA16 1218+#
RDATA17 1217+#
RDATA18 1216+#
RDATA19 1215+#
RDATA2 1270+#
RDATA20 1211+#
RDATA21 1210+#
RDATA22 1209+#
RDATA23 1208+#
RDATA24 1207+#
RDATA25 1206+#
RDATA26 1205+#
RDATA27 1204+#
RDATA28 1200+#
RDATA29 1199+#
RDATA3 1269+#
RDATA30 1198+#
RDATA31 1197+#
RDATA32 1196+#
RDATA33 1195+#
RDATA34 1194+#
RDATA35 1193+#
RDATA4 1233+#
RDATA5 1232+#
RDATA6 1231+#
RDATA7 1230+#
RDATA8 1229+#
RDATA9 1228+#
RD_0 722+#
RD_1 723+#
RD_100 726+# 7821 7861
RD_101 727+#
RD_102 728+#
RD_103 729+#
RD_2 724+#
RD_3 725+#
RD_300 730+#
RD_301 731+# 4083 5082 5255 8012 8135
RD_303 732+# 8520 8625 8772 8898 9293
REC_PE 1243+#
REG_EXAMINE 722+ 723+ 724+ 725+ 726+ 727+ 728+ 729+ 730+ 731+ 732+ 792+
REM_DIAG_ENB 1303+#
REM_DIAG_PRO 1304+#
REPEAT 761+ 6714 6718 7401 7405 7544 7548
REPLACEI 741+ 2682
RESET 1083+#
RIO_BUSY 1262+#
RIO_DATA 1259+#
RMEM_BUSY 1263+#
RPT_ERR_FLAG 819+ 1627# 1633# 4077# 4100# 5050# 5111# 5208# 5280# 5373# 5436# 5870#
5939# 6031# 6108# 6692# 6743# 7075# 7153# 7240# 7298# 7367# 7454# 7527#
7595# 7677# 7741# 7814# 7883# 7995# 8250# 8319# 8372# 8473# 8535# 8595#
8643# 8732# 8795# 8873# 8919# 9014# 9050# 9425# 9468#
RRESET 1264+#
RUN 1187+#
RUN_1 1282+#
RW 7858 7867 7870
R_CLK_ENB0 1311+#
SCAD_Q 63 1835* 2221 2316 2392 2470 2570 2830 2928 3025 3131 3411
3535 9522
SCAD_VAL 1869 1872# 1873# 1874# 1876 3502 3535# 3536 3553
SCANI 740+ 2693 2694
SC_0 779+ 1634
SEL 351+ 352+ 362+ 363+ 373+ 374+
SEND_CMD_LINE 1005+#
SEND_EB_LINE 996+#
SEND_EC_LINE 997+#
SEND_EI_LINE 993+#
SEND_EJ_LINE 994+#
SEND_EK_LINE 995+#
SEND_EM_LINE 998+#
SEND_ER_LINE 992+#
SEND_INFO 1017+#
SEND_LINE 760+
SEND_NUL 765+ 1632 1645 1734 6712 6716 7399 7403 7542 7546
SEND_PM_LINE 999+#
SEND_UUO_1 1009+#
SEND_X1A_LINE 1000+#
SEND_X1B_LINE 1001+#
SERIAL 62 1789* 1871 1935 2032 2129 2682 3215 3319 3659 3777 3794
3887 4026 4188 4511 4626 4740 5565 6732 8007 8048 8073 8098
8126 8174 8203 8230 8364 9439 9459
SETNXT 713+ 766+ 1325
SET_CRAM_ADR 1325# 1351 1353 1642 1685 1732 1930 2027 2124 2218 2314 2390
2467 2565 2680 2827 2925 3022 3129 3210 3312 3408 3529 3531
3533 3657 3773 3792 3885 3993 4023 4081 4184 4267 4331 4411
4509 4624 4738 4866 4870 4938 4969 5045 5047 5059 5068 5070
5211 5218 5220 5229 5238 5244 5378 5387 5390 5396 5403 5408
5548 5563 5581 5647 5652 5669 5762 5765 5872 5878 5896 5920
6033 6043 6064 6088 6212 6232 6252 6269 6355 6500 6505 6507
6510 6516 6606 6612 6695 6701 6707 6723 6727 6802 6879 6883
6963 6967 7087 7089 7091 7094 7101 7106 7116 7124 7242 7249
7262 7270 7281 7296 7378 7381 7384 7387 7390 7407 7410 7423
7437 7532 7535 7550 7553 7565 7579 7688 7691 7705 7819 7836
7854 7869 8002 8043 8068 8093 8121 8169 8194 8216 8225 8248
8334 8360 8488 8502 8504 8512 8518 8597 8602 8615 8623 8744
8746 8748 8755 8767 8770 8884 8893 8896 9021 9025 9029 9103
9108 9178 9199 9287 9431 9438 9446 9451 9458 9517 9521
SET_C 713+#
SIDE 5384 5386 5399 5401 5643 5645 5647 6595 6600 6602
SINGLE_BIT 1321# 1938 2035 2132 2227 2476 2576 2695 2838 2935 3032 3218
3322 3419
SINGLE_CLK 1170+# 9289 9291
SOURCE_ADDR 711+
SPEC_ASK 56 1438*
SPEC_DIALOGUE 55 1396*
SPEC_PRT 57 1481*
SRC 269+ 270+ 282+ 283+
SS_MODE 1152+#
STEP_U_NEXT 714+# 1687 1691 1829 1931 2028 2125 3211 3313 3774 4024 4185
5072 5246 5409 5670 5766 5879 6044 6356 6519 6613 6728 6803
6884 6968 7125 7271 7428 7570 7710 7860 8003 8044 8069 8094
8122 8170 8195 8226 8361 8771 8897 9030 9109 9179 9200
STK_RESET 1150+#
SU 1536# 1638
SUBTEST 1927 1930 1931 1934 2024 2027 2028 2031 2121 2124 2125 2128
2215 2218 2219 2220 2309 2312 2313 2314 2385 2388 2389 2390
2464 2467 2469 2562 2565 2567 2568 2569 2671 2674 2675 2680
2824 2827 2829 2834 2835 2922 2925 2927 2932 3019 3022 3024
3029 3125 3128 3129 3130 3135 3207 3210 3211 3214 3309 3312
3316 3317 3318 3405 3408 3410 3415 3416 3654 3657 3660 3666
3667 3668 3882 3885 3888 3894 3895 3896 4179 4182 4184 4185
4262 4265 4267 4506 4509 4512 4516 4621 4624 4627 4631 4735
4738 4741 4745 5376 5380 5381 5552 5555 5556 5557 5558 5559
5560 5561 5563 6876 6880 6888 6889 6960 6964 6966 6972 7246
7248 7250 7252 7682 7684 7686 7721 7724 8600 8603 8604 9283
9287 9292 9296 9299 9306 9309
SU_ADR 1535# 1638
SYNC_CLK 812+ 9288
TE 777+ 1630
TEMP 9257 9293# 9296 9306
TEN_INT 1297+# 8013 8016 8136 8139
TERM_CARR 1302+#
TEST_EDIT 1365#
TEST_INIT 58 1579*
TEST_VERSION 1364#
TEXT 901+ 902+ 905+ 906+ 921+ 922+ 925+ 926+
TICK 813+ 1327 9292
TICKS 7031 7117# 7120# 7125 7143# 7205 7263# 7266# 7271 7286# 7335 7424#
7427# 7428 7498 7566# 7569# 7570 7639 7702# 7706# 7708 7786 7851#
7855# 7860 7873# 8569 8616# 8619# 8624 8633#
TIMOUT 818+
TIU 1541# 1639
TIU_ADR 1557# 1560 1639 1642 1732 5920 6088 7281
TIU_CNT 1558# 1643 1733 5921 6089 7282
TIU_MEMCLR 1560# 8216 8248
TP 776+
TRAP_ENB 1162+#
TST1 64 1880*
TST10 73 2772*
TST11 74 2875*
TST12 75 2972*
TST13 76 3069*
TST14 77 3159*
TST15 78 3249*
TST16 79 3353*
TST17 80 3456*
TST18 81 3589*
TST19 82 3737*
TST2 65 1975*
TST20 83 3821*
TST21 84 3955*
TST22 85 4049*
TST23 86 4129*
TST24 87 4216*
TST25 88 4299*
TST26 89 4377*
TST27 90 4457*
TST28 91 4571*
TST29 92 4686*
TST3 66 2072*
TST30 93 4802*
TST31 94 4906*
TST32 95 5000*
TST33 96 5153*
TST34 97 5322*
TST35 98 5463*
TST36 99 5602*
TST37 100 5722*
TST38 101 5827*
TST39 102 5992*
TST4 67 2169*
TST40 103 6167*
TST41 104 6317*
TST42 105 6402*
TST43 106 6553*
TST44 107 6643*
TST45 108 6763*
TST46 109 6832*
TST47 110 6919*
TST48 111 7002*
TST49 112 7185*
TST5 68 2264*
TST50 113 7317*
TST51 114 7483*
TST52 115 7624*
TST53 116 7772*
TST54 117 7918*
TST55 118 8260*
TST56 119 8392*
TST57 120 8554*
TST58 121 8661*
TST59 122 8824*
TST6 69 2343*
TST60 123 8948*
TST61 124 9067*
TST62 125 9140*
TST63 126 9227*
TST64 127 9394*
TST65 128 9484*
TST7 70 2419*
TST8 71 2513*
TST9 72 2613*
TST_U_1 7947# 7997
TST_U_2 7953# 8039
TST_U_3_4 7959# 8063
TST_U_5 7965# 8116
TST_U_6 7971# 8162
TST_U_7 7977# 8190
TST_U_8 7985# 8219
TST_U_ADR 1326 1907# 1914 1915 2002# 2011 2012 2099# 2108 2109 2196# 2202
2203 2290# 2314 2368# 2390 2444# 2451 2452 2540# 2549 2550 2643#
2658 2659 2800# 2809 2810 2811 2902# 2909 2910 2999# 3006 3007
3098# 3108 3109 3110 3111 3185# 3194 3195 3276# 3296 3297 3381#
3390 3391 3392 3479# 3490 3491 3492 3493 3494 3495 3496 3621#
3628 3629 3758# 3765 3766 3851# 3858 3859 3976# 3986 3987 4067#
4081 4155# 4166 4167 4241# 4249 4250 4320# 4331 4400# 4411 4483#
4491 4492 4493 4597# 4606 4607 4608 4714# 4722 4723 4827# 4841
4926# 4934 4938 5027# 5039 5040 5041 5042 5068 5192# 5203 5204
5205 5359# 5368 5369 5370 5513# 5543 5544 5545 5624# 5636 5637
5638 5744# 5753 5754 5853# 5861 5862 6017# 6026 6027 6191# 6203
6204 6205 6337# 6355 6463# 6474 6475 6476 6477 6510 6579# 6590
6606 6678# 6695 6696 6701 6707 6708 6723 6727 6781# 6802 6854#
6868 6869 6941# 6952 6953 7041# 7067 7068 7069 7221# 7232 7233
7234 7345# 7358 7359 7360 7361 7362 7505# 7518 7519 7520 7521
7522 7656# 7669 7670 7671 7798# 7809 7810 7811 7946# 7997 8002
8039 8043 8063 8068 8093 8116 8121 8162 8169 8190 8194 8219
8225 8307# 8334 8360 8453# 8462 8463 8464 8465 8518 8577# 8588
8589 8590 8709# 8720 8721 8722 8723 8767 8852# 8863 8864 8893
8999# 9008 9009 9086# 9097 9098 9162# 9169 9170 9263# 9270 9271
9416# 9431 9435 9446 9451 9455 9504# 9517
TST_U 1326 1908# 2003# 2100# 2197# 2291# 2369# 2445# 2541# 2644# 2801# 2903#
3000# 3099# 3186# 3277# 3382# 3480# 3622# 3759# 3852# 3977# 4068# 4156#
4242# 4321# 4401# 4484# 4598# 4715# 4828# 4927# 5028# 5193# 5360# 5514#
5625# 5745# 5854# 6018# 6192# 6338# 6464# 6580# 6679# 6782# 6855# 6942#
7042# 7222# 7346# 7506# 7657# 7799# 8308# 8454# 8578# 8710# 8853# 9000#
9087# 9163# 9264# 9417# 9505#
TTI_CLR 983+#
TTI_DEC 984+#
TTI_YES 982+# 1474 1477
TT_ALTM 981+#
TUA 4841# 4850 4851 4852 4853 4854
TUA_0 1914# 1920 2011# 2017 2108# 2114 2202# 2208 2451# 2457 2549# 2555
2658# 2664 2809# 2816 2909# 2915 3006# 3012 3108# 3116 3194# 3200
3296# 3302 3390# 3397 3628# 3638 3765# 3773 3858# 3875 4166# 4172
4249# 4255 4722# 4728 9169# 9199 9270# 9276
TUA_1 1915# 1921 2012# 2018 2109# 2115 2203# 2209 2452# 2458 2550# 2556
2659# 2665 2810# 2817 2910# 2916 3007# 3013 3109# 3117 3195# 3201
3297# 3303 3391# 3398 3629# 3639 3766# 3792 3859# 3876 4167# 4173
4250# 4256 4723# 4729 9170# 9178 9271# 9277
TUA_2 2811# 2818 3110# 3118 3392# 3399
TUA_3 3111# 3119
TUA_ACVMA 6204# 6232 6269
TUA_ADD 3494# 3507 3508 3509 3510
TUA_BASE 5545# 5563
TUA_CONT 5041# 5070
TUA_FE_0 3491# 3507 3509 3511 3513 3515 3517 3542
TUA_FE__1 3493# 3508 3510 3512 3514 3516 3518
TUA_FINI 5544# 5581
TUA_INIT 5543# 5548 7809# 7819 7836 9008# 9021 9097# 9103
TUA_J 7358# 7387 7407 7437 7518# 7532 7550 7579
TUA_LDPAG 5637# 5652 5753# 5762 5861# 5872 6026# 6033 6203# 6212 8463# 8502
8721# 8744
TUA_LDVMA 5636# 5647
TUA_LD_PT 7360# 7384 7391 7520# 7536
TUA_NEXT 7810# 9009# 9025 9029
TUA_NXT 4934# 4969
TUA_PAG 5039# 5059 5204# 5218 5369# 5387 6475# 6500 7067# 7094 7101 7106
7232# 7249 7669# 7688 8464# 8488 8588# 8602
TUA_PAGVMA 6474# 6505
TUA_PE0 5042# 5047
TUA_PE1 5040# 5045
TUA_PHYSVMA 6205# 6252
TUA_READ 6027# 6043 6477# 6516 7362# 7378 7408 7411 7423 7522# 7551 7554
7565 8465# 8504 8723# 8748 8770 8864# 8896
TUA_REF 6590# 6612
TUA_R 3987# 4023 4492# 4499 4607# 4614
TUA_SC_0 3490# 3507 3508 3511 3512 3515 3516 3540
TUA_SC__1 3492# 3509 3510 3513 3514 3517 3518
TUA_SUB 3495# 3511 3512 3513 3514
TUA_SUBB 3496# 3515 3516 3517 3518
TUA_TEST 9098# 9108
TUA_TST 5205# 5230 5370# 5397 6869# 6883 6953# 6967 7069# 7087 7089 7091
7124 7234# 7270 7671# 7705 7811# 7854 7870 8590# 8623
TUA_VMA 5203# 5211 5212 5220 5229 5238 5244 5368# 5378 5379 5390 5396
5403 5408 6868# 6879 6952# 6963 7068# 7116 7233# 7262 7359# 7390
7410 7519# 7535 7553 7670# 7691 8462# 8512 8589# 8615 8720# 8755
8863# 8884
TUA_WRITE 5638# 5669 5754# 5765 5862# 5878 6476# 6507 7361# 7381 7388 7521#
7533 8722# 8746
TUA_WT 4493# 4500 4608# 4615
TUA_W 3986# 3993 4491# 4498 4606# 4613
U 610+# 1538 1539 1543 1544 1545 1546 1547 1548 1549 1550 1551
1552 1553 1554 1555 1566 1567 1568 1569 1570 1571 1576 1910
1911 1912 2005 2006 2007 2008 2009 2102 2103 2104 2105 2106
2199 2200 2293 2294 2295 2371 2372 2447 2448 2449 2543 2544
2545 2546 2547 2646 2647 2648 2649 2650 2651 2652 2653 2654
2655 2656 2803 2804 2805 2806 2807 2905 2906 2907 3002 3003
3004 3101 3102 3103 3104 3105 3106 3188 3189 3190 3191 3192
3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290
3291 3292 3293 3294 3384 3385 3386 3387 3388 3482 3483 3484
3485 3486 3487 3488 3624 3625 3626 3761 3762 3763 3854 3855
3856 3979 3980 3981 3982 3983 3984 4070 4071 4072 4073 4158
4159 4160 4161 4162 4163 4164 4244 4245 4246 4247 4323 4324
4325 4326 4403 4404 4405 4406 4486 4487 4488 4489 4600 4601
4602 4603 4604 4717 4718 4719 4720 4830 4831 4832 4833 4834
4835 4836 4837 4838 4839 4929 4930 4931 4932 5030 5031 5032
5033 5034 5035 5036 5037 5195 5196 5197 5198 5199 5200 5201
5362 5363 5364 5365 5366 5516 5517 5518 5519 5520 5521 5522
5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534
5535 5536 5537 5538 5539 5540 5541 5627 5628 5629 5630 5631
5632 5633 5634 5747 5748 5749 5750 5751 5856 5857 5858 5859
6020 6021 6022 6023 6024 6194 6195 6196 6197 6198 6199 6200
6201 6340 6341 6342 6343 6344 6345 6346 6347 6466 6467 6468
6469 6470 6471 6472 6582 6583 6584 6585 6586 6587 6588 6681
6682 6683 6684 6685 6686 6687 6688 6784 6785 6786 6787 6788
6789 6790 6791 6792 6793 6857 6858 6859 6860 6861 6862 6863
6864 6865 6866 6944 6945 6946 6947 6948 6949 6950 7044 7045
7046 7047 7048 7049 7050 7051 7052 7053 7054 7055 7056 7057
7058 7059 7060 7061 7062 7063 7064 7065 7224 7225 7226 7227
7228 7229 7230 7348 7349 7350 7351 7352 7353 7354 7355 7356
7508 7509 7510 7511 7512 7513 7514 7515 7516 7659 7660 7661
7662 7663 7664 7665 7666 7667 7801 7802 7803 7804 7805 7806
7807 7949 7950 7951 7955 7956 7957 7961 7962 7963 7967 7968
7969 7973 7974 7975 7979 7980 7981 7982 7983 7987 7988 7989
7990 7991 8310 8311 8312 8313 8314 8456 8457 8458 8459 8460
8580 8581 8582 8583 8584 8585 8586 8712 8713 8714 8715 8716
8717 8718 8855 8856 8857 8858 8859 8860 8861 9002 9003 9004
9005 9006 9089 9090 9091 9092 9093 9094 9095 9165 9166 9167
9266 9267 9268 9419 9420 9421 9507 9508 9509 9510 9511
UUO 865+ 887+ 891+ 895+ 899+ 903+ 907+ 911+ 915+ 919+ 923+ 927+
931+ 935+ 939+ 943+ 947+ 951+ 955+ 959+ 963+ 967+ 971+ 975+
977+ 981+ 982+ 983+ 984+ 988+ 992+ 993+ 994+ 995+ 996+ 997+
998+ 999+ 1000+ 1001+ 1005+ 1009+ 1013+ 1017+ 1022+ 1023+
U_0 253+ 257+ 270+ 283+ 297+ 310+ 331+ 615+ 630+ 632+ 658+#
U_0_DEFAULT 632+ 645+# 658+
U_1 352+ 363+ 374+ 394+ 398+ 403+ 407+ 411+ 416+ 420+ 449+ 459+
472+ 492+ 521+ 621+ 627+ 630+ 633+ 659+#
U_1_DEFAULT 633+ 646+# 659+
U_2 527+ 531+ 535+ 539+ 543+ 547+ 551+ 555+ 559+ 563+ 569+ 582+
595+ 604+ 630+ 634+ 660+#
U_2_DEFAULT 634+ 647+# 660+
U_3 390+ 621+ 627+ 635+ 661+#
U_3_DEFAULT 635+ 648+# 661+
U_A 309+# 312+ 313+ 314+ 315+ 316+ 317+ 318+ 319+ 320+ 321+ 322+
323+ 324+ 325+ 326+ 327+ 1337 7052 7064 7065 7226 7659 7660
7950 7951 7956 7957 7962 7963 7968 7969 7974 7975 7980 7981
7988 7989 8313 8314 8582
U_ALU_ADD 259+# 1548 3286 4326 4406 4930 7052 7226 7348 7349 7508 7509
7659 7660 7802 8582
U_ALU_AND 263+# 1331 3287 7064 7950 7956 7962 7963 7968 7969 7974 7980
7988 8313 9419 9507 9509
U_ALU_MASK 264+#
U_ALU_OR 262+# 1333 1334 1335 1336 1337 1341 1343 1547 4600 9510
U_ALU_PARITY_OK 389+#
U_ALU_RSUB 261+#
U_ALU_SUB 260+#
U_ALU_XNOR 266+# 1332 1549 3279
U_ALU_XOR 265+# 1912 2009 2106 3192 3294 4164 6688 7065 7951 7957 7975
7981 7989 8314
U_ALU 256+# 259+ 260+ 261+ 262+ 263+ 264+ 265+ 266+
U_A_AR 315+# 1547 1912 2009 2106 3192 3286 4164
U_A_ARX 316+# 1548 1549 3294
U_A_BR 317+# 7348 7349 7508 7509
U_A_BRX 318+# 1343 4600
U_A_EBR 320+#
U_A_FLG 323+#
U_A_HR 314+#
U_A_MAG 312+#
U_A_MASK 322+#
U_A_ONE 319+#
U_A_PC 313+#
U_A_PI 324+#
U_A_T0 326+# 1335 3279 3280 3281 3282 3283 3284 3288 3289 3290 3291
3292 4326 4406 4930 6688 7802
U_A_T1 327+# 1331 1332 1336
U_A_UBR 321+#
U_A_XWD1 325+#
U_B 330+# 333+ 334+ 335+ 336+ 337+ 338+ 339+ 340+ 341+ 342+ 343+
344+ 345+ 346+ 347+ 348+ 7044 7045 7046 7047 7048 7049 7050
7051 7052 7053 7062 7224 7225 7226 7348 7349 7350 7508 7509
7510 7659 7660 7661 8312 8580 8581 8582
U_BYTE 448+# 451+ 452+ 453+ 454+ 455+
U_BYTE_1 451+# 3280 3288
U_BYTE_2 452+# 3281 3289
U_BYTE_3 453+# 3282 3290
U_BYTE_4 454+# 3283 3291
U_BYTE_5 455+# 3284 3292
U_B_AR 336+# 1546
U_B_ARX 337+# 1547 1548
U_B_BR 338+# 1550
U_B_BRX 339+# 1551
U_B_EBR 341+#
U_B_FLG 344+#
U_B_HR 335+#
U_B_MAG 333+#
U_B_MASK 343+#
U_B_ONE 340+#
U_B_PC 334+#
U_B_PI 345+#
U_B_T0 347+# 3279 3280 3281 3282 3283 3284 3287 3288 3289 3290 3291
3292 4323 4326 4403 4406 4600 4602 4603 4604 4929 4930 5030
5031 5195 5362 5627 5628 5747 6020 6196 6197 6199 6340 6466
6582 6681 6784 6857 6944 7801 7802 8456 8712 8855
U_B_T1 348+# 1332 1538 1539 6785 6858
U_B_UBR 342+#
U_B_XWD1 346+#
U_CALL 558+#
U_CHKL 402+# 1345
U_CHKR 415+# 1345
U_CRY38 526+#
U_DBM_APR_FLAGS 378+# 7950 7956 7962 7968 7974 7980 7988 8313
U_DBM_BYTES 379+# 3188 3190
U_DBM_DP 382+# 2102 3280 3281 3282 3283 3284 3288 3289 3290 3291 3292
U_DBM_DP_SWAP 383+# 2005 2007 2104
U_DBM_EXP 380+# 3761 3762
U_DBM_MEM 385+# 3984 4160 4163 6472 6588 6687 6793 6866 6950 7064 7356
7516 7667 7806 8718 8861
U_DBM_MSEC 381+# 9419 9507 9509
U_DBM_N 386+# 1340 1552 1910 1911 3103 3104 4602 4603 4604 4717 4718
4830 4831
U_DBM_PF_DISP 377+# 1567
U_DBM_SCAD 376+# 2199 2200 2293 2294 2295 2371 2372 2449 2544 2546 2646
2647 2648 2649 2650 2651 2652 2653 2654 2655 2805 2807 2905
2906 3002 3003 3101 3102 3105 3385 3388 3486 3487 3488 9510
U_DBM_VMA 384+# 3626 3856 4486 4601 4720 5518 9006
U_DBM 373+# 376+ 377+ 378+ 379+ 380+ 381+ 382+ 383+ 384+ 385+ 386+
U_DBUS 362+# 365+ 366+ 367+ 368+ 369+ 370+
U_DBUS_DBM 370+# 1329 1340 1567 1910 1911 2199 2200 2293 2294 2295 2371
2372 2449 2805 2807 3103 3104 3280 3281 3282 3283 3284 3288
3289 3290 3291 3292 3385 3388 3486 3487 3488 3626 3856 3984
4160 4163 4486 4601 4602 4603 4604 4717 4718 4720 4830 4831
5518 6472 6588 6687 6793 6866 6950 7064 7356 7516 7667 7806
7950 7956 7962 7968 7974 7980 7988 8313 8718 8861 9006 9419
9507 9509 9510
U_DBUS_DP 368+# 1328 1544 4245 4247 6470 6586 6685 6789 6791 6864 6948
7354 7514 7665 7804 9090 9091 9094
U_DBUS_PC_FLAGS 365+#
U_DBUS_PI_NEW 366+#
U_DBUS_RAM 369+# 1330 9095
U_DBUS_VMA 367+#
U_DEST 296+# 299+ 300+ 301+ 302+ 303+ 304+ 305+ 306+
U_DEST_A 299+# 3280 3281 3282 3283 3284 3288 3289 3290 3291 3292
U_DEST_AD 300+# 1546 1547 1548 1550 1551 3279 3287 4323 4326 4403 4406
4602 4603 4604 4929 4930 5030 5031 5195 5362 5627 5628 5747
6020 6196 6197 6199 6340 6466 6582 6681 6784 6785 6857 6858
6944 7044 7045 7046 7047 7048 7049 7050 7051 7052 7053 7062
7224 7225 7226 7348 7349 7350 7508 7509 7510 7659 7660 7661
7802 7949 7955 7961 7973 7979 7987 8312 8456 8580 8581 8582
8712 8855 9511
U_DEST_AD_DIV2 306+# 7801
U_DEST_AD_MUL2 304+#
U_DEST_PASS 302+#
U_DEST_Q_AD 301+# 1910 1911 2006 2008 2103 2105 2199 2200 2293 2294 2295
2371 2372 2449 2547 2656 2805 2807 2907 3004 3103 3104 3106
3189 3191 3285 3293 3385 3388 3486 3487 3488 3626 3763 3856
3984 4160 4163 4486 4601 4720 5518 6687 7064 7950 7956 7962
7968 7974 7980 7988 8313 9006 9419 9421 9510
U_DEST_Q_DIV2 305+#
U_DEST_Q_MUL2 303+# 1538 1539
U_DISP 471+# 474+ 475+ 476+ 477+ 478+ 479+ 480+ 481+ 482+ 483+ 484+
485+ 486+ 487+ 488+
U_DISP_ADISP 480+#
U_DISP_AREAD 476+#
U_DISP_BDISP 481+#
U_DISP_BYTE 486+#
U_DISP_CONSOLE 474+#
U_DISP_DP 479+#
U_DISP_DP_LEFT 477+# 1567
U_DISP_DROM 475+#
U_DISP_EAMODE 487+#
U_DISP_MUL 483+#
U_DISP_NICOND 485+#
U_DISP_NORM 478+#
U_DISP_PAGEFAIL 484+#
U_DISP_RETURN 482+#
U_DISP_SCAD0 488+#
U_DIVIDE 546+#
U_FMWRITE 538+# 1328 1329 9090 9091
U_GENL 397+# 1344
U_GENR 410+# 1344
U_J 252+# 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553
1554 1555 1566 1568 1570 1576 1911 2005 2007 2008 2102 2104
2105 2447 2448 2543 2544 2545 2546 2646 2647 2648 2649 2650
2651 2652 2653 2654 2655 2803 2804 2806 2905 2906 3002 3003
3101 3102 3103 3104 3105 3188 3190 3191 3279 3280 3281 3282
3283 3284 3285 3287 3288 3289 3290 3291 3292 3293 3384 3386
3387 3624 3625 3761 3762 3854 3855 3979 3980 3982 3983 4070
4071 4072 4158 4159 4161 4162 4163 4244 4246 4323 4324 4325
4326 4403 4404 4405 4406 4487 4488 4489 4600 4602 4603 4604
4717 4718 4719 4832 4834 4836 4838 4929 4930 4931 4932 5030
5031 5032 5033 5034 5035 5036 5037 5195 5196 5198 5199 5200
5362 5363 5365 5517 5519 5520 5521 5522 5523 5524 5525 5526
5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538
5539 5540 5629 5630 5632 5633 5747 5748 5750 5856 5858 6020
6021 6023 6194 6195 6196 6197 6198 6199 6200 6340 6341 6342
6343 6344 6345 6346 6466 6467 6468 6469 6471 6582 6583 6584
6585 6587 6681 6682 6683 6684 6686 6687 6784 6785 6786 6787
6788 6789 6790 6791 6792 6857 6858 6859 6860 6861 6862 6863
6865 6944 6945 6946 6947 6949 7044 7045 7046 7047 7048 7049
7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061
7062 7063 7064 7224 7225 7226 7227 7228 7229 7230 7348 7349
7350 7351 7352 7353 7354 7355 7356 7508 7509 7510 7511 7512
7513 7514 7515 7516 7659 7660 7661 7662 7663 7664 7665 7666
7667 7801 7802 7803 7804 7805 7806 7807 7949 7950 7955 7956
7961 7962 7967 7968 7973 7974 7979 7980 7982 7983 7987 7988
7989 7990 7991 8310 8311 8312 8313 8456 8457 8458 8459 8580
8581 8582 8583 8584 8585 8712 8713 8714 8715 8717 8855 8856
8857 8858 8860 9005 9089 9090 9092 9093 9094 9165 9166 9266
9267 9419 9420 9421 9507 9508 9509 9510 9511
U_LOADFE 534+# 2803 2804 2806 3384 3386 3387 3483 3485 9266 9267 9507
9508 9509
U_LOADSC 530+# 2447 2448 2543 2545 3482 3484 9165 9166
U_LSRC 269+# 272+ 273+ 274+ 275+ 276+ 277+ 278+ 279+
U_LSRC_0A 276+# 1331 1335 1336 1337 1343 1547 1549 7052 7226 7659 7660
8582
U_LSRC_0B 275+# 3287 4600
U_LSRC_0Q 274+# 1334
U_LSRC_AB 273+# 1332 1548 3279 4326 4406 4930 7348 7349 7508 7509 7802
U_LSRC_AQ 272+# 1912 2009 2106 3192 3286 3294 4164 6688 7065 7951 7957
7963 7969 7975 7981 7989 8314
U_LSRC_D0 279+# 1333 1341 9510
U_LSRC_DA 277+# 7064 7950 7956 7962 7968 7974 7980 7988 8313 9507 9509
U_LSRC_DQ 278+# 9419
U_MEM 542+# 3980 3981 3983 3984 4070 4071 4072 4073 4159 4160 4162
4163 4244 4245 4246 4247 4324 4325 4404 4405 4486 4487 4488
4489 4600 4601 4719 4832 4833 4836 4837 4838 4839 4931 4932
5032 5034 5035 5036 5037 5196 5198 5199 5200 5201 5363 5365
5366 5520 5522 5524 5526 5528 5530 5532 5534 5536 5538 5540
5629 5630 5632 5633 5634 5748 5750 5751 5856 5858 5859 6021
6023 6024 6194 6198 6200 6201 6341 6343 6346 6347 6467 6469
6470 6471 6472 6583 6585 6586 6587 6588 6682 6684 6685 6686
6687 6786 6788 6789 6790 6791 6792 6793 6859 6861 6863 6864
6865 6866 6945 6947 6948 6949 6950 7054 7055 7056 7058 7059
7060 7061 7063 7064 7227 7229 7230 7351 7353 7354 7355 7356
7511 7513 7514 7515 7516 7662 7664 7665 7666 7667 7803 7804
7805 7806 7982 7983 7990 7991 8457 8459 8460 8583 8585 8586
8713 8715 8716 8717 8718 8856 8858 8859 8860 8861 9005
U_MULTI_PREC 550+#
U_MULTI_SHIFT 554+# 9268
U_N 562+# 1340 1552 1910 1911 3103 3104 3624 3625 3854 3855 3980
3981 3983 3984 4070 4071 4072 4073 4159 4160 4162 4163 4244
4245 4246 4247 4324 4325 4404 4405 4486 4487 4488 4489 4600
4601 4602 4603 4604 4717 4718 4719 4830 4831 4832 4833 4834
4835 4836 4837 4838 4839 4931 4932 5032 5034 5035 5036 5037
5196 5198 5199 5200 5201 5363 5365 5366 5520 5522 5524 5526
5528 5530 5532 5534 5536 5538 5540 5629 5630 5632 5633 5634
5748 5750 5751 5856 5858 5859 6021 6023 6024 6194 6198 6200
6201 6341 6343 6346 6347 6467 6469 6470 6471 6472 6583 6585
6586 6587 6588 6682 6684 6685 6686 6687 6786 6788 6789 6790
6791 6792 6793 6859 6861 6863 6864 6865 6866 6945 6947 6948
6949 6950 7054 7055 7056 7058 7059 7060 7061 7063 7064 7227
7229 7230 7351 7353 7354 7355 7356 7511 7513 7514 7515 7516
7662 7664 7665 7666 7667 7803 7804 7805 7806 7982 7983 7989
7990 7991 8457 8459 8460 8583 8585 8586 8713 8715 8716 8717
8718 8856 8858 8859 8860 8861 9005 9090 9091 9094 9507 9508
9509 9510
U_NO_CLKL 393+# 1576 7045 7049 7051
U_NO_CLKR 406+# 1576 3763 7046 7050 7053 7062
U_RAM_AC 354+# 1328 1329 1330
U_RAM_AC_FN 355+#
U_RAM_N 359+# 9090 9091
U_RAM_RAM 358+#
U_RAM_VMA 357+#
U_RAM_XR 356+# 9095
U_RAM 351+# 354+ 355+ 356+ 357+ 358+ 359+
U_RSRC 282+# 286+ 287+ 288+ 289+ 290+ 291+ 292+ 293+
U_RSRC_0A 290+# 4600
U_RSRC_0B 289+#
U_RSRC_0Q 288+#
U_RSRC_AB 287+#
U_RSRC_AQ 286+#
U_RSRC_D0 293+# 1343
U_RSRC_DA 291+# 7052 7226 7659 7660 8582
U_RSRC_DQ 292+#
U_SCAD 568+# 571+ 572+ 573+ 574+ 575+ 576+ 577+ 578+
U_SCADA 581+# 584+ 585+ 586+ 587+ 588+ 589+ 590+ 591+
U_SCADA_BYTE1 587+# 2650 2655
U_SCADA_BYTE2 588+# 2649 2654
U_SCADA_BYTE3 589+# 2648 2653
U_SCADA_BYTE4 590+# 2647 2652
U_SCADA_BYTE5 591+# 2646 2651
U_SCADA_PTR44 586+# 2544 2546
U_SCADA_SC 584+# 2449 3486 3487 3488
U_SCADA_SN 585+# 1338 1339 2293 2294 2295 2371 2372 2805 2807 2905 2906
3002 3003 3101 3102 3105 3385 3388 9165 9166 9266 9267
U_SCADB 594+# 597+ 598+ 599+ 600+
U_SCADB_EXP 598+# 3101 3102 3105
U_SCADB_FE 597+# 2805 2807 3385 3388 3486 3487 3488
U_SCADB_SHIFT 599+# 2905 2906
U_SCADB_SIZE 600+# 3002 3003
U_SCAD_A 578+# 1338 1339 2449 2544 2546 2646 2647 2648 2649 2650 2651
2652 2653 2654 2655 9165 9166 9266 9267
U_SCAD_ADD 575+# 3486
U_SCAD_AND 576+# 3385 3388
U_SCAD_A_DEC 577+# 2293 2294 2295
U_SCAD_A_MUL2 571+# 2371 2372
U_SCAD_OR 572+# 2805 2807 2905 2906 3002 3003 3101 3102 3105
U_SCAD_SUBB 573+# 3488
U_SCAD_SUB 574+# 3487
U_SET_GENL 399+ 619+ 652+#
U_SET_GENR 412+ 625+ 653+#
U_SET_RSRC 284+ 613+ 651+#
U_SET 284+ 399+ 412+ 613+ 619+ 625+ 636+ 662+#
U_SHSTYLE 458+# 461+ 462+ 463+ 464+ 465+ 466+ 467+ 468+
U_SHSTYLE_ASHC 465+#
U_SHSTYLE_DIV 467+#
U_SHSTYLE_LSHC 466+#
U_SHSTYLE_NORM 461+#
U_SHSTYLE_ONES 463+#
U_SHSTYLE_ROT 464+#
U_SHSTYLE_ROTC 468+#
U_SHSTYLE_ZERO 462+#
U_SKIP 491+# 494+ 495+ 496+ 497+ 498+ 499+ 500+ 501+ 502+ 503+ 504+
505+ 506+ 507+ 508+ 509+ 510+ 511+ 512+ 513+ 514+ 515+ 516+
517+
U_SKIP_1_MS 517+#
U_SKIP_AC0 501+#
U_SKIP_ADEQ0 512+# 1910 1912 2006 2009 2103 2106 3189 3192 3286 3294 3984
4160 4164 6472 6588 6688 6793 6866 6950 7065 7356 7516 7667
7951 7957 7963 7969 7975 7981 7989 8314 8718 8861 9095 9419
9507 9509
U_SKIP_ADLEQ0 497+# 3763
U_SKIP_ADREQ0 498+#
U_SKIP_CONTINUE 516+#
U_SKIP_CRY0 496+#
U_SKIP_CRY1 509+#
U_SKIP_CRY2 504+#
U_SKIP_DP0 505+# 1538 1539
U_SKIP_DP18 506+#
U_SKIP_EXECUTE 514+#
U_SKIP_FPD 500+#
U_SKIP_INT 502+# 1566
U_SKIP_IOLGL 494+#
U_SKIP_IOT 507+#
U_SKIP_IO_BUSY 515+#
U_SKIP_JFCL 508+#
U_SKIP_KERNEL 499+#
U_SKIP_LE 503+#
U_SKIP_LLE 495+#
U_SKIP_SC 513+# 9167
U_SKIP_TRAP_CYC 511+#
U_SKIP_TXXX 510+#
U_SN 603+# 1338 1339 2293 2294 2295 2371 2372 2807 2905 2906 3002
3003 3101 3102 3105 3385 3388 9165 9166 9266 9267
U_SPEC 419+# 422+ 423+ 424+ 425+ 426+ 427+ 428+ 429+ 430+ 431+ 432+
433+ 434+ 435+ 436+ 437+ 438+ 439+ 440+ 441+ 442+ 443+ 444+
445+
U_SPEC_APRFLAGS 432+# 7949 7967 8310
U_SPEC_APR_EN 434+# 1551 1569 1571 8311
U_SPEC_ASHOV 441+#
U_SPEC_CLRCLK 423+# 1553
U_SPEC_CLRCSH 433+# 6790
U_SPEC_CLRIOBSY 425+#
U_SPEC_CLRIOLAT 424+#
U_SPEC_EXPTST 442+#
U_SPEC_FLAGS 443+# 1552 5519 5521 5523 5525 5527 5529 5531 5533 5535 5537
5539 5541
U_SPEC_INHCRY18 438+#
U_SPEC_LDACBLK 444+# 1543 9089
U_SPEC_LDINST 445+#
U_SPEC_LDPAGE 426+# 5032 5196 5363 5629 5630 5748 5856 6021 6194 6341 6344
6467 6583 6682 6786 6859 6861 6945 7056 7227 7351 7511 7662
8457 8583 8713 8856
U_SPEC_LDPI 440+# 1554
U_SPEC_LDPXCT 428+# 5516 9002 9003 9092
U_SPEC_LOADIR 439+# 1544 4717 4718 4830 4831
U_SPEC_LOADXR 431+# 9094
U_SPEC_MEMCLR 435+# 1555 4720
U_SPEC_N 422+#
U_SPEC_NICOND 427+#
U_SPEC_PREV 430+# 5522
U_SPEC_PXCT_OFF 437+# 5517 9004 9093
U_SPEC_SWEEP 436+# 3624 3625 3854 3855 6343
U_SPEC_WAIT 429+#
U_T 520+# 9266 9267 9268
VAL 4313 4342# 4343 4348 4393 4422# 4423 4428 4845 4872# 4873 4880
4918 4950# 4951 4954 4959# 4960 4963
VIR_PAG 7109 7111 7112 7113 7255 7257 7258 7259 7339 7374 7375 7693
7695 7696 8608 8610 8611 8612
VMA 5016 5056# 5063 5064 5103# 5169 5216# 5221 5222 5235# 5239 5240
5341 5386# 5391 5401# 5402 5404 5486 5565# 5566 5567 5615 5645#
5646 5734 6431 6487# 6488 6567 6602# 6603 6604 6607 6608 6658
6700# 6702 6722# 6724 6731 6732 6775 7028 7112# 7204 7258# 7332
7375# 7392 7393 7415 7638 7696# 8416 8482# 8483 8567 8611# 8681
8736# 8737 8738 8842 8877# 8878 8879 8881 8885 8886 8887
VMA_EASY_MASK 3630# 3660 3860# 3888
VMA_EASY_VALU 3632# 3639 3862# 3876
VMA_ERROR_FIELD 3641 3671 3692 3866 3899 3913
VMA_INFO 5347 5386 5401
VMA_PREV 8970 9030# 9031 9037
V_AC_DBM 1329# 2005 2007 2102 2104 2544 2546 2646 2647 2648 2649 2650
2651 2652 2653 2654 2655 2905 2906 3002 3003 3101 3102 3105
3188 3190 3761 3762
V_AC_DP 1328# 1545 1549 3979 3982 4158 4161
V_CHK 1345# 7806
V_DP_D 1333# 1546 1550 1567 1910 1911 2006 2008 2103 2105 2199 2200
2293 2294 2295 2371 2372 2449 2547 2656 2805 2807 2907 3004
3103 3104 3106 3189 3191 3280 3281 3282 3283 3284 3288 3289
3290 3291 3292 3385 3388 3486 3487 3488 3626 3763 3856 3984
4160 4163 4486 4601 4602 4603 4604 4720 5516 5518 5519 5521
5523 5525 5527 5529 5531 5533 5535 5537 5539 5541 6472 6588
6687 7356 7516 7667 8718 8861 9006 9095
V_DP_N 1342# 1570 1571 4323 4403 4929 5030 5031 5033 5195 5197 5362
5364 5627 5628 5631 5747 5749 5857 6020 6022 6196 6340 6342
6345 6466 6468 6582 6584 6681 6683 6784 6785 6787 6857 6858
6860 6862 6944 6946 7044 7047 7224 7225 7350 7352 7510 7512
7661 7663 7949 7955 7961 7967 7973 7979 7987 8310 8311 8312
8456 8458 8580 8581 8712 8714 8855 8857 9421 9511
V_DP_NN 1341# 7045 7046 7048 7049 7050 7051 7053 7062 9089
V_DP_Q 1334# 1538 1539 3105
V_DP_R 1337# 7054 7055 7056 7057 7058 7060 7063 7227 7228 7229 7351
7353 7355 7511 7513 7515 7662 7664 7666 7801 8583 8584 8585
V_DP_T0 1335# 3285 3293 4324 4404 4932 5032 5034 5036 5196 5198 5200
5363 5365 5629 5630 5632 5633 5748 5750 6021 6023 6198 6200
6341 6346 6467 6469 6471 6583 6585 6587 6682 6684 6685 6686
6786 6790 6859 6863 6945 6947 6949 7804 8457 8459 8713 8715
8717 8856 8858 8860
V_DP_T1 1336# 6788 6792 6861 6865
V_DP__1 1332# 1545 1554 2007 2104 2546 2651 2652 2653 2654 2655 2906
3003 3102 3190 3625 3762 3854 3979 4158 4245 4325 4405 5856
5858 6470 6586 6789 6864 6948 7354 7514 7665 7982 8716 8859
9003 9004 9091 9092
V_DP_0 1331# 1543 1544 1551 1552 1555 1568 1569 2005 2102 2544 2646
2647 2648 2649 2650 2905 3101 3188 3624 3761 3855 3980 3981
3982 3983 4070 4071 4072 4159 4161 4162 4244 4246 4247 4487
4488 4489 4719 4832 4833 4834 4835 4836 4837 4838 4839 4931
5035 5199 5366 5517 5634 5751 5859 6024 6194 6195 6197 6199
6201 6343 6344 6347 6791 7059 7230 7803 7805 7990 8460 8586
9002 9090 9093 9094
V_D_AC 1330# 1546 1550 2006 2008 2103 2105 2547 2656 2907 3004 3106
3189 3191 3763
V_D_N 1340# 1341 1343 5516 5519 5521 5523 5525 5527 5529 5531 5533
5535 5537 5539 5541 7052 7226 7659 7660 8582
V_GEN 1344#
V_SCAD_0 1338# 2199 2447 2543 2803 2806 3188 3280 3281 3282 3283 3284
3386 3482 3483 3761
V_SCAD__1 1339# 2200 2448 2545 2804 3190 3288 3289 3290 3291 3292 3384
3387 3484 3485 3762
WAIT 759+ 9433 9453 9519
WRITE_USER 5654 5656 5659 5669
WRT100 793+
WRT102 794+
WRT103 795+
WRT104 796+
WRT105 797+
WRT106 798+
WRT107 799+
WRT110 800+
WRT111 801+
WRT112 802+
WRT113 803+
WRT114 804+
WRT115 805+
WRT116 806+
WRT204 807+
WRT205 808+ 8001 8120
WRT206 809+ 9289 9291
WRT210 810+
WRT212 811+ 1629 5562 5583
WR_CRAM 768+
X 419+ 420+ 448+ 449+ 458+ 459+ 471+ 472+ 491+ 492+ 520+ 521+
568+ 569+ 581+ 582+ 594+ 595+ 1320 1321 1337
X1 769+
X1A_AC 876+# 1000+
X1B_AC 877+# 1001+
XMIT_ADR 1179+#
XMIT_DATA 1178+#
Y 1321
ZORK 1347# 1387
TIME: 22 SEC.
CORE: 23K