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Trailing-Edge - PDP-10 Archives - klad_sources - klad.sources/msdpe.msg
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]1
[1
!	DIAGNOSTIC DIPATCH TEST
STIMULUS:
	TRIED TO LOAD ADDRESS 000, USING DIAG ADDRESS DISPATCH
	TEST FAILED, ABORT PROGRAM 
	CANT LOAD ANY MICROCODE
	ABORT....ABORT....ABORT....
RESPONSE:
!
]2
[1
!	2901'S TEST
STIMULUS:
	OUTPUT A 0 ONTO DP FROM THE 2901'S
	SKIP IF DP EQL TO 0
	J = 0
RESPONSE:
	DP WAS NOT A 0
!
]3
[1
!STIMULUS:
	LOAD THE VMA AND WRITE TO MEM WITH THE 
	SAME DATA (DP = 0 FROM A PORT)
RESPONSE:
	READ DATA FROM MEMORY
!
]4
[1
!	2901'S TEST
STIMULUS:
	WRITE ZERO INTO THE 2901'S Q REGISTER
	WRITE (-1) INTO THE 2901'S REGISTER 0 SELECTING DEST = \O0
	THEN OUTPUT THE CONTENTS OF REGISTER \S1 INTO MEM 0.\S2
RESPONSE:
	EXAMINE THE DATA FROM MEM 0
!
]5
[1
!	2901'S TEST
STIMULUS:
	LOAD THE 2901'S REGISTER \O0 WITH \U1
	FROM THE MAGIC # FIELD VIA DBUS
	THEN WRITE IT OUT TO MEM 0 THROUGH PORT A
RESPONSE:
	READ THE DATA FROM MEMORY
!
]6
[1
!	2901'S TEST
STIMULUS:
	LOAD THE 2901'S REGISTER 0 WITH \U0
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	THEN WRITE IT OUT TO MEM 0 THROUGH PORT B
RESPONSE:
	READ THE DATA FROM MEMORY
!
]7
[1
!	2901'S TEST
STIMULUS:
	LOAD THE 2901'S Q REGISTER WITH \U0
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	THEN WRITE IT OUT TO MEM 0 THROUGH PORT B
RESPONSE:
	READ THE DATA FROM MEM 0
!
]8
[1
!	2901'S TEST
STIMULUS:
	LOAD THE Q REGISTER WITH 252525252525
	WRITE A \U0 INTO THE 2901'S SELECTING DEST = \O1
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	THEN OUTPUT THE CONTENTS OF REGISTER \S2 INTO MEM 0.\S3
RESPONSE:
	EXAMINE THE DATA FROM MEM 0
!
]9
[1
!	2901'S TEST
STIMULUS:
	LOAD 2901'S REGISTER \O0 WITH \U1
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	SHIFT LEFT 3, SHIFT RIGHT 3
	THEN WRITE IT OUT TO MEM 0 THROUGH PORT B
RESPONSE:
	READ THE DATA FROM MEM 0
!
]10
[1
!	2901'S TEST
STIMULUS:
	LOAD 2901'S REGISTER \O0 WITH \U1
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	SHIFT RIGHT 3, SHIFT LEFT 3
	THEN WRITE IT OUT TO MEM 0 THROUGH PORT B
RESPONSE:
	READ THE DATA FROM MEM 0
!
]11
[1
!	2901'S TEST
STIMULUS:
	WRITE A \U0 INTO THE 2901'S REGISTER \S2 SELECTING DEST = \O1
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	THEN OUTPUT THE CONTENTS OF REGISTER \S2 INTO MEM 0.
RESPONSE:
	EXAMINE THE DATA FROM MEM 0
!
]12
[1
!	2901'S TEST
STIMULUS:
	LOAD 2901'S Q REGISTER WITH \U0
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	SHIFT LEFT 3, SHIFT RIGHT 3
	THEN WRITE IT OUT TO MEM 0 THROUGH PORT B
RESPONSE:
	READ THE DATA FROM MEM 0
!
]13
[1
!	2901'S TEST
STIMULUS:
	LOAD 2901'S Q REGISTER WITH \U0
	FROM THE MAGIC # FIELD VIA DBUS & DBM
	SHIFT RIGHT 3, SHIFT LEFT 3
	THEN WRITE IT OUT TO MEM 0 THROUGH PORT B
RESPONSE:
	READ THE DATA FROM MEM 0
!
]14
[1
!	ALU FUNC (R OR S) :
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
	FOR THE \S2 20 BITS OF THE 2901'S
	\S0    OR    \S1
	THEN WRITE THE DATA OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]15
[1
!	ALU FUNC (R + S) :
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
	FOR THE \S2 20 BITS OF THE 2901'S
	\S0    +    \S1
	THEN WRITE THE DATA OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]16
[1
!	ALU FUNC (S - R) :
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
	FOR THE \S2 20 BITS OF THE 2901'S
	\S0    -    \S1
	THEN WRITE OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]17
[1
!	ALU FUNC (R - S) :
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
	FOR THE \S2 20 BITS OF THE 2901'S
	\S0    -    \S1
	THEN WRITE THE DATA OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]18
[1
!	ALU FUNC (R AND S) :
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
	FOR THE \S2 20 BITS OF THE 2901'S
	\S0    AND    \S1
	THEN WRITE THE DATA OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]19
[1
!	2901'S FUNC TEST
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
		  _
	ALU FUNC (R AND S) :
	FOR THE \S2 20 BITS OF THE 2901'S
	_______
	\S0    AND    \S1
	THEN WRITE THE DATA OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]20
[1
!	ALU FUNC (R XOR S) :
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
	FOR THE \S2 20 BITS OF THE 2901'S
	\S0    XOR    \S1
	THEN WRITE THE DATA OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]21
[1
!	ALU FUNC (R XNOR S) :
	PASS A 0 AND -1 INTO THE 2901'S FROM THE 
	MAGIC # FIELD VIA DBUS & DBM
	FOR THE \S2 20 BITS OF THE 2901'S
	\S0    XNOR    \S1
	THEN WRITE THE DATA OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]22
[1
!	DP CRY1 FLAG TEST
STIMULUS:
	DPE1 DP SIGN IS \S0
	DPE2 DP 00 IS \S1
	DPE2 CARRY OUT IS \S0
	DPE9 DP CRY1 SHOULD BE \S1
	WE DO A SKIP IF DP CRY1 IS HI
RESPONSE:
	GET NXT CRAM ADRS
!
]23
[1
!STIMULUS:
	OUTPUT A 0 ON DP(DPE2 CARRY OUT IS LO)
	SKIP IF DPE2 CARRY OUT IS SET (SKIP = 31)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[2
!STIMULUS:
	OUTPUT A 0 ON DP(DPE2 CARRY 02 IS LO)
	SKIP IF DPE2 CARRY 02 IS SET (SKIP = 51)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[3
!STIMULUS:
	OUTPUT A 0 FROM 2901'S
	SKIP IF ADL SIGN (SKIP = 52)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[4
!STIMULUS:
	OUTPUT A 0 FROM 2901'S
	SKIP IF ADR SIGN (SKIP = 53)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[5
!STIMULUS:
	OUTPUT A -1 FROM 2901'S
	SKIP IF ADR SIGN (SKIP = 53)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[6
!STIMULUS:
	OUTPUT A -1 FROM 2901'S
	SKIP IF ADL SIGN (SKIP = 52)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[7
!STIMULUS:
	PASS -1 2901'S AND OUTPUT ON DP(DPE2 CARRY 02 IS HI)
	SKIP ON DPE2 CARRY 02
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[8
!STIMULUS:
	PASS -1 FROM 2901'S AND OUTPUT ON DP(DPE2 CARRY OUT IS HI)
	SKIP ON DPE2 CARRY OUT
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
]24
[1
!	DP CLKS TEST
STIMULUS:
	PUT 0 IN REGISTER 0
	THEN WRITE IT OUT TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[2
!	DP CLKS TEST
STIMULUS:
	PUT A 0 IN REGISTER 0
	TRY TO WRITE A -1 INTO REGISTER 0
	WITH DP HOLD L/R CLEARED 
	(IT SHOULDN'T WRITE)
	THEN WRITE IT OUT TO MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]25
[1
!	SHIFT TEST
STIMULUS:
	DID A LEFT SHIFT  7 TO REGISTER 0 
	WITH SPEC SELECT = 0 (SHSTYLE NORM)
	INITIAL DATA = 20000,,20000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 1
	SHIFT BOTH HALFS LEFT 3 WITH MULTI PRECISION SET
	SHIFT RIGHT HALF LEFT 3
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[2
!STIMULUS:
	DID A LEFT SHIFT  7 TO THE Q REGISTER 
	WITH SPEC SELECT = 0 (SHSTYLE NORM)
	INITIAL DATA = 20000,,20000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 1
	SHIFT BOTH HALFS LEFT 3 WITH MULTI PRECISION SET
	SHIFT RIGHT HALF LEFT 3
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[3
!STIMULUS:
	DID A LEFT SHIFT  7 TO THE Q REGISTER 
	WITH SPEC SELECT = 5 (SHSTYLE LSHC)
	INITIAL DATA = 20000,,20000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 4
	SHIFT RIGHT HALF LEFT 3
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[4
!STIMULUS:
	DID A LEFT SHIFT  7 TO REGISTER 0
	WITH SPEC SELECT = 5 (SHSTYLE LSHC)
	INITIAL DATA = 20000,,20000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 4
	SHIFT RIGHT HALF LEFT 3
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[5
!STIMULUS:
	DID A LEFT SHIFT  5 TO REGISTER 0
	WITH SPEC SELECT = 1 (SHSTYLE ZERO)
	INITIAL DATA = 200000,,200000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[6
!STIMULUS:
	DID A LEFT SHIFT  5 TO THE Q REGISTER 
	WITH SPEC SELECT = 1 (SHSTYLE ZERO)
	INITIAL DATA = 10000,,10000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[7
!STIMULUS:
	DID A LEFT SHIFT  5 TO THE Q REGISTER 
	WITH SPEC SELECT = 2 (SHSTYLE ONES)
	INITIAL DATA = 10000,,10000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[8
!STIMULUS:
	DID A LEFT SHIFT  5 TO REGISTER 0
	WITH SPEC SELECT = 2 (SHSTYLE ONES)
	INITIAL DATA = 200000,,200000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[9
!STIMULUS:
	DID A LEFT SHIFT  5 TO REGISTER 0
	WITH SPEC SELECT = 3 (SHSTYLE ROT)
	INITIAL DATA = 240000,,240000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM MEM
!
[10
!STIMULUS:
	DID A LEFT SHIFT  5 TO THE Q REGISTER 
	WITH SPEC SELECT = 3 (SHSTYLE ROT)
	INITIAL DATA = 40000,,40000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[11
!STIMULUS:
	DID A LEFT SHIFT  5 TO THE Q REGISTER 
	WITH SPEC SELECT = 4 (SHSTYLE ASHC)
	INITIAL DATA = 40000,,40000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[12
!STIMULUS:
	DID A LEFT SHIFT  5 TO REGISTER 0
	WITH SPEC SELECT = 4 (SHSTYLE ASHC)
	INITIAL DATA IN Q = 40000,,40000
	INITIAL DATA IN REGISTER 0 = 240000,,240000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[13
!STIMULUS:
	DID A LEFT SHIFT  5 TO REGISTER 0
	WITH SPEC SELECT = 7 (SHSTYLE ROTC)
	INITIAL DATA IN Q = 40000,,40000
	INITIAL DATA IN REGISTER 0 = 240000,,240000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[14
!STIMULUS:
	DID A LEFT SHIFT  5 TO THE Q REGISTER 
	WITH SPEC SELECT = 7 (SHSTYLE ROTC)
	INITIAL DATA IN Q = 40000,,40000
	INITIAL DATA IN REGISTER 0 = 240000,,240000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[15
!STIMULUS:
	DID A LEFT SHIFT  8 TO THE Q REGISTER 
	WITH SPEC SELECT = 6 (SHSTYLE DIV)
	INITIAL DATA IN Q = 10000,,10000
	INITIAL DATA IN REGISTER 0 = 210000,,210000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 8
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[16
!STIMULUS:
	DID A LEFT SHIFT  8 TO REGISTER 0
	WITH SPEC SELECT = 6 (SHSTYLE DIV)
	INITIAL DATA IN Q = 10000,,10000
	INITIAL DATA IN REGISTER 0 = 210000,,210000
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS LEFT 8
	THEN OUTPUT THE DATA FROM REGISTER R 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
]26
[1
!	SHIFT TEST
STIMULUS:
	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 0 (SHSTYLE NORM)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[2
!STIMULUS:
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 0 (SHSTYLE NORM)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[3
!STIMULUS:
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 2 (SHSTYLE ONES)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[4
!STIMULUS:
	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 2 (SHSTYLE ONES)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[5
!	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 3 (SHSTYLE ROT)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[6
!STIMULUS:
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 3 (SHSTYLE ROT)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[7
!STIMULUS:
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 4 (SHSTYLE ASHC)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[8
!STIMULUS:
	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 4 (SHSTYLE ASHC)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[9
!STIMULUS:
	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 5 (SHSTYLE LSHC)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[10
!	STIMULUS :
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 5 (SHSTYLE LSHC)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[11
!STIMULUS:
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 6 (SHSTYLE DIV)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[12
!STIMULUS:
	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 6 (SHSTYLE DIV)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[13
!STIMULUS:
	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 7 (SHSTYLE ROTC)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[14
!STIMULUS:
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 7 (SHSTYLE ROTC)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y1 = DPE1 DP SIGN SMEAR, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[15
!STIMULUS:
	DID A RIGHT SHIFT 5 TO THE Q REGISTER 
	WITH SPEC SELECT = 1 (SHSTYLE ZERO)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y0 = DPE1 DP SIGN H, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM THE Q REGISTER TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[16
!STIMULUS:
	DID A RIGHT SHIFT 5 TO REGISTER 0
	WITH SPEC SELECT = 1 (SHSTYLE ZERO)
	INITIAL DATA IN REGISTERS Q & 0  = 10,,200002
	(Y0 = DPE1 DP SIGN H, IS ALSO SET IN BOTH REGISTERS)
	THE FOLLOWING WAS CLOCKED :
	SHIFT BOTH HALFS RIGHT 5
	THEN OUTPUT THE DATA FROM REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
]27
[1
!	DP CRY TEST
STIMULUS:
	PUT 700000 IN REGISTER 0
	THEN ADD THE CONTENTS OF REGISTER 0 TO ITSELF 3 TIMES
	FINALLY OUTPUT THE CONTENTS OF REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[2
!STIMULUS:
	PUT 700000 IN REGISTER 0
	THEN ADD THE CONTENTS OF REGISTER 0 TO ITSELF ONCE
	THEN ADD THE CONTENTS OF REGISTER 0 TO ITSELF AGAIN WITH SPEC FIELD = 40 (CARRY INHIBIT)
	THEN ADD THE CONTENTS OF REGISTER 0 TO ITSELF A THIRD TIME
	FINALLY OUTPUT THE CONTENTS OF REGISTER 0 TO MEM
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
]28
[1
!	DP TEST
STIMULUS:
	OUTPUT \O2 FROM BOTH HALF OF THE 2901'S
	THEN SKIP IF \S1 = 0
	THE CURRENT J FIELD IS 0
	IT SHOULD \S0SKIP
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
]29
[1
!	BYTE DISP LOGIC TEST (DPE3)
STIMULUS:
	PASS A DATA WORD FROM THE MAGIC # FIELD (\O0)
	TO BOTH HALFS OF DP VIA DBUS.
	DO A BYTE DISPATCH
	EXAMINE NXT CRAM ADRS
RESPONSE:
!
]30
[1
!	DBUS TEST
STIMULUS:
	DBUS SELECT 0 GROUND PINS (DPE3 & 4)
	START A MEM CYCLE & LOAD THE VMA WITH 0
	FINISH MEM CYCLE AND OUTPUT DATA FROM DBUS (DBUS SELECT = 0)
	INTO MEM VIA DP
	ALL TESTED PINS SHOULD BE LO
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[2
!STIMULUS:
	DBUS PARITY SELECT 0
	CHECK \S0 HALF OF DBUS PAR WITH DBUS SELECT = 0
	READ BACK REGISTER 101 AND CHK PARITY BIT
	DBUS SELECT 0 PARITY INPUTS SHOULD BE GROUNDED
	PARITY ERROR SHOULD NEVER OCCUR
RESPONSE:
!
]31
[1
!	DBUS TEST
STIMULUS:
	DBUS MIX'S SELECT 1 (DPE3 & 4)
	LOAD THE 2901'S REGISTER 0 WITH A \O0
	OUTPUT REGISTER 0 ONTO DP AND WRITE IT BACK TO 
	REGISTER 1 FROM DBUS (DBUS SELECT = 1)
	START AND FINISH A MEM CYCLE OUTPUTING THE CONTENTS 
	OF REGISTER 1 INTO PHYSICAL MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]32
[1
!	10 BIT VMA COPY TEST
STIMULUS:
	10 BIT VMA COPY TEST (DPE5)
	DEPOSIT \O0 IN MEM \O1
	START A MEM CYCLE AND LOAD THE VMA WITH A \O1
	FINISH MEM CYCLE AND OUTPUT DBUS TO MEM VIA DP (DBUS SELECT = 0)
	DBUS SHOULD INCLUDE 10 BIT VMA COPY (26-35)
RESPONSE:
!
]33
[1
!	DISP ON OUTPUT OF DP
STIMULUS:
	DID A DISP = \O1
	DP = \U0, CRAM J = 0
	WE GET NXT CRAM ADRS 
RESPONSE:
!
]34
[1
!	BUS PI TEST
STIMULUS:
	DP 33 - 35 = \O0
	DPE5 SPEC/APR EN IS \S1
	DPMB APR INT REQ IS \S2
	READ THE 8080'S REGISTER 101
	(BITS 7-1 CONTAIN BUS PI LEVEL 1-7)
RESPONCE:
!
]35
[1
!	PI SOFT TEST
STIMULUS:
	DPEB PI ON IS \S0
	BOTH HALFS OF DP CONTAIN \O1
	LOAD PI SYSTEM, THEN READ PI NEW THROUGH THE DBUS OUT TO MEM
RESPONSE:
	EXAMINE THE CONTENTS OF THE DBUS (BITS 19-21 CONTAIN PI NEW)
!
]36
[1
!	PI ACTIVE TEST
STIMULUS:
	FORCE BUS PI LEVEL TO \O0
	LOAD THE PI SYSTEM WITH DP = \S1
	READ BACK PI NEW OUT TO MEM THROUGH THE DBUS
	EXAMINE MEM (BITS 19 - 21 COJNTAIN PI NEW)
RESPONCE:
!
]37
[1
!	PI CURRENT TEST
STIMULUS:
	DPMC PI XMIT IS \S1
	LOAD THE PI SYSTEM \S2
	WITH RIGHT HALF OF DP = \O0
	SINGLE STEP THE MAIN CLOCK
	EXAMINE THE 8080'S REGISTER 2
	BITS (14 - 17) CONTAIN THE TRNCVR OUTPUT
RESPONSE:
!
]38
[1
!	PI COMPARE TEST
STIMULUS:
	LOAD THE PI SYSTEM WITH DP = \S0
	SKIP ON DPEB INTERRUPT REQ (J = 4)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
]39
[1
!STIMULUS:
	P.C. FLAGS TEST
	LOAD THE FLAGS FROM DP (DP LEFT = 0)
	READ THE FLAGS INTO REGISTER 0 OF THE 2901'S
	OUTPUT REGISTER 0 INTO PHYSICAL MEM 0
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[2
!STIMULUS:
	P.C. FLAGS TEST
	LOAD THE FLAGS FROM DP (DP LEFT = 0)
	LOOP FLAGS BACK INTO THE FLOPS (MIX SELECT = 0)
	HOLD USER IS SET (DBM 05)
	READ THE FLAGS INTO REGISTER 0 OF THE 2901'S
	OUTPUT REGISTER 0 INTO PHYSICAL MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[3
!STIMULUS:
	P.C. FLAGS TEST
	LOAD THE FLAGS WITH 0
	LOAD THE FLAGS WITH DP LEFT = 774740
	READ THE FLAGS INTO REGISTER 0 OF THE 2901'S
	OUTPUT REGISTER 0 INTO PHYSICAL MEM 0
	(BIT 15 IS CLEAR ON DBM FLAGS SHOULD NOT LOAD FROM DP)
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[4
!STIMULUS:
	P.C. FLAGS TEST
	LOAD THE FLAGS FROM DP (DP LEFT = 774740)
	READ THE FLAGS INTO REGISTER 0 OF THE 2901'S
	OUTPUT REGISTER 0 INTO PHYSICAL MEM 0
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[5
!STIMULUS:
	P.C. FLAGS TEST
	LOAD THE FLAGS FROM DP (DP LEFT = 774740)
	LOOP FLAGS BACK INTO THE FLOPS (MIX SELECT = 0)
	HOLD USER FLAG IS SET (DBM 05)
	READ THE FLAGS INTO REGISTER 0 OF THE 2901'S
	OUTPUT REGISTER 0 INTO PHYSICAL MEM 0
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[6
!STIMULUS:
	P.C. FLAGS TEST
	LOAD THE FLAGS FROM DP (DP LEFT = 774740)
	LOOP FLAGS BACK INTO THE FLOPS (MIX SELECT = 0)
	READ THE FLAGS INTO REGISTER 0 OF THE 2901'S
	OUTPUT REGISTER 0 INTO PHYSICAL MEM 0
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
]40
[1
!	JFCL LOGIC TEST (P.C. FLAGS)
STIMULUS:
	DPE9 \S0
	DPEA \S1
	DPE9 JFCL EN IS \S2
	ALL OTHER AC & FLAG INPUTS TO THE JFCL GATES ARE LO
	SKIP IF JFCL (CURRENT J FIELD IS 4)
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[2
!STIMULUS:
	JFCL LOGIC TEST (P.C. FLAGS)
	DPE9 OV,CRY0,CRY1 & FOV FLAGS ARE HI
	DPEA AC 9,10,11 & 12 ARE HI
	DPE9 JFCL EN IS HI
	LOOP FLAGS BACK INTO THE FLOPS (MIX SELECT = 0)
	READ THE FLAGS INTO REGISTER 0 OF THE 2901'S
	OUTPUT REGISTER 0 INTO PHYSICAL MEM 0
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]41
[1
!STIMULUS:
	P.C. FLAGS TEST
	DBM 03 IS CLEAR
	DBM 04 & 07 ARE SET
	DPE2 CARRY OUT IS SET
	DPE9 DP CRY1 IS SET 
	DPE9 CARRY FLAGS IS SET
	OUTPUT THE FLAGS INTO MEMORY VIA DBUS & DP
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[2
!STIMULUS:
	P.C. FLAGS TEST
	DBM 03 & 04 ARE SET
	DBM 07 IS CLEAR
	DPE2 CARRY OUT IS CLEAR
	DPE9 DP CRY1 IS CLEAR 
	DPE9 CARRY FLAGS IS SET
	OUTPUT THE FLAGS INTO MEMORY VIA DBUS & DP
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[3
!STIMULUS:
	P.C. FLAGS TEST
	DBM 03,04 & 07 ARE CLEAR
	DPE2 CARRY OUT IS SET
	DPE9 DP CRY1 IS SET 
	DPE9 CARRY FLAGS IS CLEAR
	OUTPUT THE FLAGS INTO MEMORY VIA DBUS & DP
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]42
[1
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV,TRAP 1,FOV & NO DIV FLAGS FROM DBM
	DBM BITS 00,01,02 & 08 ARE HI
	DPE9 SPEC/PC FLAGS IS HI
	WRITE P.C. FLAGS OUT TO MEM VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[2
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV,TRAP 1,FOV & NO DIV FLAGS FROM DBM
	DBM BITS 00,01,02 & 08 ARE LO
	DPE9 SPEC/PC FLAGS IS HI
	WRITE P.C. FLAGS OUT TO MEM VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[3
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV,TRAP 1 & FOV FLAGS FROM DBM
	DBM BITS 00,01 & 08 ARE HI
	DPE9 SPEC/PC FLAGS IS LO
	WRITE P.C. FLAGS OUT TO MEM VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]43
[1
!STIMULUS:
	P.C. FLAGS TEST
	LOADS FLAGS FROM OUTPUT OF SCAD (00,01)
	SCAD(00,01) BITS ARE LO
	DPE9 SPEC/EXP TEST IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[2
!STIMULUS:
	P.C. FLAGS TEST
	LOADS FLAGS FROM OUTPUT OF SCAD (00,01)
	SCAD 00 & 01 BITS ARE HI
	DPE9 SPEC/EXP TEST IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[3
!STIMULUS:
	P.C. FLAGS TEST
	LOADS FLAGS FROM OUTPUT OF SCAD (00,01)
	SCAD(00,01) BITS ARE HI
	DPE9 SPEC/EXP TEST IS LO
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]44
[1
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP ASH TEST
	DP (01,02) BITS ARE LO
	DPE9 SPEC/ASH TEST IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[2
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP ASH TEST
	DP (01,02) BITS ARE HI
	DPE9 SPEC/ASH TEST IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[3
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP ASH TEST
	DP 01 IS HI
	DP 02 IS LO
	DPE9 SPEC/ASH TEST IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[4
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP ASH TEST
	DP 01 IS LO
	DP 02 IS HI
	DPE9 SPEC/ASH TEST IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[5
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP ASH TEST
	DP 01 & 02 ARE HI
	DPE9 SPEC/ASH TEST IS LO
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[6
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP OVERFLOW
	DPE9 DP OVERFLOW IS HI
	DPE9 CARRY FLAGS IS LO
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[7
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP OVERFLOW
	DPE9 DP OVERFLOW IS HI
	DPE9 CARRY FLAGS IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[8
!STIMULUS:
	P.C. FLAGS TEST
	LOAD OV & TRAP 1 FROM DP OVERFLOW
	DPE9 DP OVERFLOW IS LO
	DPE9 CARRY FLAGS IS HI
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]45
[1
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	-DPE9 USER FLAG H IS SET
	DPE1 DP 06 IS SET
	DPE9 LOAD FLAGS H IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD SET WHEN FLAGS ARE LOADED
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[2
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	-DPE9 USER FLAG H IS SET
	DPE1 DP 06 IS SET
	DPE9 LOAD FLAGS H IS CLEAR
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD CLEAR WHEN FLAGS ARE LOADED
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[3
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	-DPE9 USER FLAG H IS SET
	DPE1 DP 06 IS CLEAR
	DPE9 LOAD FLAGS H IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD CLEAR WHEN FLAGS ARE LOADED
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[4
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	-DPE9 USER FLAG H IS CLEAR
	DPE1 DP 06 IS SET
	DPE9 LOAD FLAGS H IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD CLEAR WHEN FLAGS ARE LOADED
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[5
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD SET WHEN FLAGS ARE LOADED
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[6
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS CLEAR
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD CLEAR WHEN FLAGS ARE LOADED
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[7
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS CLEAR
	DPE1 DP 09 IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD CLEAR WHEN FLAGS ARE LOADED
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[8
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD SET WHEN FLAGS ARE LOADED
	WE LOAD THE FLAGS AGAIN WITH -DPE9 LOAD FLAGS H CLEAR
	THIS SHOULD CLEAR USER I/O FLAG
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[9
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD SET WHEN FLAGS ARE LOADED
	WE LOAD THE FLAGS AGAIN WITH -DPE9 LOAD FLAGS H SET
	THIS SHOULD SET AGAIN  USER I/O FLAG
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[10
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS CLEAR
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD CLEAR WHEN FLAGS ARE LOADED
	WE LOAD THE FLAGS AGAIN WITH -DPE9 LOAD FLAGS H SET
	THIS SHOULD CLEAR AGAIN USER I/O FLAG
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[11
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD SET WHEN FLAGS ARE LOADED
	WE LOAD THE FLAGS AGAIN WITH DPE9 LOAD FLAGS H,DP 06 & DBM 05 SET
	THIS SHOULD SET AGAIN USER I/O FLAG
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[12
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD SET WHEN FLAGS ARE LOADED
	WE LOAD THE FLAGS AGAIN WITH DPE9 LOAD FLAGS H & DP 06 ARE SET, DBM 05 IS CLEAR
	THIS SHOULD CLEAR USER I/O FLAG
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[13
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS CLEAR
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD CLEAR WHEN FLAGS ARE LOADED
	WE LOAD THE FLAGS AGAIN WITH DPE9 LOAD FLAGS H,DP 06 & DBM 05 SET
	THIS SHOULD CLEAR AGAIN USER I/O FLAG
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
[14
!STIMULUS:
	P.C. FLAGS TEST (USER I/O FLAG)
	DPE9 USER FLAG H IS SET
	DPE1 DP 09 IS SET
	ALL OTHER FLAGS AND FLAG INPUTS ARE CLEAR
	USER I/O FLAG SHOULD SET WHEN FLAGS ARE LOADED
	WE LOAD THE FLAGS AGAIN WITH DPE9 LOAD FLAGS H & DBM 05 ARE SET, DP 06 IS CLEAR
	THIS SHOULD CLEAR USER I/O FLAG
	WRITE THE FLAGS OUT TO MEM 0 VIA DBUS & DP (DBUS SELECT = 0)
RESPONSE:
	EXAMINE DATA FROM MEM 0
!
]46
[1
!STIMULUS:
	SET DPEB TRAP EN
	SET CSL4 TRAP EN
	DPE9 TRAP 1 FLAG IS CLEAR
	DPE9 TRAP 2 FLAG IS CLEAR
	WE DO A NICOND DISP
	CURRENT J FIELD = 0
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[2
!STIMULUS:
	SET DPEB TRAP EN
	SET CSL4 TRAP EN
	DPE9 TRAP 1 FLAG IS SET
	DPE9 TRAP 2 FLAG IS CLEAR
	WE DO A NICOND DISP
	CURRENT J FIELD = 0
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[3
!STIMULUS:
	SET DPEB TRAP EN
	SET CSL4 TRAP EN
	DPE9 TRAP 1 FLAG IS CLEAR
	DPE9 TRAP 2 FLAG IS SET
	WE DO A NICOND DISP
	CURRENT J FIELD = 0
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[4
!STIMULUS:
	SET DPEB TRAP EN
	SET CSL4 TRAP EN
	DPE9 TRAP 1 FLAG IS SET
	DPE9 TRAP 2 FLAG IS SET
	WE DO A NICOND DISP
	CURRENT J FIELD = 0
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[5
!STIMULUS:
	CLEAR DPEB TRAP EN
	SET CSL4 TRAP EN
	DPE9 TRAP 1 FLAG IS SET
	DPE9 TRAP 2 FLAG IS SET
	WE DO A NICOND DISP
	CURRENT J FIELD = 0
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
]47
[1
!STIMULUS:
	LOAD INSTRUCTION REGISTER WITH A \O4
	EXECUTE THE FOLOWING:
		SKIP ON AC0 (SKIP = 36)
		DISP ON XR=0, JRST,0 & INDIRECT BIT (DISP = 66)
	THEN EXAMINE NXT CRAM ADRS. IT SHOULD BE:
	NXT ADRS = CRAM J + JRST,0 + INDIRECT BIT + XR=0 + AC=0
		 =  0000  +   \S0   +      \S1      +  \S2  +  \S3  
RESPONSE:
!
]48
[1
!STIMULUS:
	LOAD FPD FLAG WITH A 0 FROM DP
	SKIP IF FPD FLAG IS SET
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[2
!STIMULUS:
	LOAD USER FLAG WITH A 0 FROM DP
	SKIP IF USER FLAG IS CLEAR
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[3
!STIMULUS:
	LOAD USER I/O FLAG WITH A 0 FROM DP CONDITIONALLY
	SKIP IF USER I/O FLAG IS SET
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[4
!STIMULUS:
	LOAD USER FLAG WITH A 1 FROM DP
	SKIP IF USER FLAG IS CLEAR
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[5
!STIMULUS:
	LOAD USER I/O FLAG WITH A 1 FROM DP CONDITIONALLY
	SKIP IF USER I/O FLAG IS SET
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[6
!STIMULUS:
	LOAD FPD FLAG WITH A 2 FROM DP
	SKIP IF FPD FLAG IS SET
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
]49
[1
!	PARITY LOGIC TEST ON DPE3,4
STIMULUS:
	OUTPUT A \O0 ON THE \S1 HALF OF THE DBUS
	CHECK \S1 HALF OF DBUS PARITY
	READ 8080 REGISTER 100 AND VERIFY DP PARITY BIT
	IT SHOULD BE SET FOR CORRECT EVEN PARITY OUTPUT
	AND CLEAR FOR CORRECT ODD PARITY OUTPUT
	DPE3 & 4 DBUS PAR PROPEGATED FROM MEMORY BUS PARITY ARE BOTH LO
RESPONSE:
!
[2
!	PARITY LOGIC TEST ON DPE3,4
STIMULUS:
	OUTPUT A \O0 ON THE \S1 HALF OF THE DBUS
	CHECK \S1 HALF OF DBUS PARITY
	READ 8080 REGISTER 100 AND VERIFY DP PARITY BIT
	IT SHOULD BE CLEAR FOR CORRECT EVEN PARITY OUTPUT
	AND SET FOR CORRECT ODD PARITY OUTPUT
	DPE3 & 4 DBUS PAR PROPEGATED FROM MEMORY BUS PARITY ARE BOTH HI
RESPONSE:
!
[3
!	PARITY LOGIC TEST ON DPE3,4
STIMULUS:
	OUTPUT A \O0 ON BOTH HALFS OF THE DBUS
	CHCK BOTH HALFS OF DBUS PARITY
	DPE3 & 4 DBUS PAR PROPEGATED FROM MEMORY BUS PARITY ARE BOTH HI
	THIS WILL CAUSE A DP PARITY ERROR
	NOW WE DO A MASTER RESET THIS SHOULD CLEAR THE CONDITION
	READ 8080 REGISTER 100 AND VERIFY DP PARITY BIT
RESPONSE:
!
[4
!	OUTPUT A \O0 ON BOTH HALFS OF THE DBUS
	DON'T CHCK  EITHER HALF OF DBUS PARITY
	DPE3 & 4 DBUS PAR PROPEGATED FROM MEMORY BUS PARITY ARE BOTH HI
	READ 8080 REGISTER 100 AND VERIFY DP PARITY BIT
RESPONSE:
!
]50
[1
!	DP PARITY TEST
STIMULUS:
	WRITE INTO THE 2901'S SELECTING DEST = 1, WITH PARITY ODD 
	HI FOR BOTH HALFS. ENABLE BOTH HALFS OF DP PARITY.DP B ADRS = \O1
	THEN OUTPUT 0 ON DP, PASS IT THROUGH THE DBUS CHK \S0 HALF
	OF DBUS PARITY.THIS WILL FORCE A BAD PARITY ON \S0 HALF.
	EXAMINE THE 8080 REGISTER 100 AND VERIFY DP PARITY BIT.
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[2
!	DP PARITY TEST
STIMULUS:
	WRITE INTO THE 2901'S SELECTING DEST = 1, WITH PARITY ODD 
	LO FOR BOTH HALFS. ENABLE BOTH HALFS OF DP PARITY.DP B ADRS = \O1
	THEN OUTPUT 0 ON DP, PASS IT THROUGH THE DBUS CHK \S0 HALF
	OF DBUS PARITY.EXAMINE THE 8080 REGISTER 100 AND VERIFY DP PARITY BIT.
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[3
!	DP PARITY TEST
STIMULUS:
	WRITE INTO THE 2901'S SELECTING DEST = 1, WITH PARITY ODD 
	HI FOR BOTH HALFS. DISABLE BOTH HALFS OF DP PARITY.DP B ADRS = \O1
	THEN OUTPUT 0 ON DP, PASS IT THROUGH THE DBUS CHK \S0 HALF
	OF DBUS PARITY.EXAMINE THE 8080 REGISTER 100 AND VERIFY DP PARITY BIT.
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[4
!	DP PARITY TEST
STIMULUS:
	WRITE INTO THE 2901'S SELECTING DEST = 7, WITH PARITY ODD 
	HI FOR BOTH HALFS. ENABLE BOTH HALFS OF DP PARITY.
	THEN OUTPUT 0 ON DP, PASS IT THROUGH THE DBUS CHK \S0 HALFS
	OF DBUS PARITY.EXAMINE THE 8080 REGISTER 100 AND VERIFY DP PARITY BIT.
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
[5
!	DP PARITY TEST
STIMULUS:
	WRITE INTO THE 2901'S SELECTING DEST = 3, WITH PARITY ODD 
	HI FOR BOTH HALFS.DPE5 WRITE PARITY SHOULD BE HI. PARITY SHOULD 
	NOT CHANGE IN THE RAM.
	THEN OUTPUT 0 ON DP, PASS IT THROUGH THE DBUS CHK \S0 HALFS
	OF DBUS PARITY.EXAMINE THE 8080 REGISTER 100 AND VERIFY DP PARITY BIT.
RESPONSE:
	EXAMINE NXT CRAM ADRS
!
]51
[1
!STIMULUS:
	LOAD THE VMA WITH RAMFILE ADRS \O0 FROM THE 2901'S Q REGISTER
	WRITE A \O1 INTO RAMFILE ADRS SELECTED BY THE VMA
	START A PHYSICAL MEM WRITE CYCLE
	OUTPUT THE CONTENTS OF THE RAMFILE INTO MEM
	(BOTH RAMFILE AND PHYSICAL MEM ADRS'S ARE SELECTED BY THE VMA = \O0)
	EXAMINE THE SELECTED MEM LOCATION \O0 AND VERIFY DATA
RESPONSE:
!
]52
[1
!	RAMFILE PARITY TEST
STIMULUS:
	LOAD THE VMA WITH RAMFILE ADRS \O0 FROM THE 2901'S Q REGISTER
	WRITE INTO THE RAMFILE ADRS POINTED TO BY THE VMA
	A DATA WORD TO GENERATE BOTH HALFS OF PARITY \S1 .
	OUTPUT THE CONTENTS OF THE RAMFILE THROUGH THE DBUS
	AND CHECK BOTH HALFS OF THE DBUS PARITY.
	EXAMINE THE 8080'S REGISTER 100 AND VERIFY DP PPARITY BIT.
RESPONSE:
!
]53
[1
!	RAMFILE ADRS TEST
STIMULUS:
	LOAD THE VMA WITH A 1777
	WRITE A ZERO INTO RAMFILE LOCATION POINTED TO BY THE VMA
	LOAD THE VMA WITH A \O0
	WRITE A -1 INTO RAMFILE LOCATION POINTED TO BY THE VMA
	LOAD THE VMA BACK WITH A 1777
	READ THE CONTENTS OF THE RAMFILE POINTED TO BY THE VMA 
	AND VERIFY THAT IT DID NOT CHANGE
RESPONSE:
	RAMFILE CONTENTS DID CHANGE
	BIT 0\D1 OF RAMFILE ADRS IS STUCK HI
!
]54
[1
!	RAMFILE ADRS TEST
STIMULUS:
	LOAD THE VMA WITH A ZERO
	WRITE A ZERO INTO RAMFILE LOCATION POINTED TO BY THE VMA
	LOAD THE VMA WITH A \O0
	WRITE A -1 INTO RAMFILE LOCATION POINTED TO BY THE VMA
	LOAD THE VMA BACK WITH A ZERO
	READ THE CONTENTS OF THE RAMFILE POINTED TO BY THE VMA 
	AND VERIFY THAT IT DID NOT CHANGE
RESPONSE:
	RAMFILE CONTENTS DID CHANGE
	BIT 0\D1 OF RAMFILE ADRS IS STUCK LO
!
]55
[1
!	RAMFILE ADRS TEST (RAMFILE SELECT = 0)
STIMULUS:
	LOAD DPE5 CURRENT AC BLOCK WITH \S0.
	LOAD DPEA AC WITH \S0.
	LOAD THE 10 BIT VMA COPY ON DPE5 WITH \O1.
	CLEAR RAMFILE LOCATION POINTED TO BY THE VMA (SELECT = 6).
	WRITE A -1 INTO RAMFILE LOCATION POINTED TO BY 
	DPEA AC & DPE5 AC CURRENT BLOCK (RAMFILE SELECT = 0).
	READ BACK THE CONTENTS OF THE RAMFILE LOCATION POINTED TO BY
	THE VMA (SELECT = 6) AND VERIFY THAT IT CHANGED TO A -1.
!
]56
[1
!	RAMFILE ADRS TEST (RAMFILE SELECT 2)
STIMULUS:
	TURN PXCT ON AND LOAD PXCT 09 WITH \S1
	LOAD THE XR REGISTER WITH ALL \S0 AND LOAD XR PREVIOUS WITH \S1
	LOAD AC PREVIOUS BLK WITH ALL \S0 AND CURRENT BLOCK WITH ALL ONES
	LOAD THE 10 BIT VMA COPY ON DPE5 WITH \O2.
	CLEAR THE RAMFILE LOCATION POINTED TO BY THE VMA(SELECT = 6).
	WRITE A -1 INTO RAMFILE LOCATION SELECTING 2 (XR & XR BLOCK)
	READ BACK THE CONTENTS OF THE RAMFILE LOCATION POINTED TO BY
	THE VMA (SELECT = 6) AND VERIFY THAT IT CHANGED TO A -1.
!
]57
[1
!	RAMFILE ADRS TEST (RAMFILE SELECT 4)
STIMULUS:
	LOAD AC PREVIOUS AND CURRENT TO 0.\S1
	LOAD THE 10 BIT VMA COPY ON DPE5 WITH \O0.
	CLEAR THE RAMFILE LOCATION POINTED TO BY THE VMA (SELECT = 6)
	WRITE A -1 INTO RAMFILE LOCATION SELECTING 4 
	READ BACK THE CONTENTS OF THE RAMFILE LOCATION POINTED TO BY
	THE VMA (SELECT = 6) AND VERIFY THAT IT CHANGED TO A -1.
!
]58
[1
!	RAMFILE ADRS TEST (RAMFILE SELECT 7)
STIMULUS:
	LOAD THE 10 BIT VMA COPY ON DPE5 WITH \O0.
	CLEAR THE RAMFILE LOCATION POINTED TO BY THE VMA(SELECT = 6).
	WRITE A -1 INTO RAMFILE LOCATION SELECTING 7 WITH DPM4 VMA AC REF HI
	( # FIELD = \O0 FOR BOTH HALFS OF THE DBM).
	READ BACK THE CONTENTS OF THE RAMFILE LOCATION POINTED TO BY
	THE VMA (SELECT = 6) AND VERIFY THAT IT CHANGED TO A -1.
!
]59
[1
!	RAMFILE ADRS TEST (RAMFILE SELECT 7) WITH VMA AC REF LO
STIMULUS:
	LOAD THE 10 BIT VMA COPY ON DPE5 WITH \O0.
	CLEAR THE RAMFILE LOCATION POINTED TO BY THE VMA(SELECT = 6).
	WRITE A -1 INTO RAMFILE LOCATION SELECTING 7 
	( # FIELD = \O0 FOR BOTH HALFS OF THE DBM).
	READ BACK THE CONTENTS OF THE RAMFILE LOCATION POINTED TO BY
	THE VMA (SELECT = 6) AND VERIFY THAT IT CHANGED TO A -1.
!
]60
[1
!	RAMFILE ADRS TEST (RAMFILE SELECT 1)
STIMULUS:
	LOAD DPEA AC WITH \O2
	LOAD AC CURRENT BLOCK TO \O0
	LOAD THE 10 BIT VMA COPY ON DPE5 WITH \O1.
	CLEAR THE RAMFILE LOCATION POINTED TO BY THE VMA (SELECT = 6)
	WRITE A -1 INTO RAMFILE LOCATION SELECTING 1, DBM = \O3 
	READ BACK THE CONTENTS OF THE RAMFILE LOCATION POINTED TO BY
	THE VMA (SELECT = 6) AND VERIFY THAT IT CHANGED TO A -1.
!
]61
[1
!	SET SWEEP TEST
STIMULUS:
	DEPOSITE A -1 IN MEM LOCATION 0
	START A MEM CYCLE AND LOAD THE VMA WITH 11012
	SWEEP THE CASH (SPEC = 24) WITH A ZERO ON DP 
	(SHOULD LOAD THE VMA WITH A 0)
	FINISH THE MEM WRITE CYCLE
	EXAMINE MEM LOCATION 0 AND VERIFY IT CHANGED TO 0
!
]62
[1
!	RAMFILE WRITE ENABLE TEST
STIMULUS:
	LOAD THE VMA WITH 0 AND NO PHYSICAL (SET VMA AC REF)
	WRITE A 0 INTO RAMFILE LOCATION POINTED TO BY THE VMA 
	(WRITE BIT FROM THE CRAM)
	WRITE A 2 INTO THE SAME LOCATION 
	(ENABLE WRITE FROM DPM4 RAMFILE WRITE) = \S0
	EXAMINE THAT RAMFILE LOCATION AND VERIFY IF IT CHANGED
RESPONSE:
	RAMFILE CONTENTS DID\S1CHANGE
!
]63
[1
!STIMULUS:
	DID A DROM DISPATCH AT DROM LOCATION 000
	DROM 000 CONTAINS / 0000,1556,2100
	AC DISP BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + CRAM J
	         = 1400 +  156   +  0000  = 1556
!
[2
!STIMULUS:
	DID AN AREAD DISPATCH AT DROM LOCATION 000
	DROM 000 CONTAINS / 0000,1556,2100
	DROM A=J BIT IS HI, ACDISP BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + CRAM J
	         = 1400 +  156   +  0000  = 1556
!
[3
!STIMULUS:
	DID AN ADISP AT DROM LOCATION 000
	DROM 000 CONTAINS / 0000,1556,2100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM A + CRAM J (0-7)
	         =  00    + 	 000     = 0000
!
[4
!STIMULUS:
	DID A BDISP AT DROM LOCATION 000
	DROM 000 CONTAINS / 0000,1556,2100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM B + CRAM J (0-7)
		 =   00   +    000	 =0000
!
[5
!STIMULUS:
	D A SKIP ON TXXX (SKIP = 57) FOR DROM LOCATION 000
	DROM 000 SHOULD CONTAIN TXXX LO
	WE GET NXT CRAM ADRS = CRAM J = 0
RESPONSE:
!
[6
!STIMULUS:
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE VMA WITH 11012
	LOAD THE IR WITH DROM ADDRESS /000
	DROM CONTAINS /0000,1556,2100
	VMA EN BIT IS HI
	LOAD THE VMA WITH 0 IF DROM ASKS
	WRITE A ZERO TO PHYSICAL MEM
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
[7
!STIMULUS:
	LOAD THE VMA WITH A ZERO
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE IR WITH DROM ADDRESS /000
	DROM CONTAINS /0000,1556,2100
	COND FUNC BIT IS LO
	START AND FINISH A PHYSICAL MEM WRITE CYCLE DROM ASKS (OUTPUT A ZERO)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
[8
!STIMULUS:
	LOAD THE IR WITH DROM ADDRESS /000
	DROM CONTAINS /0000,1556,2100
	READ AND WRT TEST BITS ARE LO
	START A MEM CYCLE DO AN AREAD IF DROM ASKS
	ABORT MEM CYCLE, AND STOR THE VMA FLAGS IN 2901'S VIA DBM & DBUS
	START A MEM CYCLE
	FINISH MEM CYCLE AND OUTPUT THE VMA FLAGS TO MEM
	(BITS 3 & 4 CONTAIN DROM BITS READ AND WRT TEST)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
]64
[1
!STIMULUS:
	DID A DROM DISP AT DROM LOCATION 777
	DROM 777 CONTAINS / 0007,1657,2100
	AC DISP BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + CRAM J
	         = 1400 +  257   +  0000  = 1657
!
[2
!STIMULUS:
	DID AN AREAD DISP AT DROM LOCATION 777
	DROM 777 CONTAINS / 0007,1657,2100
	A = J BIT IS HI, AC DISP BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + CRAM J
	         = 1400 +  257   +  0000  = 1657
!
[3
!STIMULUS:
	DID AN ADISP AT DROM LOCATION 777
	DROM 777 CONTAINS / 0007,1657,2100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM A + CRAM J (0-7)
	         =  00    + 	 000     = 0000
!
[4
!STIMULUS:
	DID A BDISP AT DROM LOCATION 777
	DROM 777 CONTAINS / 0007,1657,2100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM  + CRAM J (0-7)
	         =  07    + 	 000     = 007
!
[5
!STIMULUS:
	DID A SKIP ON TXXX (SKIP = 57) AT DROM LOCATION 777
	DROM 777 SHOULD CONTAIN TXXX HI
	WE GET NXT CRAM ADRS = CRAM J + 1 = 1
RESPONSE:
	EXAMINE DATA FROM PHYSICAL MEM 0
!
[6
!STIMULUS:
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE VMA WITH 11012
	LOAD THE IR WITH DROM ADDRESS /777
	DROM CONTAINS /0007,1657,2100
	VMA EN BIT IS HI
	LOAD THE VMA WITH 0 IF DROM ASKS
	WRITE A ZERO TO PHYSICAL MEM
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
[7
!STIMULUS:
	LOAD THE VMA WITH A ZERO
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE IR WITH DROM ADDRESS /777
	DROM CONTAINS /0007,1657,2100
	COND FUNC BIT IS LO
	START AND FINISH A PHYSICAL MEM WRITE CYCLE DROM ASKS (OUTPUT A ZERO)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
[8
!STIMULUS:
	LOAD THE IR WITH DROM ADDRESS /777
	DROM CONTAINS /0007,1657,2100
	READ AND WRT TEST BITS ARE LO
	START A MEM CYCLE DO AN AREAD IF DROM ASKS
	ABORT MEM CYCLE, AND STOR THE VMA FLAGS IN 2901'S VIA DBM & DBUS
	START A MEM CYCLE
	FINISH MEM CYCLE AND OUTPUT THE VMA FLAGS TO MEM
	(BITS 3 & 4 CONTAIN DROM BITS READ AND WRT TEST)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
]65
[1
!STIMULUS:
	DID A DROM DISPATCH AT DROM LOCATION 126
	DROM 126 CONTAINS / 0711,1626,1100
	AC DISP BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + CRAM J
	         = 1400 +  226   +  0000  = 1626
!
[2
!STIMULUS:
	DID AN AREAD DISPATCH AT DROM LOCATION 126
	DROM 126 CONTAINS / 0711,1626,1100
	DROM A=J BIT IS LO ACDICP BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 40  +  DROM A
	         = 40  +  07     = 47
!
[3
!STIMULUS:
	DID AN ADISP AT DROM LOCATION 126
	DROM 126 CONTAINS / 0711,1626,1100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM A + CRAM J (0-7)
	         =  07    + 	 000     = 0007
!
[4
!STIMULUS:
	DID A BDISP AT DROM LOCATION 126
	DROM 126 CONTAINS / 0711,1626,1100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM B + CRAM J (0-7)
		 =   11   +    000	 = 0011
!
]66
[1
!STIMULUS:
	DID A DROM DISPATCH AT DROM LOCATION 701
	DROM 701 CONTAINS / 1200,1720,4100
	AC DISP BIT IS HI AC FIELD LOADED IS ZERO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + AC FIELD
	         = 1400 +  320   +  0000  = 1720
!
[2
!STIMULUS:
	DID A DROM DISPATCH DROM LOCATION
	CONTAINS AC DISP BIT HI
	AC FIELD IS 17
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + AC FIELD
		 =1400  +  320   +  17	      = 1737
!
[3
!STIMULUS:
	DID AN AREAD DISPATCH AT DROM LOCATION 701
	DROM 701 CONTAINS / 1200,1720,4100
	DROM A=J BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 40  +  DROM A
	         = 40  +  12     = 52
!
[4
!STIMULUS:
	DID AN ADISP AT DROM LOCATION 701
	DROM 701 CONTAINS / 1200,1720,4100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM A + CRAM J (0-7)
	         =  12    + 	 000     = 0012
!
[5
!STIMULUS:
	DID A BDISP AT DROM LOCATION 701
	DROM 701 CONTAINS / 1200,1720,4100
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM B + CRAM J (0-7)
		 =   00   +    000	 =0000
!
]67
[1
!STIMULUS:
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE VMA WITH 11012
	LOAD THE IR WITH DROM ADDRESS /240
	DROM CONTAINS /0400,1622,1000
	VMA EN BIT IS LO
	LOAD THE VMA WITH 0 IF DROM ASKS
	WRITE A ZERO TO PHYSICAL MEM
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
]68
[1
!STIMULUS:
	LOAD THE VMA WITH A ZERO
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE IR WITH DROM ADDRESS /277
	DROM CONTAINS /0017,1561,1700
	COND FUNC BIT IS HI
	START AND FINISH A PHYSICAL MEM WRITE CYCLE DROM ASKS (OUTPUT A ZERO)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
[2
!STIMULUS:
	LOAD THE IR WITH DROM ADDRESS /277
	DROM CONTAINS /0017,1561,1700
	READ AND WRT TEST BITS ARE HI
	START A MEM CYCLE DO AN AREAD IF DROM ASKS
	ABORT MEM CYCLE, AND STOR THE VMA FLAGS IN 2901'S VIA DBM & DBUS
	START A MEM CYCLE
	FINISH MEM CYCLE AND OUTPUT THE VMA FLAGS TO MEM
	(BITS 3 & 4 CONTAIN DROM BITS READ AND WRT TEST)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
]69
[1
!STIMULUS:
	DID A DROM DISPATCH AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	AC DISP BIT LO.
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + CRAM J
!
[2
!STIMULUS:
	DID A DROM DISPATCH AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	AC DISP BIT HI
	AC FIELD IS 00
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + AC FIELD
!
]70
[1
!STIMULUS:
	DID AN AREAD DISPATCH AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	A = J BIT HI
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 1400 + DROM J + CRAM J
!
[2
!STIMULUS:
	DID AN AREAD DISPATCH AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	A = J BIT IS LO
	DROM A CONTAINS /\O2
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = 40 + DROM A 
!
]71
[1
!STIMULUS:
	DID SKIP ON TXXX AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	TXXX BIT HI
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = CRAM J + 1
!
[2
!STIMULUS:
	DID SKIP ON TXXX AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	TXXX BIT IS LO
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = CRAM J + 0
!
]72
[1
!STIMULUS:
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE VMA WITH 11012
	LOAD THE IR WITH DROM ADDRESS /\O0
	DROM CONTAINS /\U1
	VMA EN BIT IS HI
	LOAD THE VMA WITH 0 IF DROM ASKS
	WRITE A ZERO TO PHYSICAL MEM
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
[2
!STIMULUS:
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE VMA WITH 11012
	LOAD THE IR WITH DROM ADDRESS /\O0
	DROM CONTAINS /\U1
	VMA EN BIT IS LO
	LOAD THE VMA WITH 0 IF DROM ASKS
	WRITE A ZERO TO PHYSICAL MEM
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
]73
[1
!STIMULUS:
	LOAD THE IR WITH DROM ADDRESS /\O0
	DROM CONTAINS /\U1
	WRT TEST BIT FOUND WAS \S3, IT SHOULD BE \S2
	READ BIT FOUND WAS \S5, IT SHOULD BE \S4
!
]74
[1
!STIMULUS:
	LOAD THE VMA WITH A ZERO
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE IR WITH DROM ADDRESS /\O0
	DROM CONTAINS /\U1
	COND FUNC BIT IS HI
	START AND FINISH A PHYSICAL MEM WRITE CYCLE DROM ASKS (OUTPUT A ZERO)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
[2
!STIMULUS:
	LOAD THE VMA WITH A ZERO
	DEPOSITE -1 IN PHYSICAL MEM 0
	LOAD THE IR WITH DROM ADDRESS /\O0
	DROM CONTAINS /\U1
	COND FUNC BIT IS LO
	START AND FINISH A PHYSICAL MEM WRITE CYCLE DROM ASKS (OUTPUT A ZERO)
RESPONSE:
	EXAMINE PHYSICAL MEM 0 AND SEE IF IT CHANGED
!
]75
[1
!STIMULUS:
	DID AN ADISP AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	DROM A CONTAINS /\O2
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM A + CRAM J
!
]76
[1
!STIMULUS:
	DID A BDISP AT DROM LOCATION /\O0
	DROM CONTAINS /\U1
	B FEILD IS /\O2
RESPONSE:
	WE READ NEXT CRAM ADDRESS WHICH SHOULD BE
	NXT ADRS = DROM B + CRAM J
!