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PDP-10 Archives
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klad_sources
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klad.sources/mscra.msg
There are no other files named mscra.msg in the archive.
]1
[1
!STIMULUS:
WRT 205/7 - SET DIAG FN = 7 TO READ BACK ZEROS.
WRT 210/111 - CLOCK DATA FROM CRA BOARD TO CSL BOARD USING
'CRA T CLK ENABLE'.
RESPONSE:
DATA READ BACK WAS NOT ALL ZEROS.
!
]2
[1
!STIMULUS:
WRT 103/DATA - WRITE DATA PATTERN INTO CSL I/O BUFFER
WRT 105/DATA
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 205/11 - SET DIAG FN = 11 TO READ BACK BUS DATA BITS.
WRT 210/111 - CLOCK DATA FROM CRA BOARD TO CSL BOARD USING
'CRA T CLK ENABLE'.
RESPONSE:
DATA READ BACK WAS NOT WHAT WAS WRITTEN TO CRA BOARD.
!
]3
[1
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/0 - SET DIAG FN = 0 TO ACCESS CRAM BITS 0-11
WRT 103/DATA - WRITE 'CORRECT' DATA INTO CSL I/O BUFFER
WRT 105/DATA
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 0-11.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 210/111 - CLOCK CRAM BITS 0-11 TO CSL BOARD.
RESPONSE:
CRAM BITS 0-11 WERE NOT READ BACK AS THEY WERE WRITTEN.
!
]4
[1
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/1 - SET DIAG FN = 1 TO ACCESS CRAM BITS 12-23
WRT 103/DATA - WRITE 'CORRECT' DATA INTO CSL I/O BUFFER
WRT 105/DATA
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 12-23.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 205/4 - SET DIAG FN = 4 TO READ CRAM BITS 12-23.
WRT 210/111 - CLOCK CRAM BITS 12-23 TO CSL BOARD.
RESPONSE:
CRAM BITS 12-23 WERE NOT READ BACK AS THEY WERE WRITTEN.
!
]5
[1
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/2 - SET DIAG FN = 2 TO WRITE CRAM BITS 24-35A
WRT 103/DATA - WRITE 'CORRECT' DATA INTO CSL I/O BUFFER
WRT 105/DATA
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 24-35A.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 205/5 - SET DIAG FN = 5 TO READ CRAM BITS 24-35A.
WRT 210/111 - CLOCK CRAM BITS 24-35A TO CSL BOARD.
RESPONSE:
CRAM BITS 24-35A WERE NOT READ BACK AS THEY WERE WRITTEN.
!
]6
[1
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/2 - SET DIAG FN = 2 TO WRITE CRAM BITS 24-35B
WRT 103/DATA - WRITE 'CORRECT' DATA INTO CSL I/O BUFFER
WRT 105/DATA
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 24-35B.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 205/6 - SET DIAG FN = 6 TO READ CRAM BITS 24-35B.
WRT 210/111 - CLOCK CRAM BITS 24-35B TO CSL BOARD.
RESPONSE:
CRAM BITS 24-35B WERE NOT READ BACK AS THEY WERE WRITTEN.
!
]7
[1
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/0 - SET DIAG FN = 0 TO ACCESS CRAM BITS 0-11
WRT 103/377 - WRITES ALL ONES INTO CSL I/O BUFFER
WRT 105/17
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 0-11.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 204/1 - ASSERT 'CRA/M RESET'.
WRT 204/0 - NEGATE IT.
WRT 210/111 - CLOCK CRAM BITS 0-11 TO CSL BOARD.
RESPONSE:
CRAM BITS 0-11 WERE NOT NEGATED BY 'CRA/M RESET'.
!
]8
[1
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/1 - SET DIAG FN = 1 TO ACCESS CRAM BITS 12-23
WRT 103/377 - WRITES ALL ONES INTO CSL I/O BUFFER
WRT 105/17
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 12-23.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 204/1 - ASSERT 'CRA/M RESET'.
WRT 204/0 - NEGATE IT.
WRT 205/4 -SET DIAG FN = 4 TO READ CRAM BITS 12-23
WRT 210/111 - CLOCK CRAM BITS 12-23 TO CSL BOARD.
RESPONSE:
CRAM BITS 12-23 WERE NOT NEGATED BY 'CRA/M RESET'.
!
]9
[1
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/2 - SET DIAG FN = 2 TO ACCESS CRAM BITS 24-35A
WRT 103/377 - WRITES ALL ONES INTO CSL I/O BUFFER
WRT 105/17
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 24-35A.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 204/1 - ASSERT 'CRA/M RESET'.
WRT 204/0 - NEGATE IT.
WRT 205/5 - SET DIAG FN = 5 TO READ CRAM BITS 24-35A
WRT 210/111 - CLOCK CRAM BITS 24-35A TO CSL BOARD.
RESPONSE:
CRAM BITS 24-35A WERE NOT NEGATED BY 'CRA/M RESET'.
!
[2
!STIMULUS:
SET CRAM ADDRESS TO ZERO
WRT 205/2 - SET DIAG FN = 2 TO ACCESS CRAM BITS 24-35B
WRT 103/377 - WRITES ALL ONES INTO CSL I/O BUFFER
WRT 105/17
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS USING
'CRA R CLK'.
WRT 204/40 - ASSERT 'CRAM WRITE' TO WRITE DATA INTO CRAM
WRT 204/0 - BITS 24-35B.
WRT 206/2 - ASSERT 'SINGLE CLK' TO CLOCK CRAM BITS INTO
LATCHES.
WRT 204/1 - ASSERT 'CRA/M RESET'.
WRT 204/0 - NEGATE IT.
WRT 205/6 - SET DIAG FN = 6 TO READ CRAM BITS 24-35B
WRT 210/111 - CLOCK CRAM BITS 24-35B TO CSL BOARD.
RESPONSE:
CRAM BITS 24-35B WERE NOT NEGATED BY 'CRA/M RESET'.
!
]10
[1
!STIMULUS:
X1 \O0 - THIS EXECUTES AN 8080 SUBROUTINE WHICH:
CLEARS THE CRAM REGISTER,
LOADS THE DIAG ADR = \O0.
WRT 205/1 - SET DIAG FN = 1 TO READ NEXT CRAM ADDR
WRT 210/111 - READ THE NEXT CRAM ADDR
RESPONSE:
THE NEXT CRAM ADDR IS NOT WHAT WAS WRITTEN AS 'DIAG ADR'.
!
]11
[1
!STIMULUS:
X1 \O0 - THIS EXECUTES AN 8080 SUBROUTINE WHICH:
CLEARS THE CRAM REGISTER,
LOADS THE DIAG ADR = \O0.
WRT 206/2 - CLOCK NEXT ADDR INTO CURRENT ADDR
WRT 205/3 - SET DIAG FN = 3 TO READ CURR LOC
X1 0 - THIS EXECUTES AN 8080 SUBROUTINE WHICH:
CLEARS THE CRAM REGISTER,
LOADS THE DIAG ADR = 0.
WRT 210/111 - READ THE CURR LOC
RESPONSE:
'CURR LOC' DID NOT GET LOADED CORRECTLY.
!
]12
[1
!STIMULUS:
LOAD CRAM LOCATION ZERO WITH MICRO-INSTR WITH J FIELD = \O0.
CP 1 - GIVE A CLOCK PULSE TO GATE THE J FIELD THRU THE CRAM
ADDRESS MUXS.
RESPONSE:
THE J FIELD DID NOT BECOME THE NEXT CRAM ADDRESS.
!
[2
!STIMULUS:
LOAD CRAM LOCATION \O0 WITH ALL ONES.
LOAD CRAM LOCATION ZERO WITH MICRO-INSTR WITH J FIELD = \O0.
CP 1 - GIVE A CLOCK PULSE TO GATE THE J FIELD THRU THE CRAM
ADDRESS MUXS.
CP 1 - GIVE ANOTHER PULSE TO CLOCK CRAM BITS FROM LOCATION
\O0 INTO THE CRAM BIT REGISTER.
EC - READ BACK THOSE BITS
RESPONSE:
BITS 36-71 WERE NOT READ BACK AS ONES. THIS IMPLIES THAT THE
NEXT ADDRESS BITS WHICH GO TO THE 'CRM' BOARD (CRA1 ADR 00-11)
ARE NOT CORRECT, I.E., NOT EQUAL TO \O0. THEREFORE, THE CRAM
BITS READ BACK WERE FROM A DIFFERENT LOCATION.
!
]13
[1
!STIMULUS:
WRITE ZEROS TO BITS 0-35 OF CRAM LOCATION \O0.
RESPONSE:
NON-ZERO DATA WAS READ BACK FROM LOCATION \O0.
!
[1
!STIMULUS:
WRITE ONES TO BITS 0-35 OF CRAM LOCATION \O0.
RESPONSE:
DATA WHICH WAS NOT ALL ONES WAS READ BACK FROM LOCATION \O0.
!
]14
[1
!STIMULUS:
WRITE ZEROS INTO BITS 0-35 OF CRAM LOCATION 0.
WRITE ONES INTO BITS 0-35 OF CRAM LOCATION \O0.
RESPONSE:
BITS 0-35 READ BACK FROM LOCATION 0 ARE NOT ALL ZEROS. THIS
IMPLIES THAT WRITING INTO LOCATION \O0 REALLY WROTE INTO
LOCATION 0, OR VICE-VERSA.
!
[2
!STIMULUS:
WRITE ZEROS INTO BITS 36-95 OF CRAM LOCATION 0.
WRITE ONES INTO BITS 36-95 OF CRAM LOCATION \O0.
RESPONSE:
BITS 36-95 READ BACK FROM LOCATION 0 ARE NOT ALL ZEROS. THIS
IMPLIES THAT WRITING INTO LOCATION \O0 REALLY WROTE INTO
LOCATION 0, OR VICE-VERSA.
!
]15
[1
!STIMULUS:
SET CRAM ADDRESS = THE COMPLEMENT OF THE PRESENT VALUE OF
'SBR RET'.
GENERATE 2 CPU CLOCK PULSES - THE FIRST WILL CLOCK THE CRAM
ADDRESS INTO 'CURR LOC' AND INTO THE STACK. SINCE
'CALL OR RETURN' SHOULD BE NEGATED, THE 2ND PULSE
SHOULD NOT CLOCK THE ADDRESS INTO 'SBR RET'.
RESPONSE:
THE VALUE OF 'SBR RET' CHANGED.
!
]16
[1
!STIMULUS:
LOAD CRAM ADDR \O0 WITH A CALL MICROINSTRUCTION.
CP 2 - THE FIRST CLOCK PULSE WILL CLOCK THE CRAM ADDR INTO
'CURR LOC' AND THE CALL MICRO-INSTR INTO THE LATCHES.
THE 2ND PULSE SHOULD EXECUTE THE CALL MICRO-INSTR.
THIS SHOULD CLOCK THE 'CURR LOC' CONTENTS THRU THE
SUBROUTINE STACK RAM AND INTO THE 'SBR RET' LATCHES.
RESPONSE:
THE VALUE CLOCKED INTO 'SBR RET' IS NOT EQUAL TO THE ORIGINAL
CRAM ADDR.
!
]17
[1
!STIMULUS:
LOAD CRAM ADDR \O0 WITH A CALL MICROINSTRUCTION.
LOAD CRAM ADDR 707 WITH RETURN MICROINSTRUCTION.
CP 2 - THE FIRST CLOCK PULSE WILL CLOCK THE CRAM ADDR INTO
'CURR LOC' AND THE CALL MICRO-INSTR INTO THE LATCHES.
THE 2ND PULSE SHOULD EXECUTE THE CALL MICRO-INSTR.
THIS SHOULD CLOCK THE 'CURR LOC' CONTENTS THRU THE
SUBROUTINE STACK RAM AND INTO THE 'SBR RET' LATCHES.
IT WILL ALSO LATCH THE RETURN MICRO-INSTR WHICH IN
TURN WILL SELECT THE 'SBR RET' INPUTS TO THE CRAM
ADDR MUXS.
RESPONSE:
THE NEXT CRAM ADDR IS NOT EQUAL TO THE 'SBR RET' ADDRESS.
!
]18
[1
!STIMULUS:
LOAD MICRO-INSTRUCTIONS STARTING AT LOCATION 0 WHICH WILL
EXECUTE 15 'CALLS' FROM EVEN LOCATIONS, I.E., FROM 0 TO
2 TO 4 TO 6 ETC. LOCATION 36 AND ALL ODD LOCATIONS UP
TO THAT CONTAIN 'RETURNS' WITH A J FIELD OF 1.
X1 0 - SET CRAM ADDRESS TO 0.
CP 15 - EXECUTE THE 15 CALL INSTRUCTIONS.
CP \O0 - EXECUTE \O0 RETURN INSTRUCTIONS.
RESPONSE:
THE NEXT CRAM ADDRESS IS NOT CORRECT.
!
]19
[1
!STIMULUS:
LOAD MICRO-INSTRUCTIONS TO JUMP FROM 0 TO 2, DO A CALL FROM 2 TO
4, DO A CALL FROM 4 TO 6, AND DO A RETURN FROM 6.
X1 0 - SET THE CRAM ADDRESS TO ZERO.
CP 3 - THREE CLOCK PULSES EXECUTE THE CALL INSTRS AT LOCS 2
AND 4.
WRT 204/2 - DO A STACK RESET.
WRT 204/0
CP 1 - EXECUTE THE RETURN INSTR AT LOC 6. AFTER THE STACK
RESET, THIS SHOULD CAUSE THE NEXT CRAM ADDR TO BE 2
INSTEAD OF 4.
RESPONSE:
THE NEXT CRAM ADDRESS AFTER EXECUTING THE RETURN IS NOT 2.
!
]20
[1
!STIMULUS:
LOAD MICRO-INSTR TO DO A NICOND DISPATCH TO 377X.
TP 0 - NEGATE 'CSL4 TRAP EN'. THIS WILL NEGATE
'DPE9 TRAP 1,2 AND 3'.
WRT 212/4 - ASSERT 'RUN' PRE-FLOP
CP 1 - GIVE A CLOCK PULSE TO ASSERT 'RUN'.
X1 0 - SET NEXT CRAM ADDR TO 0.
CP 1 - EXECUTE THE NICOND DISPATCH. WITH ALL TRAPS
NEGATED AND 'RUN' ASSERTED, 'CRA2 NICOND 9, 10
AND 11' SHOULD ALL BE ASSERTED.
RESPONSE:
THE NEXT CRAM ADDR DID NOT DISPATCH TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO DO A NICOND DISPATCH TO 377X.
TP 0 - NEGATE 'CSL4 TRAP EN'. THIS WILL NEGATE
'DPE9 TRAP 1,2 AND 3'.
WRT 212/0 - NEGATE 'RUN' PRE-FLOP
WRT 100/200 - ASSERT 'RESET' TO NEGATE 'RUN'
WRT 100/0 - NEGATE 'RESET'
X1 0 - SET NEXT CRAM ADDR TO 0.
CP 1 - EXECUTE THE NICOND DISPATCH. WITH ALL TRAPS
NEGATED AND 'RUN' NEGATED, 'CRA2 NICOND 9
AND 11' SHOULD ALL BE ASSERTED AND 'CRA2
NICOND 10' SHOULD BE NEGATED.
RESPONSE:
THE NEXT CRAM ADDR DID NOT DISPATCH TO 3775.
!
[3
!STIMULUS:
LOAD MICRO-INSTRS TO SET 'DPE9 TRAP 1' AND DO A NICOND DISPATCH
TO 377X.
TP 1 - ASSERT 'CSL4 TRAP EN'.
WRT 212/0 - NEGATE 'RUN' PRE-FLOP
WRT 100/200 - ASSERT 'RESET' TO NEGATE 'RUN'
WRT 100/0 - NEGATE 'RESET'
X1 0 - SET NEXT CRAM ADDR TO 0.
CP 3 - EXECUTION OF THE FIRST MICRO-INSTR ASSERTS
'DPEB TRAP EN'. THE 2ND INSTR ASSERTS
'DPE9 TRAP 1'. THE 3RD INSTR DOES A NICOND
DISPATCH TO LOCATION 377X. WITH 'TRAP 1'
ASSERTED, 'CRA2 NICOND 9-11' SHOULD BE = 3.
RESPONSE:
THE NEXT CRAM ADDR DID NOT DISPATCH TO 3773.
!
[4
!STIMULUS:
LOAD MICRO-INSTRS TO SET 'DPE9 TRAP 2' AND DO A NICOND DISPATCH
TO 377X.
TP 1 - ASSERT 'CSL4 TRAP EN'.
WRT 212/0 - NEGATE 'RUN' PRE-FLOP
WRT 100/200 - ASSERT 'RESET' TO NEGATE 'RUN'
WRT 100/0 - NEGATE 'RESET'
X1 0 - SET NEXT CRAM ADDR TO 0.
CP 3 - EXECUTION OF THE FIRST MICRO-INSTR ASSERTS
'DPEB TRAP EN'. THE 2ND INSTR ASSERTS
'DPE9 TRAP 2'. THE 3RD INSTR DOES A NICOND
DISPATCH TO LOCATION 377X. WITH 'TRAP 2'
ASSERTED, 'CRA2 NICOND 9-11' SHOULD BE = 2.
RESPONSE:
THE NEXT CRAM ADDR DID NOT DISPATCH TO 3772.
!
[5
!STIMULUS:
LOAD MICRO-INSTRS TO SET 'DPE9 TRAP 1 AND 2' AND DO A NICOND
DISPATCH TO 377X.
TP 1 - ASSERT 'CSL4 TRAP EN'.
WRT 212/0 - NEGATE 'RUN' PRE-FLOP
WRT 100/200 - ASSERT 'RESET' TO NEGATE 'RUN'
WRT 100/0 - NEGATE 'RESET'
X1 0 - SET NEXT CRAM ADDR TO 0.
CP 3 - EXECUTION OF THE FIRST MICRO-INSTR ASSERTS
'DPEB TRAP EN'. THE 2ND INSTR ASSERTS
'DPE9 TRAP 1 AND 2'. THE 3RD INSTR DOES A
NICOND DISPATCH TO LOCATION 377X. WITH
'TRAP 1 AND 2' ASSERTED, 'CRA2 NICOND 9-11'
SHOULD BE = 1.
RESPONSE:
THE NEXT CRAM ADDR DID NOT DISPATCH TO 3771.
!
]21
[1
!STIMULUS:
LOAD MICRO-INSTRS TO SET 'DPE9 TRAP 1' AND DO A TRAP CYCLE SKIP
TO 3776.
TP 1 - ASSERT 'CSL4 TRAP EN'.
X1 0 - SET NEXT CRAM ADDR TO 0.
CP 4 - EXECUTION OF THE FIRST MICRO-INSTR ASSERTS
'DPEB TRAP EN'. THE 2ND INSTR ASSERTS
'DPE9 TRAP 1'. THE 3RD INSTR ASSERTS 'SPEC/
NICOND' WHICH SHOULD ASSERT 'TRAP CYCLE'.
THE 4TH INSTR DOES A TRAP CYCLE SKIP.
RESPONSE:
THE NEXT CRAM ADDR DID NOT SKIP TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO ASSERT 'SPEC/NICOND' AND DO A TRAP CYCLE
SKIP TO 3776.
TP 0 - NEGATE 'CSL4 TRAP EN'. THIS WILL NEGATE
'DPE9 TRAP 1,2 AND 3'.
X1 3 - SET NEXT CRAM ADDR TO 3.
CP 2 - THE 1ST INSTR WILL ASSERT 'SPEC/NICOND'. WITH
ALL TRAPS NEGATED, 'NICOND 9' IS ASSERTED. SO
'TRAP CYCLE' WILL BE NEGATED. WITH 'TRAP
CYCLE' NEGATED, THE 2ND INSTR WHICH DOES A
TRAP CYCLE SKIP, SHOULD NOT SKIP.
RESPONSE:
THE NEXT CRAM ADDR DID SKIP TO 3777.
!
]22
[1
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A CONSOLE EXECUTE MODE SKIP.
WRT 212/2 - ASSERT 'EXECUTE' PRE-FLOP
CP 1 - ASSERT 'EXECUTE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE EXECUTE MODE SKIP.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A CONSOLE EXECUTE MODE SKIP.
WRT 212/2 - ASSERT 'EXECUTE' PRE-FLOP
CP 1 - ASSERT 'EXECUTE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE EXECUTE MODE SKIP. THIS WILL CAUSE
THE NEXT CRAM ADDR TO BECOME 3777.
WRT 100/200 - ASSERT 'RESET' ON THE CSL BOARD. THIS WILL
NEGATE 'CSL4 EXECUTE'. BUT WITH 'CRA2 DISP &
SKIP EN' NEGATED, THE NEXT ADDR SHOULD NOT
CHANGE.
RESPONSE:
THE NEXT CRAM ADDRESS CHANGED FROM 3777. THIS IMPLIES THAT
'CRA2 DISP & SKIP EN' IS STUCK ASSERTED.
!
[3
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A CONSOLE EXECUTE MODE SKIP.
WRT 212/0 - NEGATE 'EXECUTE' PRE-FLOP
CP 1 - NEGATE 'EXECUTE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE EXECUTE MODE SKIP.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777.
!
]23
[1
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT CONTINUE' SKIP.
WRT 212/2 - ASSERT 'CONTINUE' PRE-FLOP
CP 1 - ASSERT 'CONTINUE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT CONTINUE SKIP. SINCE
'CONTINUE' IS ASSERTED, NO SKIP SHOULD OCCUR.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT CONTINUE' SKIP.
WRT 212/0 - NEGATE 'CONTINUE' PRE-FLOP
CP 1 - NEGATE 'CONTINUE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT CONTINUE SKIP. SINCE
'CONTINUE' IS NEGATED, WE SHOULD SKIP TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
]24
[1
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT 1 MSEC TIMER' SKIP.
WRT 100/4 - ENABLE 1 MSEC TIMER. THIS SHOULD CAUSE 'DPMC
1 MSEC' TO ASSERT.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT 1 MSEC TIMER SKIP. SINCE
'1 MSEC' IS ASSERTED, NO SKIP SHOULD OCCUR.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT 1 MSEC TIMER' SKIP.
WRT 100/0 - NEGATE '1 MSEC TIMER' ENABLE. THIS SHOULD
CAUSE 'DPMC 1 MSEC' TO NEGATE.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT 1 MSEC TIMER SKIP. SINCE
'1 MSEC' IS NEGATED, WE SHOULD SKIP TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
]25
[1
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT I/O LATCH' SKIP.
WRT 115/2 - ASSERT 'I/O DATA CYCLE' IN CSL I/O BUFFER.
WRT 210/140 - GATE 'I/O DATA CYCLE' ONTO KS10 BUS. THIS
SHOULD ASSERT 'CRA2 I/O LATCH'.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT I/O LATCH SKIP. SINCE
'I/O LATCH' IS ASSERTED, NO SKIP SHOULD OCCUR.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO CLEAR 'I/O LATCH' AND TO EXECUTE A 'NOT
I/O LATCH' SKIP.
WRT 115/2 - ASSERT 'I/O DATA CYCLE' IN CSL I/O BUFFER.
WRT 210/140 - GATE 'I/O DATA CYCLE' ONTO KS10 BUS. THIS
SHOULD ASSERT 'CRA2 I/O LATCH'.
X1 0 - SET CRAM ADDR TO 0
CP 2 - THE 1ST INSTR DOES A 'SPEC/CLR I/O LATCH'.
THIS SHOULD CLEAR 'I/O LATCH'. THE 2ND INSTR
EXECUTES THE NOT CONTINUE SKIP. SINCE
'I/O LATCH' IS NEGATED,WE SHOULD SKIP TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
]26
[1
!STIMULUS:
LOAD MICRO-INSTR TO DO 'AD EQ 0' SKIP TO LOCATION 3776.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE INSTR WHICH ASSERTS 'DPEA AD=0' AND DOES
A 'AD EQ 0' SKIP (SKIP FIELD = 62).
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO DO 'AD EQ 0' SKIP TO LOCATION 3776.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE INSTR WHICH NEGATES 'DPEA AD=0' AND DOES
A 'AD EQ 0' SKIP (SKIP FIELD = 62).
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777.
!
]27
[1
!STIMULUS:
LOAD MICRO-INSTRS TO ASSERT 'DPM4 SC SIGN' AND TO DO 'SC SIGN
BIT' SKIP TO LOCATION 3776.
X1 0 - SET CRAM ADDR TO 0
CP 2 - THE FIRST INSTR SHOULD SETUP FOR THE ASSERTION OF
'DPM SC SIGN'. THE 2ND INSTR WILL ASSERT IT AND DO A
SKIP BASED ON THAT ASSERTION.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO NEGATE 'DPM4 SC SIGN' AND TO DO 'SC SIGN
BIT' SKIP TO LOCATION 3776.
X1 0 - SET CRAM ADDR TO 0
CP 2 - THE FIRST INSTR SHOULD SETUP FOR THE NEGATION OF
'DPM SC SIGN'. THE 2ND INSTR WILL NEGATE IT AND DO A
SKIP BASED ON THAT NEGATION.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777.
!
]28
[1
!STIMULUS:
LOAD MICRO-INSTR TO ASSERT 'DPM3 SCAD 00' AND DO A SCAD 00
DISPATCH (67) TO 3775.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE MICRO-INSTR. WITH 'SCAD 00' ASSERTED, THE
NEXT CRAM ADDRESS SHOULD DISPATCH TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO NEGATE 'DPM3 SCAD 00' AND DO A SCAD 00
DISPATCH (67) TO 3775.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE MICRO-INSTR. WITH 'SCAD 00' NEGATED, THE
NEXT CRAM ADDRESS SHOULD DISPATCH TO 3775.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3775.
!
]29
[1
!STIMULUS:
LOAD MICRO-INSTRS TO ASSERT 'DPE5 FLAG QR 37' THEN DO A
'MULTIPLY' DISPATCH (62) TO 3773.
X1 0 - SET CRAM ADDR TO 0
CP 5 - THE FIRST INSTR LOADS ONES INTO THE Q REGISTER.
THE NEXT 3 INSTRS SHIFT THE Q REG RIGHT AND ASSERT
'DPE1-2 QR 37'. THE LAST INSTR ASSERTS 'DPE5 FLAG
QR 37' AND DOES THE 'MULTIPLY' DISPATCH WHICH SHOULD
GO TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO NEGATE 'DPE5 FLAG QR 37' THEN DO A
'MULTIPLY' DISPATCH (62) TO 3773.
X1 0 - SET CRAM ADDR TO 0
CP 3 - THE FIRST INSTR LOADS A ZERO INTO BIT 37 OF THE Q
REGISTER. THE NEXT INSTR SHIFTS THE Q REG RIGHT AND
NEGATES 'DPE1-2 QR 37'. THE LAST INSTR NEGATES
'DPE5 FLAG QR 37' AND DOES A MULTIPLY DISPATCH WHICH
SHOULD GO TO 3773.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3773.
!
]30
[1
!STIMULUS:
LOAD MICRO-INSTRS TO ASSERT 'DPM6 MEMORY CYCLE' THEN DO A
'NICOND' DISPATCH (64) TO 3767.
X1 0 - SET CRAM ADDR TO 0
CP 3 - THE FIRST INSTR CLEARS ANY LEFT OVER PAGE FAULTS.
THE 2ND INSTR STARTS A MEMORY CYCLE. THE 3RD INSTR
ASSERTS 'DPM6 MEMORY CYCLE' AND DOES A NICOND DISPATCH
WHICH SHOULD GO TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO NEGATE 'DPM6 MEMORY CYCLE' THEN DO A
'NICOND' DISPATCH (64) TO 3767.
X1 0 - SET CRAM ADDR TO 0
CP 2 - THE FIRST INSTR DOES A SPEC/MEMORY CLEAR.THE 2ND INSTR
NEGATES 'DPM6 MEMORY CYCLE' AND DOES A NICOND DISPATCH
WHICH SHOULD GO TO 3767.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3767.
!
]31
[1
!STIMULUS:
LOAD MICRO-INSTR TO ASSERT 'DPE5 BYTE DISP 9,10,11' AND DO A
BYTE DISPATCH TO 3770.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE MICRO-INSTR TO ASSERT THE 'BYTE DISP' BITS
AND DO A BYTE DISPATCH WHICH SHOULD GO TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3777.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO NEGATE 'DPE5 BYTE DISP 9,10,11' AND DO A
BYTE DISPATCH TO 3770.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE MICRO-INSTR TO NEGATE THE 'BYTE DISP' BITS
AND DO A BYTE DISPATCH WHICH SHOULD GO TO 3770.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3770.
!
]32
[1
!STIMULUS:
LOAD MICRO-INSTR TO SETUP THE 3 EA MODE DISPATCH SIGNALS AND DO
AN 'EA MODE' DISPATCH TO 3760.
X1 0 - SET CRAM ADDR TO 0
CP 2 -THE 1ST INSTR SETS UP THE DBUS BITS AND ASSERTS SPEC IR
AND XR LOAD. THE 2ND INSTR NEGATES 'DPEA JRST,0' AND
ASSERTS 'DPEA XR=0' AND 'DPEA INDIRECT' THEN DOES AN
EA MODE DISPATCH WHICH SHOULD GO TO 3776.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3776.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO SETUP THE 3 EA MODE DISPATCH SIGNALS AND DO
AN 'EA MODE' DISPATCH TO 3760.
X1 0 - SET CRAM ADDR TO 0
CP 2 -THE 1ST INSTR SETS UP THE DBUS BITS AND ASSERTS SPEC IR
AND XR LOAD. THE 2ND INSTR ASSERTS 'DPEA JRST,0' AND
NEGATES 'DPEA XR=0' AND 'DPEA INDIRECT' THEN DOES AN
EA MODE DISPATCH WHICH SHOULD GO TO 3760.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 3760.
!
]33
[1
!STIMULUS:
LOAD MICRO-INSTRS TO SELECT DROM LOCATION WITH 'DROM J 00-03'
EQUAL TO ONES AND 'AC DISP' ASSERTED. ALSO, ASSERT
'AC 09' TO 'AC 12'.
X1 0 - SET CRAM ADDR TO 0
CP 2 -THE 1ST INSTR SETS UP THE DBUS BITS AND ASSERTS SPEC IR
AND XR LOAD. THE 2ND INSTR LOADS THE IR WITH 702,
SELECTING A DROM LOCATION WITH 'DROM J 00-03' = 1S AND
'AC DISP' ASSERTED. WITH THE AC FIELD ALL ONES, THE
DROM DISPATCH THEN SHOULD GO TO 1777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 1777.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO CAUSE A DROM DISPATCH FROM A DROM LOACTION
WHICH HAS 'DROM 00-07' = 0 AND 'AC DISP' NEGATED.
X1 0 - SET CRAM ADDR TO 0
CP 2 -THE 1ST INSTR SETS UP THE DBUS BITS AND ASSERTS SPEC IR
AND XR LOAD. THE 2ND INSTR LOADS THE IR WITH 600,
SELECTING A DROM LOCATION WITH 'DROM 00-07' = 0. THE
DROM DISPATCH SHOULD THEN GO TO 1400.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 1400.
!
]34
[1
!STIMULUS:
LOAD MICRO-INSTRS TO SELECT DROM LOCATION WITH 'DROM A=J' = 0
THEN DO AN 'AREAD' DISPATCH.
X1 0 - SET CRAM ADDR TO 0
CP 2 -THE 1ST INSTR SETS UP THE DBUS BITS AND ASSERTS SPEC IR
AND XR LOAD. THE 2ND INSTR LOADS THE IR WITH 110,
SELECTING A DROM LOCATION WITH 'DROM A=J' NEGATED.
WITH THE J FIELD = 17, THE AREAD DISPATCH SHOULD THEN
GO TO 57.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 57.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO CAUSE AN 'AREAD' DISPATCH FROM A DROM
LOACTION WHICH HAS 'DROM A=J' ASSERTED AND 'DROM 00-
03' = 5.
X1 0 - SET CRAM ADDR TO 0
CP 2 -THE 1ST INSTR SETS UP THE DBUS BITS AND ASSERTS SPEC IR
AND XR LOAD. THE 2ND INSTR LOADS THE IR WITH 324,
SELECTING A DROM LOCATION WITH 'DROM 00-03' = 5 AND
'DROM A=J' ASSERTED. WITH THE J FIELD = 17, THE
DROM DISPATCH SHOULD THEN GO TO 1537.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 1537.
!
[3
!STIMULUS:
LOAD MICRO-INSTR TO CAUSE AN 'AREAD' DISPATCH FROM A DROM
LOACTION WHICH HAS 'DROM A=J' ASSERTED AND 'DROM 00-
03' = 12.
X1 0 - SET CRAM ADDR TO 0
CP 2 -THE 1ST INSTR SETS UP THE DBUS BITS AND ASSERTS SPEC IR
AND XR LOAD. THE 2ND INSTR LOADS THE IR WITH 221,
SELECTING A DROM LOCATION WITH 'DROM 00-03' = 12 AND
'DROM A=J' ASSERTED. WITH THE J FIELD = 17, THE
DROM DISPATCH SHOULD THEN GO TO 1657.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT DISPATCH TO 1657.
!
]35
[1
!STIMULUS:
LOAD MICRO-INSTRS TO CAUSE A PAGE FAIL TRAP TO ADDR 7777.
X1 0 - SET CRAM ADDR = 0.
CP 7 - THE FIRST 5 INSTRS CLEAR ANY LEFT OVER PAGE FAULT
CONDITIONS AND LOAD A ZERO ENTRY INTO THE PAGE
TABLE AT PAGE -1. THE NEXT 2 INSTRS ATTEMPT A PAGED
MEMORY REFERENCE TO PAGE -1. THIS SHOULD CAUSE A PAGE
FAIL (SINCE 'PAGE VALID' IS NEGATED) WHICH SHOULD TRAP
THE CRAM ADDR TO 7777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT TRAP TO 7777.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO CAUSE A PAGE FAIL TRAP TO ADDR 7777 AND
THEN DO A RETURN FROM THERE.
X1 0 - SET CRAM ADDRESS = 0.
CP 7 - CAUSE THE PAGE FAIL AND TRAP TO ADDRESS 7777.
CP 1 - EXECUTE THE RETURN INSTR THERE. IF THE PAGE FAIL TRAP
WORKED CORRECTLY, IT WOULD HAVE DONE A PUSH ONTO THE
STACK. THEN THE RETURN WILL GO TO ADDR 6.
RESPONSE:
THE RETURN INSTR AT 7777 DID NOT GO TO ADDR 6.
!
]36
[1
!STIMULUS:
LOAD MICRO-INSTR TO DO 'ADL = 0' SKIP TO LOCATION 3776.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE INSTR WHICH ASSERTS 'DPE1 ADL=0' AND DOES
A 'ADL EQ 0' SKIP (SKIP FIELD = 32).
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
]37
[1
!STIMULUS:
LOAD MICRO-INSTR TO DO 'ADL SIGN' SKIP TO LOCATION 3776.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE INSTR WHICH ASSERTS 'DPE1 ADL SIGN' AND DOES
A 'ADL SIGN' SKIP (SKIP FIELD = 52).
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777.
!
]38
[1
!STIMULUS:
LOAD MICRO-INSTRS TO DO 2 'CALLS' AND A DISPATCH '\O0'.
WRT 204/2 - DO A STACK RESET
WRT 204/0
X1 0 - SET CRAM ADDRESS = 0.
CP 4 - THIS FIRST INSTR DOES A CALL TO LOCATION 1.
THE 2ND INSTR DOES A CALL TO LOCATION 2. THIS
SHOULD PUT A 1 AT THE TOP OF THE STACK. THE
3RD INSTR HAS A DISPATCH FIELD OF \O0 WHICH
SHOULD DO NOTHING. THE 4TH INSTR IS JUST
EXECUTED TO CLOCK THE 'SBR RET' REGISTER. THE
'SBR RET' SHOULD CONTAIN A 1.
RESPONSE:
THE 'SBR RET' DOES NOT CONTAIN A 1. THIS IMPLIES THAT THE
INSTR AT LOC 2 WITH DISPATCH FIELD \O0 INCORRECTLY ASSERTED
'CRA2 RETURN' THUS CAUSING THE STACK TO GET DECREMENTED.
!
]39
[1
!STIMULUS:
LOAD MICRO-INSTR TO ASSERT 'SPEC/CONSOLE' AND 'CRM2 # 14B'.
ASSERT AND NEGATE 'RESET'
X1 0 - SET CRAM ADDR = 0.
WRT 212/4 - ASSERT 'RUN' PRE-FLOP
CP 2 - THE 1ST CLOCK PULSE WILL EXECUTE THE MICRO-
INSTR TO ASSERT 'CRA2 SPEC/CONSOLE' AND 'CRM2
# 14B'. THIS WILL NEGATE THE 'RUN' PRE-FLOP.
AT THE SAME TIME THE 'RUN' FLOP WILL BE
ASSERTED. THE 2ND PULSE WILL CLOCK THE
NEGATED OUTPUT OF THE PRE-FLOP INTO THE 'RUN'
FLOP, THUS NEGATING 'RUN'.
RESPONSE:
'RUN (1)' DID NOT NEGATE. THIS IMPLIES THAT 'CRA2 SPEC/CONSOLE'
DID NOT ASSERT.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO NEGATE 'SPEC/CONSOLE' AND ASSERT
'CRM2 # 14B'.
ASSERT AND NEGATE 'RESET'
X1 0 - SET CRAM ADDR = 0.
WRT 212/4 - ASSERT 'RUN' PRE-FLOP
CP 2 - THE 1ST CLOCK PULSE WILL EXECUTE THE MICRO-
INSTR TO NEGATE 'CRA2 SPEC/CONSOLE' AND
ASSERT 'CRM2 # 14B'. THIS SHOULD NOT NEGATE
THE 'RUN' PRE-FLOP. AT THE SAME TIME THE
'RUN' FLOP WILL BE ASSERTED. THE 2ND PULSE
WILL CLOCK THE STILL ASSERTED OUTPUT OF THE
PRE-FLOP INTO THE 'RUN' FLOP, THUS LEAVING
'RUN' ASSERTED.
RESPONSE:
'RUN (1)' NEGATED. THIS IMPLIES THAT 'CRA2 SPEC/CONSOLE'
ASSERTED WHEN IT SHOULDN'T HAVE.
!
]40
[1
!STIMULUS:
LC 0 - SET CRAM ADDR = 0
DC \O000000000000000000000 - DEPOSIT TEST PATTERN INTO
BITS 0-35 OF CRAM. THIS SHOULD YIELD
VALID EVEN PARITY.
RESPONSE:
'CRA PARITY ERR' ASSERTED ON THE CSL BOARD.
!
[2
!STIMULUS:
LC 0 - SET CRAM ADDR = 0
DC \O000000000000000000000 - DEPOSIT TEST PATTERN INTO
BITS 0-35 OF CRAM. THIS SHOULD YIELD
INVALID ODD PARITY.
RESPONSE:
'CRA PARITY ERR' DID NOT ASSERT ON THE CSL BOARD.
!