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Trailing-Edge - PDP-10 Archives - klad_sources - klad.sources/dakaim.mac
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EXIT:	DROPDV			;CLOSE LOGICAL OUTPUT FILE
	EXIT

PGMNAM:	ASCIZ/
PDP-10 KA10 BASIC INSTRUCTION DIAGNOSTIC #9 SHIFT-ROTATE [DAKAI]
/

;INITIALIZE SUBROUTINES

START:	PGMINT
	MOVE	[ASCIZ/AI/]
	MOVEM	TLET

STARTA:	JRST	E00		;GO PERFORM DIAGNOSTIC
SUBTTL	DIAGNOSTIC SECTION - TEST FETCH, STORE AND DECODE FUNCTIONS

;TEST FETCH,STORE AND DECODE
;TEST THE ABILITY OF ROT, ROTC TO FETCH AND STORE
;AC,AC+1
;TESTING IS ACCOMPLISHED BY ROTATING ZERO TIMES ALL
;ZERO'S, ALL ONE'S.
;OPERANDS SELECTED ARE LEAST AFFECTED BY
;INADVERTENT ROTATING
;FAILURE OF A SC BIT TO SET,OR SC TO
;COUNT WILL RESULT IN LOOPING


	AC=1
E00:	SAVEAC	(1,1)

E100:	SETZ	AC,		;CLEAR AC
	ROT	AC,0		;*ROTATE LEFT ZERO TIMES
	SKIPE	AC		;TEST AC FOR ZERO
	ER3	AC,101		;FETCH OR STORE FAILED
	JUMPL	AC+2,E100	;LOOP ON ERROR SWITCH

E200:	SETOB	AC,AC-1		;SET AC,AC-1 FOR COMPARE
	ROT	AC,0		;*ROTATE LEFT ZERO TIMES
	CAME 	AC,AC-1		;TEST AC FOR A -1
	ER3	AC,201		;FETCH OR STORE FAILED
	JUMPL	AC+2,E200	;LOOP ON ERROR SWITCH

	AC=2
	SAVEAC	(1,1)

E300:	SETZB	AC,AC+1		;CLEAR AC,AC+1
	ROTC	AC,0		;*ROTATE COMBINED LEFT ZERO TIMES
	SKIPE	AC		;TEST AC FOR ZERO
	ER3	AC,301		;FETCH OR STORE AC FAILED
	SKIPE	AC+1		;TEST AC+1 FOR ZERO
	ER4	AC+1,301	;FETCH OR STORE AC+1 FAILED
	JUMPL	AC+2,E300	;LOOP ON ERROR SWITCH

E400:	SETO	AC-1,		;SET UP FOR COMPARISON
	SETOB	AC,AC+1		;SET AC,AC+1
	ROTC	AC,0		;*ROTATE COMBINED LEFT ZERO TIMES
	CAME	AC,AC-1		;TEST AC FOR A -1
	ER3	AC,401		;FETCH OR STORE AC FAILED
	CAME	AC+1,AC-1	;TEST AC+1 FOR A -1
	ER4	AC+1,401	;FETCH OR STORE AC+1 FAILED
	JUMPL	AC+2,E400	;LOOP ON ERROR SWITCH
;TEST FETCH,STORE AND DECODE
;TEST THE ABILITY OF LSH, LSHC TO FETCH AND STORE
;AC,AC+1
;TESTING IS ACCOMPLISHED BY SHIFTING ZERO TIMES ALL
;ZERO'S ALL ONE'S
;OPERANDS SELECTED ARE LEAST AFFECTED BY
;INADVERTENT SHIFTING
;FAILURE OF A SC BIT TO SET,OR SC TO
;COUNT WILL RESULT IN LOOPING

	AC=3
	SAVEAC	(1,1)

E500:	SETZ	AC,		;CLEAR AC
	LSH	AC,0		;*SHIFT LEFT ZERO TIMES
	SKIPE	AC		;TEST AC FOR ZERO
	ER3	AC,501		;FETCH OR STORE AC FAILED
	JUMPL	AC+2,E500	;LOOP ON ERROR SWITCH

E600:	SETOB	AC,AC-1		;SET AC,AC-1 FOR COMPARE
	LSH	AC,0		;*SHIFT LEFT ZERO TIMES
	CAME	AC,AC-1		;TEST AC FOR -1
	ER3	AC,601		;FETCH OR STORE AC FAILED
	JUMPL	AC+2,E600	;LOOP ON ERROR SWITCH

	AC=14
	SAVEAC	(1,1)

E700:	SETZB	AC,AC+1		;CLEAR AC,AC+1
	LSHC	AC,0		;*SHIFT COMBINED LEFT ZERO TIMES
	SKIPE	AC		;TEST AC FOR 0
	ER3	AC,701		;FETCH OR STORE AC FAILED
	SKIPE	AC+1		;TEST AC+1 FOR 0
	ER4	AC+1,701	;FETCH OR STORE AC+1 FAILED
	JUMPL	AC+2,E700	;LOOP ON ERROR SWITCH

E1000:	SETO	AC-1,		;SET UP FOR COMPARISON
	SETOB	AC,AC+1		;SET AC,AC+1
	LSHC	AC,0		;*SHIFT COMBINED LEFT ZERO TIMES
	CAME	AC,AC-1		;TEST AC FOR -1
	ER3	AC,1001		;FETCH OR STORE AC FAILED
	CAME	AC+1,AC-1	;TEST AC+1 FOR -1
	ER4	AC+1,1001	;FETCH OR STORE AC+1 FAILED
	JUMPL	AC+2,E1000	;LOOP ON ERROR SWITCH
;TEST FETCH,STORE AND DECODE
;TEST THE ABILITY OF ASH, ASHC TO FETCH AND STORE
;AC,AC+1
;TESTING IS ACCOMPLISHED BY SHIFTING ZERO TIMES ALL
;ZERO'S ALL ONES
;OPERANDS SELECTED ARE LEAST AFFECTED BY
;INADVERTENT SHIFTING
;FAILURE OF A SC BIT TO SET,OR SC TO
;COUNT WILL RESULT IN LOOPING

	AC=13
	SAVEAC	(1,1)

E1100:	SETZ	AC,		;CLEAR AC
	ASH	AC,0		;*SHIFT LEFT ZERO TIMES
	SKIPE	AC		;TEST AC FOR ZERO
	ER3	AC,1101		;FETCH OR STORE AC FAILED
	JUMPL	AC+2,E1100	;LOOP ON ERROR SWITCH

E1200:	SETOB	AC,AC-1		;SET AC,AC-1 FOR COMPARE
	ASH	AC,0		;*SHIFT LEFT ZERO TIMES
	CAME	AC,AC-1		;TEST AC FOR A -1
	ER3	AC,1201		;FETCH OR STORE AC FAILED
	JUMPL	AC+2,E1200	;LOOP ON ERROR SWITCH

	AC=12
	SAVEAC	(1,1)

E1300:	SETZB	AC,AC+1		;CLEAR AC,AC+1
	ASHC	AC,0		;*SHIFT COMBINED LEFT ZERO TIMES
	SKIPE	AC		;TEST AC FOR 0
	ER3	AC,1301		;FETCH OR STORE AC FAILED
	SKIPE	AC+1		;TEST AC+1 FOR 0
	ER4	AC+1,1301	;FETCH OR STORE AC+1 FAILED
	JUMPL	AC+2,E1300	;LOOP ON ERROR SWITCH

E1400:	SETO	AC-1,		;SET UP FOR COMPARISON
	SETOB	AC,AC+1		;SET AC,AC+1
	ASHC	AC,0		;*SHIFT COMBINED LEFT ZERO TIMES
	CAME	AC,AC-1		;TEST AC FOR A -1
	ER3	AC,1401		;FETCH OR STORE AC FAILED
	CAME	AC+1,AC-1	;TEST AC+1 FOR A -1
	ER4	AC+1,1401	;FETCH OR STORE AC+1 FAILED
	JUMPL	AC+2,E1400	;LOOP ON ERROR SWITCH
SUBTTL	DIAGNOSTIC SECTION - CHECK SIGN BIT OF AC+1 FOR ASHC

;VERIFY THAT THE SIGN BIT OF AC+1 IS NOT MADE TO AGREE WITH THE SIGN BIT OF AC
;WHEN THE 'E' FIELD OF ASHC SECIFIES A SHIFT OF ZERO BIT POSITIONS.
;HENCE, C(AC+1) IS NOT ALTERE BY 'ASHC AC,0'.
;CHECK THIS WHEN THE SIGN BIT OF AC IS ZERO AND THE SIGN BIT OF AC+1 IS ONE.

	SR2	(443,0,0,-1,-1,0,0,-1,-1,ASHC,0)

;VERIFY THAT THE SIGN BIT OF AC+1 IS NOT MADE TO AGREE WITH THE SIGN BIT OF AC
;WHEN THE 'E' FIELD OF ASHC SECIFIES A SHIFT OF ZERO BIT POSITIONS.
;HENCE, C(AC+1) IS NOT ALTERE BY 'ASHC AC,0'.
;CHECK THIS WHEN THE SIGN BIT OF AC IS ONE AND THE SIGN BIT OF AC+1 IS ZERO.
	SR2	(444,-1,-1,0,0,-1,-1,0,0,ASHC,0)
SUBTTL	DIAGNOSTIC SECTION - TEST MQ-ADDER GATING

	AC=10
	SAVEAC	(1,1)

SN=1500
	ZZ=0
			;CHECK AC+1 RIGHT <
E1500:	REPEAT	^D18,<

;VERIFY MQ-AD GATING
;ROTC A RIPPLED ONE ZERO POSITIONS IN AC+1
;FIRST CLEAR AC; THEN, SET ONE BIT OF AC+1
;REPEAT FOR ALL 36 BITS OF MQ
;RESULT IN AC+1 SHOULD BE SAME AS INTIALIZATION DATA
SN=SN+1
	ZZ=ZZ+ZZ			;TESTED BIT
	IFE	ZZ,<ZZ=1>
	SETZM	AC			;CLEAR AC
	MOVEI	AC+1,ZZ			;INITIALIZE AC+1
	ROTC	AC,0		;*ROT 0 BIT POSIOTIONS
	CAIE	AC+1,ZZ			;CHECK BIT (N) OF AC+1
	ER4	AC+1,SN			;MQ-AD GATE FAILED
	JUMPL	AC+2,.-5		;LOOP ON ERROR SWITCH
>
PAGE
ZZ=0
			;CHECK AC+1 LEFT <
	REPEAT	^D18,<

;VERIFY MQ-AD GATING
;ROTC A RIPPLED ONE ZERO POSITIONS IN AC+1
;FIRST CLEAR AC; THEN, SET ONE BIT OF AC+1
;REPEAT FOR ALL 36 BITS OF MQ
;RESULT IN AC+1 SHOULD BE SAME AS INITIALIZATION DATA
SN=SN+1
	ZZ=ZZ+ZZ			;TESTED BIT
	IFE	ZZ,<ZZ=1>
	SETZM	AC			;CLEAR AC
	MOVSI	AC+1,ZZ			;INITIALIZE AC+1
	MOVE	AC-1,AC+1		;SETUP FOR COMPARISON
	ROTC	AC,0		;*ROT 0 BIT POSITIONS
	CAME	AC+1,AC-1		;CHECK BIT (N) OF AC+1
	ER4	AC+1,SN			;MQ-AD GATE FAILED
	JUMPL	AC+2,.-5		;LOOP ON ERROR SWITCH
>
	AC=7
	SAVEAC	(1,1)

SN=1600

	ZZ=0

			;CHECK AC+1 RIGHT <
E1600:	REPEAT	^D18,<

;VERIFY MQ-AD GATING
;ROTC A RIPPLED ZERO ZERO POSITIONS IN AC+1
;FIRST SET AC TO ALL ONES; THEN, SET ALL BUT ONE BIT OF AC+1
;REPEAT FOR ALL 36 BITS OF MQ
;RESULT IN AC+1 SHOULD BE SAME AS INITIALIZATION DATA
SN=SN+1
	ZZ=ZZ+ZZ+1			;TESTED BIT
	IFE	ZZ,<ZZ=-2>
	SETOM	AC			;INITIALIZE TO ALL ONES
	HRROI	AC+1,ZZ&777777		;INITIALIZE AC+1
	MOVE	AC-1,AC+1		;SETUP FOR COMPARISON
	ROTC	AC,0		;*ROT 0 BIT POSITIONS
	CAME	AC+1,AC-1		;CHECK BIT (N) OF AC+1
	ER4	AC+1,SN			;MQ-AD GATE FAILED
	JUMPL	AC+2,.-6		;LOOP ON ERROR SWITCH
>
PAGE
ZZ=0
			;CHECK AC+1 LEFT <
	REPEAT	^D18,<

;VERIFY MQ-AD GATING
;ROTC A RIPPLED ZERO ZERO POSIOTIONS IN AC+1
;FIRST SET AC TO ALL ONES; THEN, SET ALL BUT ONE BIT OF AC+1
;REPEAT FOR ALL 36 BITS OF MQ
;RESULT IN AC+1 SHOULD BE SAME AS INITIALIZATION DATA
SN=SN+1
	ZZ=ZZ+ZZ+1			;TESTED BIT
	IFE	ZZ,<ZZ=-2>
	SETOM	AC			;INITIALIZE	AC TO ALL ONES
	HRLOI	AC+1,ZZ&777777		;INITIALIZE AC+1
	MOVE	AC-1,AC+1		;SETUP FOR COMPARISON
	ROTC	AC,0		;*ROT 0 BIT POSITIONS
	CAME	AC+1,AC-1		;CHECK BIT (N) OF AC+1
	ER4	AC+1,SN			;MQ-AD GATE FAILED
	JUMPL	AC+2,.-6		;LOOP ON ERROR SWITCH
>
SUBTTL	DIAGNOSTIC SECTION - BASIC SHIFT TEST (0,1,-1,-2 BIT POSITIONS)

;BASIC SHIFT TEST
;TEST ABILITY TO SHIFT A BIT 0,1,-1 AND -2 POSITIONS

	AC=4
	SAVEAC	(1,1)

;TEST ABILITY TO SHIFT A BIT ZERO POSITIONS USING LSH
	SR1	(17,0,10,0,10,LSH,0)

;TEST ABILITY TO SHIFT A BIT LEFT ONE POSITION USING LSH
	SR1	(20,0,10,0,20,LSH,1)

;TEST ABILITY TO SHIFT A BIT RIGHT ONE POSITION USING LSH
	SR1	(442,0,10,0,4,LSH,-1)

;TEST ABILITY TO SHIFT A BIT RIGHT TWO POSITIONS USING LSH
	SR1	(21,0,10,0,2,LSH,-2)
PAGE
;TEST ABILITY TO SHIFT A BIT ZERO POSITIONS USING LSHC
	SR2	(22,0,10,0,10,0,10,0,10,LSHC,0)

;TEST ABILITY TO SHIFT A BIT LEFT ONE POSITION USING LSHC
	SR2	(23,0,10,0,10,0,20,0,20,LSHC,1)

;TEST ABILITY TO SHIFT A BIT RIGHT ONE POSITION USING LSHC
	SR2	(24,0,10,0,10,0,4,0,4,LSHC,-1)

;TEST ABILITY TO SHIFT A BIT RIGHT TWO POSITIONS USING LSHC
	SR2	(25,0,10,0,10,0,2,0,2,LSHC,-2)
SUBTTL	DIAGNOSTIC SECTION - TEST SAC FUNCTION

	AC=10
	SAVEAC	(1,1)

SN=2600
	ZZ=1

		;TEST SAC
E2600:	REPEAT	^D3,<
SN=SN+1
;FURTHER TEST OF SAC,SAC2
;TEST FOR ASSERTION OF SAC INH
;TEST ASSUMES ABILITY TO ROTATE
;TO SOME DEGREE
	ZZ=ZZ+ZZ
	HRRZI	AC,400000	;SET BIT 18
	ROT	AC,ZZ		;*ROT LEFT (N) NUMBER OF TIMES
	CAIN	AC,400000	;TEST FOR SAC
	ER3	AC,SN		;STORE AC FAILED
	JUMPL	AC+2,.-4	;LOOP ON ERROR SWITCH
>
PAGE
SN=2700
	ZZ=1

		;TEST SAC
E2700:	REPEAT	^D3,<
SN=SN+1
;FURTHER TEST OF SAC,SAC2
;TEST FOR ASSERTION OF SAC INH
;TEST ASSUMES ABILITY TO ROTATE
;TO SOME DEGREE

	ZZ=ZZ+ZZ
	SETZ	AC,		;CLEAR AC
	HRRZI	AC+1,400000	;SET BIT 18
	ROTC	AC,ZZ		;*ROT LEFT (N) NUMBER OF TIMES
	CAIN	AC+1,400000	;TEST FOR SAC
	ER4	AC+1,SN		;STORE AC+1 FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
SUBTTL	DIAGNOSTIC SECTION - TEST SHIFT LOGIC GATES BETWEEN AD AND AR

;TEST ROT LEFT ONE BIT POSITION USING ALL ZEROS
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF C(AC) IS NON-ZERO AFTER ROTATING

	AC=11
	SAVEAC	(1,1)

E3000:	SETZB	AC,AC-1		;INITIALIZE AC AND EXPECTED RESULT TO ZERO
	ROT	AC,1		;*ROTATE LEFT ONE
	CAME	AC,AC-1		;TEST AC FOR ALL ZEROS
	ER3	AC,3001		;AD-AR GATING FAILED
	JUMPL	AC+2,E3100	;LOOP ON ERROR SWITCH

;TEST ROT LEFT ONE BIT POSITION USING ALL ONES
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF C(AC) IS NOT ALL ONES AFTER ROTATING

E3100:	SETOB	AC,AC-1		;INITIALIZE AC AND EXPECTED RESULT TO ALL ONES
	ROT	AC,1		;*ROTATE LEFT ONE
	CAME	AC,AC-1		;TEST AC FOR ALL ONES
	ER3	AC,3101		;AD-AR GATING FAILED
	JUMPL	AC+2,E3100	;LOOP ON ERROR SWITCH
SN=3200
	ZZ=0

		;TEST AC RIGHT HALF <
E3200:	REPEAT 	^D18,<
;TEST ROT LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY OTHER BIT 
;IS ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS

SN=SN+1
	ZZ=ZZ+ZZ		;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=1>
	YY=ZZ+ZZ		;SELECTED BIT AFTER ROTATION
	MOVEI	AC,ZZ		;SET BIT (N) OF AC RIGHT
	IFN	<ZZ-400000>,<
	MOVEI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-400000>,<
	MOVSI	AC-1,1		;SETUP FOR COMPARISON>
	ROT	AC,1		;*ROTATE LEFT ONE
	CAME	AC,AC-1		;TEST FOR BIT (N-1) A ONE
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=0

		;TEST AC LEFT HALF <
	REPEAT	^D18,<;TEST ROT LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY OTHER BIT IS
;ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS

SN=SN+1

	ZZ=ZZ+ZZ		;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=1>
	YY=ZZ+ZZ		;SELECTED BIT AFTER ROTATION
	MOVSI	AC,ZZ		;SET BIT (N) OF AC LEFT
	IFN	<ZZ-400000>,<
	MOVSI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-400000>,<
	MOVEI	AC-1,1		;SETUP FOR COMPARISON>
	ROT	AC,1		;*ROTATE LEFT ONE
	CAME	AC,AC-1		;TEST FOR BIT (N-1) A ONE
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
SN=3300
	ZZ=0

	;TEST AC RIGHT HALF<
E3300:	REPEAT	^D18,<;TEST ROT LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ONE AND/OR ANY OTHER BIT
;IS ZERO AFTER ROTATING.
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS

SN=SN+1
	ZZ=ZZ+ZZ+1		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ-1>,<ZZ=-2>
	YY=<ZZ+ZZ+1>&777777	;SELECTED BIT AFTER ROTATION
	HRROI	AC,ZZ&777777	;CLEAR BIT (N) OF AC RIGHT
	IFN	<<ZZ-377777>&377777>,<
	HRROI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<<ZZ-377777>&777777>,<
	HRLOI	AC-1,-2		;SETUP FOR COMPARISON>
	ROT	AC,1		;*ROTATE LEFT ONE
	CAME	AC,AC-1		;TEST FOR BIT (N-1) A ZERO
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=0
	;TEST AC LEFT HALF<
	REPEAT	^D18,<;TEST ROT LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ONE AND/OR ANY OTHER BIT
;IS ZERO AFTER ROTATING.
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS

SN=SN+1
	ZZ=ZZ+ZZ+1		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ-1>,<ZZ=-2>
	YY=<ZZ+ZZ+1>&777777	;SELECTED BIT AFTER ROTATION
	HRLOI	AC,ZZ&777777	;CLEAR BIT (N) OF AC LEFT
	IFN	<<ZZ-377777>&777777>,<
	HRLOI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<<ZZ-377777>&777777>,<
	HRROI	AC-1,-2		;SETUP FOR COMPARISON>
	ROT	AC,1		;*ROTATE LEFT ONE
	CAME	AC,AC-1		;TEST FOR BIT (N-1) OR ZERO
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
;TEST ROT RIGHT ONE BIT POSITION
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD.
;AN ERROR OCCURS IF C(AC) IS NON-ZERO AFTER ROTATING

	AC=10
	SAVEAC	(1,1)

E3400:	SETZB	AC,AC-1		;INITIALIZE AC AND EXPECTED RESULT TO ZERO
	ROT	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC,AC-1		;TEST AC FOR ALL ZEROS
	ER3	AC,3401		;AD-AR GATING FAILED
	JUMPL	AC+2,E3400	;LOOP ON ERROR SWITCH

;TEST ROT RIGHT ONE BIT POSITION
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF C(AC) IS NOT ALL ONES AFTER ROTATING

E3500:	SETOB	AC,AC-1		;INITIALIZE AC AND EXPECTED RESULT TO ALL ONES
	ROT	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC,AC-1		;TEST AC FOR ALL ONES.
	ER3	AC,3501		;AD-AR GATING FAILED
	JUMPL	AC+2,E3500	;LOOP ON ERROR SWITCH
SN=3600
	ZZ=0

		;TEST AC LEFT HALF<
E3600:	REPEAT	^D18,<;TEST ROT RIGHT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY OTHER
;BIT IS ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	YY=ZZ/2			;SELECTED BIT AFTER ROTATION
	MOVSI	AC,ZZ		;SET BIT (N) OF AC LEFT
	IFN	<ZZ-1>,<
	MOVSI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-1>,<
	MOVEI	AC-1,400000	;SETUP FOR COMPARISON>
	ROT	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC,AC-1		;TEST FOR BIT (N+1) A ONE
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=0

		;TEST AC RIGHT HALF<
	REPEAT	^D18,<;TEST ROT RIGHT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY OTHER BIT IS
;ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	YY=ZZ/2			;SELECTED BIT AFTER ROTATION
	MOVEI	AC,ZZ		;SET BIT (N) OF AC RIGHT
	IFN	<ZZ-1>,<
	MOVEI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-1>,<
	MOVSI	AC-1,400000	;SETUP FOR COMPARISON>
	ROT	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC,AC-1			;TEST FOR BIT (N+1) A ONE
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
SN=3700
	ZZ=1

	;TEST AC LEFT HALF<
E3700:	REPEAT	^D18,<;TEST ROT RIGHT ONE BIT POSITION
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ONE AND/OR ANY OTHER BIT
;IS ZERO AFTER ROTATING.
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS

SN=SN+1
	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-1>/2>&777777	;SELECTED BIT AFTER ROTATION
	HRLOI	AC,ZZ&777777	;CLEAR BIT (N) OF AC LEFT
	IFN	<ZZ&777777-777776>,<
	HRLOI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ&777777-777776>,<
	HRROI	AC-1,377777	;SETUP FOR COMPARISON>
	ROT	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC,AC-1		;TEST FOR BIT (N+1) A ZERO
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=1

	;TEST AC RIGHT HALF<
	REPEAT	^D18,<;TEST ROT RIGHT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ONE AND/OR ANY OTHER BIT
;IS ZERO AFTER ROTATING.
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS

SN=SN+1
	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-1>/2>&777777	;SELECTED BIT AFTER ROTATION
	HRROI	AC,ZZ&777777	;CLEAR BIT (N) OF AC RIGHT
	IFN	<ZZ&777777-777776>,<
	HRROI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ&777777-777776>,<
	HRLOI	AC-1,377777	;SETUP FOR COMPARISON>
	ROT	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC,AC-1		;TEST FOR BIT (N+1) A ZERO
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
;TEST ROT RIGHT TWO BIT POSITIONS
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF C(AC) IS NON-ZERO AFTER ROTATING

	AC=7
	SAVEAC	(1,1)

E4000:	SETZB	AC,AC-1		;INITIALIZE AC AND EXPECTED RESULT TO ZERO
	ROT	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC,AC-1		;TEST AC FOR ALL ZEROS
	ER3	AC,4001		;AD-AR GATING FAILED
	JUMPL	AC+2,E4000	;LOOP ON ERROR SWITCH

;TEST ROT RIGHT TWO BIT POSITIONS
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF C(AC) IS NOT ALL ONES AFTER ROTATING

E4100:	SETOB	AC,AC-1		;INITIALIZE AC AND EXPECTED RESULT TO ALL ONES
	ROT	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC,AC-1		;TEST AC FOR ALL ONES.
	ER3	AC,4101		;AD-AR GATING FAILED
	JUMPL	AC+2,E4100	;LOOP ON ERROR SWITCH
SN=4200
	ZZ=0

		;TEST AC LEFT HALF<
E4200:	REPEAT	^D18,<;TEST ROT RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ONE GHROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY OTHER
;BIT IS ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	YY=ZZ/4			;SELECTED BIT AFTER ROTATION
	MOVSI	AC,ZZ		;SET BIT (N) OF AC LEFT
	IFG	<ZZ-2>,<
	MOVSI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-2>,<
	MOVEI	AC-1,400000	;SETUP FOR COMPARISON>
	IFE	<ZZ-1>,<
	MOVEI	AC-1,200000	;SETUP FOR COMPARISON>
	ROT	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC,AC-1		;TEST FOR BIT (N+2) A ONE
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=0

		;TEST AC RIGHT HALF <
	REPEAT	^D18,<;TEST ROT RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY OTHER BIT IS
;ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	YY=ZZ/4			;SELECTED BIT AFTER ROTATION
	MOVEI	AC,ZZ		;SET BIT (N) OF AC RIGHT
	IFG	<ZZ-2>,<
	MOVEI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-2>,<
	MOVSI	AC-1,400000	;SETUP FOR COMPARISON>
	IFE	<ZZ-1>,<
	MOVSI	AC-1,200000	;SETUP FOR COMPARISON>
	ROT	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC,AC-1		;TEST FOR BIT (N+2) A ONE
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
SN=4300
	ZZ=1

		;TEST AC LEFT HALF<
E4300:	REPEAT	^D18,<;TEST ROT RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ONE AND/OR ANY OTHER BIT
;IS ZERO AFTER ROTATING.
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS

SN=SN+1
	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-3>/4>&777777	;SELECTED BIT AFTER ROTATION
	HRLOI	AC,ZZ&777777	;CLEAR BIT (N) OF AC LEFT
	IFL	<ZZ&777777-777775>,<
	HRLOI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ&777777-777775>,<
	HRROI	AC-1,377777	;SETUP FOR COMPARISON>
	IFE	<ZZ&777777-777776>,<
	HRROI	AC-1,577777	;SETUP FOR COMPARISON>
	ROT	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC,AC-1		;TEST FOR BIT (N+2) A ZERO
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=1

		;TEST AC RIGHT HALF<
	REPEAT	^D18,<;TEST ROT RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE AR
;TEST SHIFT LOGIC GATES BETWEEN AR AND AD
;AN ERROR OCCURS IF THE TESTED BIT IS ONE AND/OR ANY OTHER BIT
;IS ZERO AFTER ROTATING.
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS

SN=SN+1
	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-3>/4>&777777	;SELECTED BIT AFTER ROTATION
	HRROI	AC,ZZ&777777	;CLEAR BIT (N) OF AC RIGHT
	IFL	<ZZ&777777-777775>,<
	HRROI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ&777777-777775>,<
	HRLOI	AC-1,377777	;SETUP FOR COMPARISON>
	IFE	<ZZ&777777-777776>,<
	HRLOI	AC-1,577777	;SETUP FOR COMPARISON>
	ROT	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC,AC-1		;TEST FOR BIT (N+1) A ZERO
	ER3	AC,SN		;AD-AR GATE UNDER TEST FAILED
	JUMPL	AC+2,.-5	;LOOP ON ERROR SWITCH
>
SUBTTL	DIAGNOSTIC SECTION - TEST MQ SHIFT LOGIC GATES

;TEST ROTC LEFT ONE BIT POSITION USING ALL ZEROS
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED LEFT ONE BIT POSITION AND
;AC+1 IS TESTED
;AN ERROR OCCURS IF C(AC+1) IS NON-ZERO AFTER ROTATING

	AC=10
	SAVEAC	(1,1)

E4400:	SETZB	AC,AC+1		;INITIALIZE AC,AC+1 TO ALL ZEROS
	SETZM	AC-1		;INITIALIZE RESULT TO ZERO
	ROTC	AC,1		;*ROTATE LEFT ONE
	CAME	AC+1,AC-1	;TEST AC+1 FOR ALL ZEROS
	ER4	AC+1,4401	;MQ GATING FAILED
	JUMPL	AC+2,E4400	;LOOP ON ERROR SWITCH

;TEST ROTC LEFT ONE BIT POSITION USING ALL ONES
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED LEFT ONE BIT POSITION AND
;AC+1 IS TESTED
;AN ERROR OCCURS IF C(AC+1) IS NON-ZERO AFTER ROTATING

E4500:	SETOB	AC,AC+1		;INITIALIZE AC,AC+1 TO ALL ONES
	SETOM	AC-1		;INITIALIZE RESULT TO ALL ONES
	ROTC	AC,1		;*ROTATE LEFT ONE
	CAME	AC+1,AC-1	;TEST AC+1 FOR ALL ONES
	ER4	AC+1,4501	;MQ GATING FAILED
	JUMPL	AC+2,E4500	;LOOP ON ERROR SWITCH
SN=4600
	ZZ=0

		;TEST AC+1 RIGHT HALF <
E4600:	REPEAT	^D18,<;TEST ROTC LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED LEFT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY
;OTHER BIT IS A ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=ZZ+ZZ		;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=1>
	YY=ZZ+ZZ		;SELECTED BIT AFTER ROTATION
	SETZ	AC,		;INITILAIZE AC TO ALL ZEROS
	MOVEI	AC+1,ZZ		;SET BIT (N) OF AC+1 RIGHT
	IFN	<ZZ-400000>,<
	MOVEI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-400000>,<
	MOVSI	AC-1,1		;SETUP FOR COMPARISON>
	ROTC	AC,1		;*ROTATE LEFT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N-1) A ONE
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>

	ZZ=0

		;TEST AC+1 LEFT HALF <
	REPEAT	^D17,<;TEST ROTC LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED LEFT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY
;OTHER BIT IS A ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=ZZ+ZZ		;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=1>
	YY=ZZ+ZZ		;SELECTED BIT AFTER ROTATION
	SETZ	AC,		;INITIALIZE AC TO ALL ZEROS
	MOVSI	AC+1,ZZ		;SET BIT (N) OF AC+1 LEFT
	MOVSI	AC-1,YY		;SETUP FOR COMPARISON
	ROTC	AC,1		;*ROTATE LEFT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N-1) A ONE
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
SN=4700
	ZZ=0
		;TEST AC+1 RIGHT HALF <
E4700:	REPEAT	^D18,<;TEST ROTC LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED LEFT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IA A ONE AND/OR ANY
;OTHER BIT IA A ZERO AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=ZZ+ZZ+1		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ-1>,<ZZ=-2>
	YY=<ZZ+ZZ+1>&777777	;SELECTED BIT AFTER ROTATION
	SETOM	AC		;INITIALIZE AC TO ALL ONES
	HRROI	AC+1,ZZ		;CLEAR BIT (N) OF AC+1 RIGHT
	IFN	<ZZ-377777>&777777,<
	HRROI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-377777>&777777,<
	HRLOI	AC-1,-2		;SETUP FOR COMPARISON>
	ROTC	AC,1		;*ROTATE LEFT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N-1) A ZERO
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=0

		;TEST AC+1 LEFT HALF <
	REPEAT	^D17,<;TEST ROTC LEFT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC, AC+1 ARE ROTATED LEFT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS A ONE AND/OR ANY
;OTHER BIT IS A ZERO AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS
;OF THE MQ

SN=SN+1
	ZZ=ZZ+ZZ+1		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ-1>,<ZZ=-2>
	YY=<ZZ+ZZ+1>&777777	;SELECTED BIT AFTER ROTATION
	SETOM	AC		;INITAILIZE AC TO ALL ONES
	HRLOI	AC+1,ZZ&777777	;CLEAR BIT (N) OF AC+1 RIGHT
	HRLOI	AC-1,YY		;SETUP FOR COMPARISON
	ROTC	AC,1		;*ROTATE LEFT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N-1) A ZERO
	ER4	AC+1,		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
;TEST ROTC RIGHT ONE BIT POSITION USING ALL ZEROS
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT ONE BIT POSITION AND
;AC+1 IS TESTED
;AN ERROR OCCURS IF C(AC+1) IS NON-ZERO AFTER ROTATING

	AC=7
	SAVEAC	(1,1)

E5000:	SETZB	AC,AC+1		;INITIALIZE AC,AC+1 TO ALL ZEROS
	SETZM	AC-1		;INITIALIZE RESULT TO ZERO
	ROTC	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC+1,AC-1	;TEST AC+1 FOR ALL ZEROS
	ER4	AC+1,5001	;MQ GRTING FAILED
	JUMPL	AC+2,E5000	;LOOP ON ERROR SWITCH

;TEST ROTC,RIGHT ONE BIT POSITION USING ALL ONES
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT ONE BIT POSITION AND
;AC+1 IS TESTED
;AN ERROR OCCURS IF C(AC+1) IS NONZERO AFTER ROTATING

E5100:	SETOB	AC,AC+1		;INITIALIZE AC,AC+1	TO ALL ONES
	SETOM	AC-1		;INITIALIZE RESULT TO ALL ONES
	ROTC	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC+1,AC-1	;TEST AC+1 FOR ALL ONES
	ER4	AC+1,5101	;MQ GATING FAILED
	JUMPL	AC+2,E5100	;LOOP ON ERROR SWITCH
SN=5200
	ZZ=0
		;TEST AC+1 LEFT HALF<
E5200:	REPEAT	^D18,<;TEST ROTC RIGHT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES

;AC,AC+1 ARE ROTATED RIGHT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY
;OTHER BIT IS A ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	YY=ZZ/2			;SELECTED BIT AFTER ROTATION
	SETZ	AC,		;INITIALIZE AC TO ALL ZEROS
	MOVSI	AC+1,ZZ		;SET BIT (N) OF AC+1 LEFT
	IFN	<ZZ-1>,	<
	MOVSI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-1>,<
	MOVEI	AC-1, 400000	;SETUP FOR COMPARISON>
	ROTC	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N+1) A ONE
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH.
>
PAGE
	ZZ=0

		;TEST AC+1 RIGHT HALF<
	REPEAT	^D17,<;TEST ROTC RIGHT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY
;OTHER BIT IS A ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	
	YY=ZZ/2			;SELECTED BIT AFTER ROTATION
	SETZ	AC,		;INITIALIZE AC TO ALL ZEROS
	MOVEI	AC+1,ZZ		;SET BIT (N) OF AC+1 RIGHT
	MOVEI	AC-1,YY		;SETUP FOR COMPARISON
	ROTC	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N+1) A ONE
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
SN=5300
	ZZ=1

		;TEST AC+1 LEFT HALF<
E5300:	REPEAT	^D18,<;TEST ROTC RIGHT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS A ONE AND/OR ANY
;OTHER BIT IS A ZERO AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-1>/2>&777777	;SELECTED BIT AFTER ROTATION
	SETOM	AC		;INITIALIZE AC TO ALL CNES
	HRLOI	AC+1,ZZ&777777	;SETUP BIT (N) OF AC+1 LEFT
	IFN	<ZZ-777776>&777777,<
	HRLOI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-777776>&777777,<
	HRROI	AC-1,377777	;SETUP FOR COMPARISON>
	ROTC	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N+1) A ZERO
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH.
>
PAGE
	ZZ=1

		;TEST AC+1 RIGHT HALF<
	REPEAT	^D17,<;TEST ROTC RIGHT ONE BIT POSITION
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT ONE BIT POSITION AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS A ONE AND/OR ANY
;OTHER BIT IS A ZERO AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-1>/2>&777777	;SELECTED BIT AFTER ROTATION
	SETOM	AC		;INITIALIZE AC TO ALL CNES
	HRROI	AC+1,ZZ&777777	;CLEAR BIT (N) OF AC+1 RIGHT
	HRROI	AC-1,YY		;SETUP FOR COMPARISON
	ROTC	AC,-1		;*ROTATE RIGHT ONE
	CAME	AC+1,AC-1	;TEST FOR BIT (N+1) A ZERO
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
;TEST ROTC RIGHT TWO BIT POSITIONS USING ALL ZEROS
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT TWO BIT POSITIONS AND
;AC+1 IS TESTED
;AN ERROR OCCURS IF C(AC+1) IS NON-ZERO AFTER ROTATING

	AC=6
	SAVEAC	(1,1)
E5400:
	SETZB	AC,AC+1		;INITIALIZE AC,AC+1 TO ALL ZEROS
	SETZM	AC-1		;INITIALIZE RESULT TO ZERO
	ROTC	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC+1,AC-1	;TEST AC+1 FOR ALL ZEROS
	ER4	AC+1,5401	;MQ GATING FAILED
	JUMPL	AC+2,E5400	;LOOP ON ERROR SWITCH

;TEST ROTC RIGHT TWO BIT POSITIONS USING ALL ONES
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT TWO BIT POSITIONS AND
;AC+1 IS TESTED
;AN ERROR OCCURS IF C(AC+1) IS ZERO AFTER ROTATING

E5500:	SETOB	AC,AC+1		;INITIALIZE AC,AC+1 TO ALL ONES
	SETOM	AC-1		;INITIALIZE RESULT TO ALL ONES
	ROTC	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC+1,AC-1	;TEST AC+1 FOR ALL ONES
	ER4	AC+1,5501	;MQ GATING FAILED
	JUMPL	AC+2,E5500	;LOOP ON ERROR SWITCH
SN=5600
	ZZ=0

		;TEST AC+1 LEFT HALF<
E5600:	REPEAT	^D18,<;TEST ROTC RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC,AC+1 ARE ROTATED RIGHT TWO BIT POSITIONS AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY
;OTHER BIT IS A ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	YY=ZZ/4			;SELECTED BIT AFTER ROTATION
	SETZ	AC,		;INITIALIZE AC TO ALL ZEROS
	MOVSI	AC+1,ZZ		;SET BIT (N) OF AC+1 LEFT
	IFG	<ZZ-2,>,<
	MOVSI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-2>,<
	MOVEI	AC-1,400000	;SETUP FOR COMPARISON>
	IFE	<ZZ-1>,<
	MOVEI	AC-1,200000	;SETUP FOR COMPARISON>
	ROTC	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC+1,AC-1	;TEST FOR BIT (N+2) A ONE
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=0

		;TEST AC+1 RIGHT HALF<
	REPEAT	^D16,<;TEST ROTC RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ONE THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC, AC+1 ARE ROTATED RIGHT TWO BIT POSITIONS AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS ZERO AND/OR ANY
;OTHER BIT IS A ONE AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ONE THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=ZZ/2			;SELECTED BIT BEFORE ROTATION
	IFE	ZZ,<ZZ=400000>
	YY=ZZ/4			;SELECTED BIT AFTER ROTATION
	SETZ	AC,		;INITIALIZE AC TO ALL ZEROS
	MOVEI	AC+1,ZZ		;SET BIT (N) OF AC+1 RIGHT

	MOVEI	AC-1,YY		;SETUP FOR COMPARISON
	ROTC	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC+1,AC-1	;TEST FOR BIT (N+2) A ONE
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
SN=5700
	ZZ=1

 		;TEST AC+1 LEFT HALF <
E5700:	REPEAT ^D18,<;TEST ROTC RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC, AC+1 ARE ROTATED RIGHT TWO BIT POSITIONS AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS A ONE AND/OR ANY
;OTHER BIT IS A ZERO AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS OF THE MQ

SN=SN+1

	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-3>/4>&777777	;SELECTED BIT AFTER ROTATION
	SETOM	AC		;INITIALIZE AC TO ALL ONES
	HRLOI	AC+1,ZZ&777777	;CLEAR BIT (N) OF AC+1 LEFT
	IFG	<ZZ-777775>&777777,<
	HRLOI	AC-1,YY		;SETUP FOR COMPARISON>
	IFE	<ZZ-777775>&777777,<
	HRROI	AC-1,377777	;SETUP FOR COMPARISON>
	IFE	<ZZ-777776>&777777,<
	HRROI	AC-1,577777	;SETUP FOR COMPARISON>
	ROTC	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC+1,AC-1	;TEST FOR BIT (N+2) A ZERO
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
PAGE
	ZZ=1

		;TEST AC+1 RIGHT HALF<
	REPEAT ^D16,<;TEST ROTC RIGHT TWO BIT POSITIONS
;TEST ABILITY TO ROTATE A ZERO THROUGH THE 36 BITS OF THE MQ
;TEST MQ SHIFT LOGIC GATES
;AC, AC+1 ARE ROTATED RIGHT TWO BIT POSITIONS AND AC+1
;IS TESTED.
;AN ERROR OCCURS IF THE TESTED BIT IS A ONE AND/OR ANY
;OTHER BIT IS A ZERO AFTER ROTATING
;THIS TEST IS REPEATED 36 TIMES TO RIPPLE A ZERO THROUGH ALL 36 BITS OF THE MQ

SN=SN+1
	ZZ=<ZZ-1>/2		;SELECTED BIT BEFORE ROTATION
	IFE	<ZZ>,<ZZ=777777377777>
	YY=<<ZZ-3>/4>&777777	;SELECTED BIT AFTER ROTATION
	SETOM	AC		;INITIALIZE AC TO ALL ONES
	HRROI	AC+1,ZZ&777777	;CLEAR BIT (N) OF AC+1 RIGHT
	HRROI	AC-1,YY		;SETUP FOR COMPARISON
	ROTC	AC,-2		;*ROTATE RIGHT TWO
	CAME	AC+1,AC-1	;TEST FOR BIT (N+2) A ZERO
	ER4	AC+1,SN		;MQ GATE UNDER TEST FAILED
	JUMPL	AC+2,.-6	;LOOP ON ERROR SWITCH
>
SUBTTL	DIAGNOSTIC SECTION - END CONNECTIONS TEST (ROT)

;END CONNECTIONS-ROT
;TEST AR END BIT INPUT GATES
;TEST LEFT-AR0,1,34,35 SHLT INP GATES
;TEST RIGHT-AR0,1,34,35 SHRT INP GATES
;AC IS ROTATED LEFT/RIGHT
;AND END BITS TESTED

;SHIFT CONNECTIONS TEST
;TEST AR35 SHLT INP-ONE'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR1	(60,400000,0,0,1,ROT,1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHLT INP-ZERO'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR
	SR1	(61,377777,-1,-1,-2,ROT,1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ONE'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR
	SR1	(62,0,1,0,2,ROT,1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ZERO'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR1	(63,-1,-2,-1,-3,ROT,1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ONE'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR1	(64,100000,0,200000,0,ROT,1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ZERO'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR1	(65,677777,-1,577777,-1,ROT,1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ONE'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR1	(66,200000,0,400000,0,ROT,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ZERO'S - ROT AC,1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR1	(67,577777,-1,377777,-1,ROT,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ONE'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR1	(70,0,1,400000,0,ROT,-1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR1	(71,-1,-2,377777,-1,ROT,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ONE'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR1	(72,400000,0,200000,0,ROT,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR1	(73,377777,-1,577777,-1,ROT,-1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR1	(74,0,4,0,2,ROT,-1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR1	(75,-1,-5,-1,-3,ROT,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR1	(76,0,2,0,1,ROT,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - ROT AC,-1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR1	(77,-1,-3,-1,-2,ROT,-1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ONE'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR1	(100,0,2,400000,0,ROT,-2)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR1	(101,-1,-3,377777,-1,ROT,-2)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ONE'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR1	(102,0,1,200000,0,ROT,-2)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR1	(103,-1,-2,577777,-1,ROT,-2)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR1	(104,0,10,0,2,ROT,-2)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR1	(105,-1,-11,-1,-3,ROT,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR1	(106,0,4,0,1,ROT,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - ROT AC,-2
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR1	(107,-1,-5,-1,-2,ROT,-2)

SUBTTL	DIAGNOSTIC SECTION - END CONNECTIONS TEST (LSH)

;END CONNECTIONS-LSH
;TEST AR END BIT INPUT GATES
;TEST LEFT-AR0,1,34,35 SHLT INP GATES
;TEST RIGHT-AR0,1,34,35 SHRT INP GATES
;AC IS SHIFTED LEFT/RIGHT
;AND END BITS TESTED

;SHIFT CONNECTIONS TEST
;TEST AR35 SHLT INP-ZERO'S - LSH AC,1
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR
	SR1	(110,-1,-1,-1,-2,LSH,1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ONE'S - LSH AC,1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR
	SR1	(111,0,1,0,2,LSH,1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ZERO'S - LSH AC,1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(112,-1,-2,-1,-4,LSH,1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ONE'S - LSH AC,1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(113,100000,0,200000,0,LSH,1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ZERO'S - LSH AC,1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(114,677777,-1,577777,-2,LSH,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ONE'S - LSH AC,1
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(115,200000,0,400000,0,LSH,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ZERO'S - LSH AC,1
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(116,577777,-1,377777,-2,LSH,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - LSH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(117,-1,-1,377777,-1,LSH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ONE'S - LSH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(120,400000,0,200000,0,LSH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - LSH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(121,377777,-1,177777,-1,LSH,-1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - LSH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(122,0,4,0,2,LSH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - LSH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(123,-1,-5,377777,-3,LSH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - LSH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(124,0,2,0,1,LSH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - LSH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(125,-1,-3,377777,-2,LSH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - LSH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(126,-1,-1,177777,-1,LSH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - LSH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(127,-1,-1,177777,-1,LSH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - LSH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(130,0,10,0,2,LSH,-2)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - LSH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(131,-1,-11,177777,-3,LSH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - LSH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(132,0,4,0,1,LSH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - LSH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(133,-1,-5,177777,-2,LSH,-2)
SUBTTL	DIAGNOSTIC SECTION - END CONNECTIONS TEST (ASH)

;END CONNECTIONS-ASH
;TEST AR END BIT INPUT GATES
;TEST LEFT-AR0,1,34,35 SHLT INP GATES
;TEST RIGHT-AR0,1,34,35 SHRT INP GATES
;AC IS SHIFTD LEFT/RIGHT
;AND END BITS TESTED

;SHIFT CONNECTIONS TEST
;TEST AR35 SHLT INP-ZERO'S - ASH AC,1
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR
	SR1	(134,-1,-1,-1,-2,ASH,1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ONE'S - ASH AC,1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR
	SR1	(135,0,1,0,2,ASH,1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ZERO'S - ASH AC,1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(136,-1,-2,-1,-4,ASH,1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ONE'S - ASH AC,1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(137,100000,0,200000,0,ASH,1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ZERO'S - ASH AC,1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(140,677777,-1,577777,-2,ASH,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ONE'S - ASH AC,1
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(141,400000,0,400000,0,ASH,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ZERO'S - ASH AC,1
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(142,377777,-1,377777,-2,ASH,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ONE'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(143,400000,0,600000,0,ASH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(144,377777,-1,177777,-1,ASH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ONE'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(145,400000,0,600000,0,ASH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(146,377777,-1,177777,-1,ASH,-1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(147,0,4,0,2,ASH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(150,-1,-5,-1,-3,ASH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(151,0,2,0,1,ASH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - ASH AC,-1
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(152,-1,-3,-1,-2,ASH,-1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ONE'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(153,400000,0,700000,0,ASH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 0 OF AR 
	SR1	(154,377777,-1,077777,-1,ASH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ONE'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(155,400000,0,700000,0,ASH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 1 OF AR 
	SR1	(156,377777,-1,077777,-1,ASH,-2)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(157,0,10,0,2,ASH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 34 OF AR 
	SR1	(160,-1,-11,-1,-3,ASH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(161,0,4,0,1,ASH,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - ASH AC,-2
;TEST ABILITY TO SHIFT INTO BIT 35 OF AR 
	SR1	(162,-1,-5,-1,-2,ASH,-2)

SUBTTL	DIAGNOSTIC SECTION - END CONNECTIONS TEST (ROTC)

;END CONNECTIONS-ROTC
;TEST AR-MQ END BIT INPUT GATES
;TEST LEFT-AR0,1,34,35 SHLT INP GATES
;          MQ0,1,34,35 SHLT INP GATES
;TEST RIGHT-AR0,1,34,35 SHRT INP GATES
;	   MQ0,1,34,35 SHRT INPUT GATES
;AC,AC+1 ARE ROTATED LEFT/RIGHT AND
;END BITS ARE TESTED
;TEST ASSUMES BOTH REGISTERS ARE
;CAPABLE OF ROTATING 1,-1 AND -2 BIT POSITIONS CORRECTLY

;SHIFT CONNECTIONS TEST
;TEST MQ35 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 35 OF MQ 
	SR2	(163,400000,0,0,0,0,0,0,1,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST MQ35 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 35 OF MQ
	SR2	(164,377777,-1,-1,-1,-1,-1,-1,-2,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST MQ34 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 34 OF MQ
	SR2	(165,0,0,0,1,0,0,0,2,ROTC,1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST MQ34 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 34 OF MQ 
	SR2	(166,-1,-1,-1,-2,-1,-1,-1,-3,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST MQ1 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 1 OF MQ 
	SR2	(167,0,0,100000,0,0,0,200000,0,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST MQ1 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 1 OF MQ 
	SR2	(170,-1,-1,677777,-1,-1,-1,577777,-1,ROTC,1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST MQ0 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 0 OF MQ 
	SR2	(171,0,0,200000,0,0,0,400000,0,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST MQ0 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 0 OF MQ 
	SR2	(172,-1,-1,577777,-1,-1,-1,377777,-1,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR2	(173,0,0,400000,0,0,1,0,0,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR
	SR2	(174,-1,-1,377777,-1,-1,-2,-1,-1,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR
	SR2	(175,0,1,0,0,0,2,0,0,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR2	(176,-1,-2,-1,-1,-1,-3,-1,-1,ROTC,1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR2	(177,100000,0,0,0,200000,0,0,0,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR2	(200,677777,-1,-1,-1,577777,-1,-1,-1,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ONE'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR2	(201,200000,0,0,0,400000,0,0,0,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHLT INP-ZERO'S - ROTC AC,1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR2	(202,577777,-1,-1,-1,377777,-1,-1,-1,ROTC,1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR2	(203,0,0,0,1,400000,0,0,0,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR2	(204,-1,-1,-1,-2,377777,-1,-1,-1,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR2	(205,400000,0,0,0,200000,0,0,0,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR2	(206,377777,-1,-1,-1,577777,-1,-1,-1,ROTC,-1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR2	(207,0,4,0,0,0,2,0,0,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR2	(210,-1,-5,-1,-1,-1,-3,-1,-1,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR2	(211,0,2,0,0,0,1,0,0,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR2	(212,-1,-3,-1,-1,-1,-2,-1,-1,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST MQ0 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 0 OF MQ 
	SR2	(213,0,1,0,0,0,0,400000,0,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST MQ0 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 0 OF MQ 
	SR2	(214,-1,-2,-1,-1,-1,-1,377777,-1,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST MQ1 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 1 OF MQ 
	SR2	(215,0,0,400000,0,0,0,200000,0,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST MQ1 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 1 OF MQ 
	SR2	(216,-1,-1,377777,-1,-1,-1,577777,-1,ROTC,-1)
PAGE
;SHIFT CONNECTIONS TEST
;TEST MQ34 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 34 OF MQ 
	SR2	(217,0,0,0,4,0,0,0,2,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST MQ34 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 34 OF MQ 
	SR2	(220,-1,-1,-1,-5,-1,-1,-1,-3,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST MQ35 SHRT INP-ONE'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 35 OF MQ 
	SR2	(221,0,0,0,2,0,0,0,1,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST MQ35 SHRT INP-ZERO'S - ROTC AC,-1
;TEST ABILITY TO ROTATE INTO BIT 35 OF MQ 
	SR2	(222,-1,-1,-1,-3,-1,-1,-1,-2,ROTC,-1)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR2	(223,0,0,0,2,400000,0,0,0,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST AR0 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 0 OF AR 
	SR2	(224,-1,-1,-1,-3,377777,-1,-1,-1,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR2	(225,0,0,0,1,200000,0,0,0,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST AR1 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 1 OF AR 
	SR2	(226,-1,-1,-1,-2,577777,-1,-1,-1,ROTC,-2)
PAGE
;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR2	(227,0,10,0,0,0,2,0,0,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST AR34 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 34 OF AR 
	SR2	(230,-1,-11,-1,-1,-1,-3,-1,-1,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR2	(231,0,4,0,0,0,1,0,0,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST AR35 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 35 OF AR 
	SR2	(232,-1,-5,-1,-1,-1,-2,-1,-1,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST MQ0 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 0 OF MQ 
	SR2	(233,0,2,0,0,0,0,400000,0,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST MQ0 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 0 OF MQ 
	SR2	(234,-1,-3,-1,-1,-1,-1,377777,-1,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST MQ1 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 1 OF MQ 
	SR2	(235,0,1,0,0,0,0,200000,0,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST MQ1 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 1 OF MQ 
	SR2	(236,-1,-2,-1,-1,-1,-1,577777,-1,ROTC,-2)
PAGE
;SHIFT CONNECTIONS TEST
;TEST MQ34 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 34 OF MQ 
	SR2	(237,0,0,0,10,0,0,0,2,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST MQ34 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 34 OF MQ 
	SR2	(240,-1,-1,-1,-11,-1,-1,-1,-3,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST MQ35 SHRT INP-ONE'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 35 OF MQ 
	SR2	(241,0,0,0,4,0,0,0,1,ROTC,-2)

;SHIFT CONNECTIONS TEST
;TEST MQ35 SHRT INP-ZERO'S - ROTC AC,-2
;TEST ABILITY TO ROTATE INTO BIT 35 OF MQ 
	SR2	(242,-1,-1,-1,-5,-1,-1,-1,-2,ROTC,-2)

LAST1:	JRST	BEGEND